Skyworks Solutions Inc. SI5338K-B06029-GMR
- Part No.:
- SI5338K-B06029-GMR
- Manufacturer:
- Skyworks Solutions Inc.
- Category:
- Application Specific Clock/Timing
- Package:
- 24-VFQFN Exposed Pad
- Datasheet:
-
SI5338K-B06029-GMR.pdf
- Description:
- I2C CONTROL, 4-OUTPUT, ANY FREQU
- Quantity:
- Payment:

- Shipping:

Inventory:3,452
Please send an inquiry. Send us your inquiry, and we will respond immediately.
Product details
Overview
SI5338K-B06029-GMR from Skyworks Solutions is a quad-output, I²C-programmable clock generator with MultiSynth™ frequency synthesis, delivering four independent low-jitter clocks (0.7 ps RMS typ) across LVPECL/LVDS/HCSL/CMOS/SSTL formats, supporting PCIe Gen 1–4 and Ethernet timing in telecom line cards and FPGA-based systems.
For engineers reviewing the SI5338K-B06029-GMR datasheet, SI5338K-B06029-GMR pinout, SI5338K-B06029-GMR application, or SI5338K-B06029-GMR equivalent, this device enables any-frequency synthesis from 0.16 MHz to 710 MHz per output, supports independent voltage supply per driver (1.5–3.3 V), and provides glitchless 1 ppm frequency adjustment and <20 ps phase step resolution.
Technical Context
The SI5338K-B06029-GMR implements a two-stage PLL architecture: a high-stability reference PLL (loop bandwidth 1.6 MHz) locks to an external crystal (8–30 MHz) or differential/CMOS input (5–710 MHz), feeding four independent MultiSynth™ fractional-N synthesizers. Each synthesizer drives a configurable output stage with programmable format, voltage, and spread-spectrum modulation.
It supports zero-delay mode via external feedback, loss-of-lock and loss-of-signal alarms, and I²C/SMBus configuration with ClockBuilder Pro software. The device operates across –40 to +85 °C with core supply options of 1.8 V, 2.5 V, or 3.3 V and delivers 45 mA typical core current at 100 MHz on all outputs.
Key Specifications
| Parameter | Value and Actual Design Meaning |
|---|---|
| Output Count | Four independent differential or single-ended clock outputs (CLK0A/B through CLK3A/B) |
| Phase Jitter (RMS) | 0.7 ps typical (12 kHz–20 MHz), meeting PCIe Gen 3 SRNS and GbE jitter requirements |
| Frequency Range | 0.16–710 MHz per output, with integer/fractional synthesis and true zero-ppm accuracy |
| Input Flexibility | Supports 8–30 MHz crystal, 5–200 MHz CMOS, 5–350 MHz SSTL/HSTL, or 5–710 MHz differential reference |
| Supply Voltages | Core: 1.8/2.5/3.3 V; Output buffers: independently configurable 1.5/1.8/2.5/3.3 V per driver |
| Package | 24-pin QFN, 4 mm × 4 mm, 0.5 mm pitch, exposed thermal pad |
| Operating Temp | –40 °C to +85 °C ambient, qualified for industrial and telecom infrastructure applications |
Pinout & Package
SI5338K-B06029-GMR is housed in a 24-lead, 4 mm × 4 mm QFN package with wettable flanks and an exposed thermal pad. Pin 1 is located at top-left corner (marked by dot); pin numbering proceeds counterclockwise.
| Pin/Terminal | Circuit Role | Design Meaning |
|---|---|---|
| IN1, IN2, IN5, IN6 | Differential input pairs | Accept 5–710 MHz AC-coupled differential clocks; require external 100 Ω termination |
| IN3, IN4 | Single-ended CMOS inputs | Accept 5–200 MHz DC-coupled signals; VIH = 0.7×VDD, VIL = 0.3×VDD |
| CLK0A–CLK3B | Differential clock outputs | Four independent output pairs; each configurable as LVPECL/LVDS/HCSL/CML/SSTL/HSTL/CMOS |
| VDDO0–VDDO3 | Output buffer supplies | Independent 1.5–3.3 V supplies per output pair; enable mixed-voltage system interfacing |
| VDD | Core supply | 1.8/2.5/3.3 V ±10%; powers PLL, MultiSynth, and control logic |
| SCL, SDA | I²C interface | Standard SMBus-compatible serial bus (up to 400 kHz); supports in-system programming |
| INTR | Interrupt output | Open-drain status indicator for loss-of-lock or loss-of-signal events |
| GND, RSVD_GND | Ground terminals | Eight dedicated ground pins including thermal pad connection; critical for jitter performance |
Key Features
| Feature | Design Value |
|---|---|
| MultiSynth™ synthesis | Enables independent, any-frequency generation on all four outputs with 1 ppb resolution and zero ppm error |
| PCIe Gen 1–4 compliance | Meets Common Clock and Gen 3 SRNS jitter specs (0.11–0.45 ps RMS), validated with Intel Clock Jitter Tool |
| Independent phase control | Programmable initial offset (±45 ns) and fine-grained increment/decrement (<20 ps steps) per output |
| Spread-spectrum modulation | Configurable on any output: 0.5–5.0% spread, 33–63 kHz modulation rate, reducing EMI in dense PCB layouts |
| Flexible input architecture | Five input options (crystal, CMOS, SSTL, HSTL, differential) with automatic detection and seamless switching |
| Low-power operation | 45 mA typical core current at full load; 12 mA in buffer-only mode; optimized for thermal-constrained designs |
Applications
| Ethernet Switch/Routing | PCIe Gen 3/4 Timing |
|---|---|
Use Scenario: High-density 10GbE/25GbE switch fabric requiring synchronized clocks across PHYs, MACs, and packet processors. IC Role / Device Role / Timing Role: Quad clock generator providing independent 156.25 MHz, 312.5 MHz, and 625 MHz clocks with sub-ps jitter for SerDes lanes and management subsystems. Use Value: Eliminates multiple discrete oscillators; ensures deterministic inter-lane skew <100 ps and meets IEEE 802.3bj jitter masks. |
Use Scenario: Server motherboard with dual CPU sockets and multiple PCIe Gen 4 x16 slots demanding strict common-clock jitter compliance. IC Role / Device Role / Timing Role: Primary clock source generating 100 MHz common reference and 100 MHz SRNS clocks with 0.11 ps RMS jitter per PCIe Gen 4 spec. Use Value: Passes Intel Clock Jitter Tool validation; enables single-chip replacement of four oscillators while maintaining Gen 4 link training reliability. |
| Broadcast Video Timing | FPGA/Processor Clocking |
Use Scenario: SMPTE ST 2082-1 (12G-SDI) video router requiring ultra-low-jitter 270 MHz, 74.25 MHz, and 148.5 MHz clocks for encoder/decoder chains. IC Role / Device Role / Timing Role: Any-frequency synthesizer delivering three precisely phase-aligned outputs with <20 ps step resolution for genlock and frame synchronization. Use Value: Achieves <0.7 ps RMS jitter at 148.5 MHz, satisfying SMPTE RP 184 mask and enabling clean eye diagrams at 12 Gbps. |
Use Scenario: Heterogeneous compute platform integrating Xilinx Versal FPGA, ARM SoC, and DDR4 memory controllers with disparate clock domain requirements. IC Role / Device Role / Timing Role: Centralized clock hub generating 500 MHz FPGA logic clock, 1 GHz GTY transceiver reference, 200 MHz DDR4 controller clock, and 100 MHz system management clock. Use Value: Independent voltage per output (1.8 V for DDR4, 1.2 V for GTY, 3.3 V for management) avoids level-shifter components and reduces BOM count. |
Equivalent & Alternatives
The following parts are listed as comparable options for similar quad-output programmable clock generator applications.
| Alternative Part | Technical Difference | Application Difference | Selection Advice |
|---|---|---|---|
| Si5332A-D06089-GM | Higher integration: includes integrated LDOs, enhanced jitter filtering (0.35 ps RMS), and support for up to 10 outputs | Targets higher-end server and AI accelerator boards where ultra-low jitter and multi-rail power simplification are critical | Preferred when replacing legacy Si5338 designs requiring lower jitter or simplified power delivery |
| ICS8430I-01T | Fixed-frequency, non-programmable quad LVDS clock fanout buffer; no synthesis capability; 0.9 ps RMS jitter | Used only in fixed-clock distribution scenarios without frequency translation or flexibility needs | Select only when design requires no I²C configuration and all clocks are static multiples of a single reference |
Compared with Si5332A-D06089-GM, SI5338K-B06029-GMR offers broader input flexibility (crystal + five input types) and lower cost, while ICS8430I-01T lacks programmability entirely-making SI5338K-B06029-GMR the optimal balance of configurability, jitter performance, and cost for mid-tier telecom and embedded systems.
Availability
SI5338K-B06029-GMR is available at Aetrix Electronics and suitable for telecom line cards, PCIe Gen 4 add-in cards, and broadcast video equipment requiring stable component supply, long-term lifecycle support, and traceable sourcing.
Supply support for SI5338K-B06029-GMR includes scheduled delivery planning, volume procurement assistance, BOM continuity management, traceable sourcing, and lifecycle availability coordination for OEM customers, industrial embedded developers, connected-device designers, and electronics production programs.
Manufacturer
Skyworks Solutions is a global leader in analog semiconductors, specializing in RF, timing, and precision analog solutions for wireless infrastructure, aerospace, and high-performance computing markets.
The Si5338 family was designed specifically for high-density, multi-protocol timing consolidation in networking, storage, and FPGA-based systems-replacing multiple discrete oscillators with a single, field-programmable clock generator.
FAQ
What is the primary function of the SI5338K-B06029-GMR?
The SI5338K-B06029-GMR is a quad-output, I²C-programmable clock generator using MultiSynth™ technology to synthesize any frequency from 0.16 MHz to 710 MHz on each output with 0.7 ps RMS typical jitter. It replaces up to four discrete oscillators in systems requiring flexible, low-jitter timing such as PCIe Gen 4 and 10GbE switches. Its role in the SI5338K-B06029-GMR is to deliver independent, programmable clocks with zero ppm frequency error and sub-20 ps phase resolution.
Does the SI5338K-B06029-GMR support PCIe Gen 4 timing requirements?
Yes, the SI5338K-B06029-GMR meets PCIe Gen 4 Common Clock jitter specifications with 0.15–0.45 ps RMS (12 kHz–20 MHz), validated using the Skyworks PCIe Clock Jitter Tool and Intel Clock Jitter Tool v1.6.4. It achieves this with a 1.6 MHz PLL loop bandwidth and supports both Common Clock and SRNS modes. The SI5338K-B06029-GMR is explicitly listed in Skyworks documentation as PCIe Gen 1/2/3/4 compliant.
Can the SI5338K-B06029-GMR generate different output voltages simultaneously?
Yes, the SI5338K-B06029-GMR supports independent output supply voltages (VDDO0–VDDO3) per output pair, allowing simultaneous 1.8 V LVDS, 2.5 V HCSL, and 3.3 V CMOS outputs. Each VDDO pin accepts 1.5–3.63 V, enabling direct interface to mixed-voltage FPGAs, processors, and memory controllers without external level shifters. This capability is confirmed in Table 1 of the datasheet for the SI5338K-B06029-GMR.
What input references does the SI5338K-B06029-GMR accept?
The SI5338K-B06029-GMR accepts five input types: 8–30 MHz crystal (differential), 5–200 MHz CMOS (single-ended on IN3/IN4), 5–350 MHz SSTL/HSTL, and 5–710 MHz differential (on IN1/IN2 or IN5/IN6). Input detection is automatic, and the device supports seamless switching between sources. These capabilities are specified in Section 3.2 and Table 6 of the SI5338K-B06029-GMR datasheet.
How is the SI5338K-B06029-GMR programmed and configured?
The SI5338K-B06029-GMR is programmed via its I²C/SMBus-compatible interface (SCL/SDA pins) using Skyworks' ClockBuilder Pro software, which generates custom configuration files and registers. Configuration can be stored in on-chip OTP NVM for autonomous startup. The SI5338K-B06029-GMR also supports pin-controlled frequency/phase adjustments (PINC/FDEC/OEB) for real-time tuning without host intervention.
SI5338K-B06029-GMR Specifications
- Product attributes
- Attribute value
- Manufacturer:
- Skyworks Solutions Inc.
- Series:
- MultiSynth™
- Package/Case:
- 24-VFQFN Exposed Pad
- Packaging:
- Tape & Reel (TR)
- Product Status:
- Active
- Programmable:
- Not Verified
- PLL:
- -
- Main Purpose:
- -
- Input:
- -
- Output:
- -
- Number of Circuits:
- -
- Ratio - Input:Output:
- -
- Differential - Input:Output:
- -
- Frequency - Max:
- -
- Voltage - Supply:
- -
- Operating Temperature:
- -
- Mounting Type:
- Surface Mount
- Grade:
- -
- Qualification:
- -
- Supplier Device Package:
- 24-QFN (4x4)
SI5338K-B06029-GMR FAQ
1.How can I place an order for SI5338K-B06029-GMR through Aetrix?
Please submit a Request for Quotation (RFQ) for SI5338K-B06029-GMR on Aetrix. Our sales agent will provide a competitive quotation and guide you through the order confirmation once you accept the terms.
2.Are the price and stock information for SI5338K-B06029-GMR reliable?
The price and inventory of SI5338K-B06029-GMR are updated periodically and may fluctuate due to market conditions. Stock and pricing data are typically refreshed every 24 hours. Quotation validity for SI5338K-B06029-GMR is usually 5 days.
3.What payment methods are accepted for SI5338K-B06029-GMR?
We accept Wire Transfer, PayPal, Credit Card, Western Union, MoneyGram, and Escrow for SI5338K-B06029-GMR transactions.
Note: Certain payment methods may incur a processing fee.
4.How is shipping managed for SI5338K-B06029-GMR?
SI5338K-B06029-GMR orders can be shipped via leading logistics carriers, including DHL, UPS, FedEx, TNT, or Registered Mail.
Once your SI5338K-B06029-GMR order is processed, you will receive an email with the shipment details and tracking number.
Note: Tracking information may take up to 24 hours to appear. Express delivery typically takes 3–5 business days.
5.How can I obtain technical support or documentation for SI5338K-B06029-GMR?
For technical support, including SI5338K-B06029-GMR datasheets, pinout diagrams, or application guidance, please contact our engineering support team. They can provide detailed documentation and assistance for your SI5338K-B06029-GMR requirements.
6.How does Aetrix verify that SI5338K-B06029-GMR is sourced from the original manufacturer or authorized distributors?
All SI5338K-B06029-GMR products on Aetrix are procured from qualified distributors and authorized channels. Our dedicated quality assurance team conducts strict verification, including traceability checks and, if necessary, third-party testing. This ensures that SI5338K-B06029-GMR meets industry standards.
7.What is the process for return or replacement of SI5338K-B06029-GMR?
All SI5338K-B06029-GMR units undergo pre-shipment inspection (PSI). If there is an issue with SI5338K-B06029-GMR, returns or replacements are accepted under the following conditions:
1.Quantity discrepancies, incorrect items, or visible external defects (such as breakage or corrosion), acknowledged by Aetrix.
2.The issue is reported within 90 days of delivery.
3.The SI5338K-B06029-GMR part is unused and in its original packaging.
Return procedure for SI5338K-B06029-GMR:
1.Submit a request within 90 days.
2.Obtain a Return Material Authorization (RMA) from Aetrix.
SI5338K-B06029-GMR Tags

-
LMK00334RTVRQ1
Texas Instruments
.jpg)
-
DSC557-0344FI0T
Microchip Technology

-
9FGV0241AKILFT
Renesas

-
9DBL0452CKILFT
Renesas
.jpg)
-
DSC557-0344FL1T
Microchip Technology
-
RC19008AGND#KB0
Renesas
-
RC19008AGND#BB0
Renesas

-
9DB403DGILFT
Renesas

-
9DB233AGILFT
Renesas

-
9DB803DGILFT
Renesas

-
9FGL0851DKILFT
Renesas
-
AB-557-03-HCHC-F-L-C-T
Abracon LLC
Tech Hub
Counterfeit components can hide behind convincing markings and passing basic function tests. This engineering reference covers source traceability, external inspection, X-ray, XRF, electrical testing, …
A practical engineering and sourcing framework covering lifecycle verification, lifetime-buy calculations, replacement qualification, supplier checks and counterfeit-risk controls.
TTL and CMOS logic families differ in thresholds, loading, output drive, power and timing. This engineering guide compares 74HC and 74HCT, calculates noise margins and checks 3.3 V/5 V compatibility.
A practical engineering guide to 3.3V and 5V logic compatibility, input thresholds, resistor dividers, translator ICs, MOSFET level shifting, I2C pull-ups, timing limits and power-sequencing risks.
The 74HC595 uses push-pull logic outputs, while the TPIC6B595 uses 50 V open-drain DMOS sinks for higher-power loads. This guide compares timing, current limits, 3.3 V interfacing, load wiring, thermal…
The 74HC595 converts serial data into eight stable parallel outputs. This guide covers pin functions, shift and storage timing, OE and MR behavior, drive-current limits, cascading, voltage compatibilit…
A technical comparison of level-sensitive latches and edge-triggered flip-flops, covering timing windows, setup and hold limits, master–slave operation, time borrowing, race-through, HDL inference and…
A D latch stores one bit while Enable controls when data can pass. This reference covers gate-level operation, truth tables, transparency, setup and hold timing, LE versus OE, common ICs and practical …
An SR latch stores one bit through cross-coupled feedback. This engineering reference covers NOR and NAND implementations, truth tables, forbidden-state recovery, gated operation, switch debouncing, fa…
Latch circuits retain one bit through feedback. This technical reference covers SR and D latches, truth tables, transparency, timing limits, latch-versus-flip-flop behavior, applications and common log…

