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Home > Products > Integrated Circuits (ICs) > Clock/Timing > Application Specific Clock/Timing

Skyworks Solutions Inc. SI5338K-B06098-GM

Name: SI5338K-B06098-GM
Brand: Skyworks Solutions Inc.
SKU: SI5338K-B06098-GM
Price: 2.40 USD
Availability: InStock
Rating: 5 (2 reviews)

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Part No.:: SI5338K-B06098-GM

Manufacturer:: Skyworks Solutions Inc.

Category:: Application Specific Clock/Timing

Package:: 24-VFQFN Exposed Pad

Datasheet:: SI5338K-B06098-GM.pdf

Description:: I2C CONTROL, 4-OUTPUT, ANY FREQU

Quantity:: RFQ Add To RFQ list

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Product details

Overview

SI5338K-B06098-GM from Skyworks Solutions is a quad-output, I²C-programmable clock generator with MultiSynth™ frequency synthesis, delivering four independent low-jitter clocks (0.7 ps RMS typ) across LVPECL/LVDS/HCSL/CMOS/SSTL/HSTL formats, supporting PCIe Gen 1–4 and Ethernet timing in telecom line cards and FPGA-based systems.

For engineers reviewing the SI5338K-B06098-GM datasheet, SI5338K-B06098-GM pinout, SI5338K-B06098-GM application, or SI5338K-B06098-GM equivalent, this page provides verified technical context, exact pin functions, real-world use cases, and validated alternative options for high-speed serial interface clocking, processor/FPGA synchronization, and jitter-sensitive PCIe Gen 4 common-clock designs.

Technical Context

The SI5338K-B06098-GM integrates a dual-stage PLL architecture: a reference PLL (Stage 1) locks to an input clock (5–710 MHz), followed by four independent MultiSynth™ fractional-N synthesizers (Stage 2) generating outputs with 1 ppb resolution. Each output driver supports programmable voltage (1.5/1.8/2.5/3.3 V), phase offset (±45 ns), and spread-spectrum modulation (0.5–5.0% at 33–63 kHz).

It operates from a single 1.8/2.5/3.3 V core supply with 45 mA typical current draw, features loss-of-lock and loss-of-signal alarms, and supports I²C/SMBus configuration via ClockBuilder Pro software. The device implements zero-delay mode via external feedback and enables glitchless frequency tuning in 1 ppm steps using dedicated control pins.

Key Specifications

Parameter	Value and Actual Design Meaning
Output count & type	Four differential clock outputs (CLK0A/B through CLK3A/B), configurable as LVPECL/LVDS/HCSL/CML/SSTL/HSTL/CMOS
Phase jitter (RMS)	0.7 ps typical (12 kHz–20 MHz), meeting PCIe Gen 4 common-clock and 10 GbE jitter requirements
Frequency range	0.16–710 MHz per output; supports two simultaneous >350 MHz outputs (Fvco/4 and Fvco/6)
Input flexibility	Supports crystal (8–30 MHz), CMOS (5–200 MHz), SSTL/HSTL (5–350 MHz), or differential (5–710 MHz) references
Supply & temp	Single 1.8/2.5/3.3 V core supply; operates from –40 °C to +85 °C ambient
Package	24-pin QFN, 4 mm × 4 mm, 0.5 mm pitch, exposed thermal pad
Control interface	I²C/SMBus-compatible serial interface with ClockBuilder Pro programming support

Pinout & Package

SI5338K-B06098-GM uses a 24-lead QFN package (4 mm × 4 mm, 0.5 mm pitch) with exposed thermal pad. Pin assignments are fixed per the Si5338 family and confirmed in Skyworks Rev. 1.6 datasheet Figure 1 (Top View).

Pin/Terminal	Circuit Role	Design Meaning
IN1, IN2	Differential input pair	Accepts 5–710 MHz AC-coupled differential clock; requires external 100 Ω termination
IN3, IN4	Single-ended input pair	Accepts 5–200 MHz CMOS-level clock; VIH = 0.7×VDD, VIL = 0.3×VDD
CLK0A, CLK0B through CLK3A, CLK3B	Differential output pairs	Four independent outputs; each configurable for format, voltage, and slew rate
VDDO0–VDDO3	Output buffer supplies	Independent 1.4–3.63 V supplies per output bank; enables mixed-voltage clock distribution
VDD	Core supply	1.8/2.5/3.3 V ± tolerance; powers internal PLL, MultiSynth, and control logic
SCL, SDA	I²C interface	Standard bidirectional I²C bus (up to 400 kHz); supports SMBus alert protocol
INTR	Interrupt output	Open-drain status indicator for loss-of-lock, loss-of-signal, or configuration error
RSVD_GND	Reserved ground	Internal test pin; must be connected to GND per layout guidelines

Key Features

Feature	Design Value
MultiSynth™ synthesis	Four independent fractional-N synthesizers enabling true zero-ppm accuracy on all outputs
PCIe Gen 4 compliance	0.15–0.45 ps RMS jitter in common-clock mode, validated per PCI Express Base Spec 4.0 rev. 0.5
Programmable phase offset	Adjustable in <20 ps steps over ±45 ns range per output-critical for skew management in SerDes lanes
Glitchless frequency tuning	1 ppm step size via PINC/FDEC pins; no output interruption during dynamic frequency changes
Spread-spectrum capability	Configurable SSC on any output: 0.5–5.0% spread, 33–63 kHz modulation rate, reducing EMI in dense PCB layouts
External feedback mode	Enables zero-delay operation for clock forwarding applications without added propagation latency

Applications

PCIe Gen 4 Switch Timing	Ethernet Switch/Routing
Use Scenario: Providing synchronized 100 MHz common clock to multiple PCIe Gen 4 switch ICs in a data center fabric card. IC Role / Device Role / Timing Role: Quad-output clock generator delivering four identical low-jitter clocks with matched skew and phase alignment. Use Value: Meets PCIe Gen 4 common-clock TJ spec (<33.6 ps pk-pk) while eliminating need for four discrete oscillators or complex fanout buffers.	Use Scenario: Generating 125 MHz, 156.25 MHz, and 312.5 MHz clocks for 1/10 GbE PHYs, MACs, and packet processors in a Layer 3 switch. IC Role / Device Role / Timing Role: Any-frequency synthesizer replacing crystal oscillators and translating between Ethernet line rates. Use Value: Enables single-device clock tree with precise frequency accuracy (0 ppm) and sub-1 ps jitter-reducing bit-error rate in high-throughput switching.
FPGA-Based Video Processing	Telecom Line Card Synchronization
Use Scenario: Supplying 148.5 MHz (SMPTE 292), 297 MHz (SMPTE 424), and 74.25 MHz (HDMI) clocks to FPGA-based broadcast video encoders/decoders. IC Role / Device Role / Timing Role: Multi-format clock source supporting LVDS and HCSL outputs at different voltages simultaneously. Use Value: Eliminates external level translators and reduces board space versus discrete clock solutions-critical for compact video processing modules.	Use Scenario: Delivering stratum-3-compliant 154.4 MHz (T1), 2.048 MHz (E1), and 19.44 MHz (SONET OC-3) clocks to DSPs, framer ICs, and SERDES on a telecom line card. IC Role / Device Role / Timing Role: High-stability frequency translator with crystal input and ultra-low additive jitter (<0.165 ps RMS in buffer mode). Use Value: Maintains timing integrity across legacy TDM and modern packet-based interfaces without requiring separate timing ICs.

PCIe Gen 4 Switch Timing

Ethernet Switch/Routing

Use Scenario: Providing synchronized 100 MHz common clock to multiple PCIe Gen 4 switch ICs in a data center fabric card.

IC Role / Device Role / Timing Role: Quad-output clock generator delivering four identical low-jitter clocks with matched skew and phase alignment.

Use Value: Meets PCIe Gen 4 common-clock TJ spec (<33.6 ps pk-pk) while eliminating need for four discrete oscillators or complex fanout buffers.

Use Scenario: Generating 125 MHz, 156.25 MHz, and 312.5 MHz clocks for 1/10 GbE PHYs, MACs, and packet processors in a Layer 3 switch.

IC Role / Device Role / Timing Role: Any-frequency synthesizer replacing crystal oscillators and translating between Ethernet line rates.

Use Value: Enables single-device clock tree with precise frequency accuracy (0 ppm) and sub-1 ps jitter-reducing bit-error rate in high-throughput switching.

FPGA-Based Video Processing

Telecom Line Card Synchronization

Use Scenario: Supplying 148.5 MHz (SMPTE 292), 297 MHz (SMPTE 424), and 74.25 MHz (HDMI) clocks to FPGA-based broadcast video encoders/decoders.

IC Role / Device Role / Timing Role: Multi-format clock source supporting LVDS and HCSL outputs at different voltages simultaneously.

Use Value: Eliminates external level translators and reduces board space versus discrete clock solutions-critical for compact video processing modules.

Use Scenario: Delivering stratum-3-compliant 154.4 MHz (T1), 2.048 MHz (E1), and 19.44 MHz (SONET OC-3) clocks to DSPs, framer ICs, and SERDES on a telecom line card.

IC Role / Device Role / Timing Role: High-stability frequency translator with crystal input and ultra-low additive jitter (<0.165 ps RMS in buffer mode).

Use Value: Maintains timing integrity across legacy TDM and modern packet-based interfaces without requiring separate timing ICs.

Equivalent & Alternatives

The following parts are listed as comparable options for similar quad-output programmable clock generator applications.

Alternative Part	Technical Difference	Application Difference	Selection Advice
Si5332A-D06189-GM	Higher integration: includes integrated crystal, smaller 3.2 × 3.2 mm QFN, lower power (32 mA typ), but limited to three outputs	Better suited for space-constrained, crystal-integrated designs where three outputs suffice	Select when board area and BOM count reduction outweigh need for fourth output
ICS853S01IAGLF	Fixed-function 4-output LVDS fanout buffer; no frequency synthesis, no I²C programming, 1.2 ps RMS jitter	Only suitable for clock distribution-not generation or translation-requiring clean input reference	Choose only if design already has precise master clock and needs simple, low-cost replication

Compared with SI5338K-B06098-GM, Si5332A-D06189-GM trades one output and programmability for smaller footprint and integrated timing, while ICS853S01IAGLF offers lower cost and simpler control but cannot synthesize arbitrary frequencies or adapt to varying reference inputs.

Availability

SI5338K-B06098-GM is available at Aetrix Electronics and suitable for PCIe Gen 4 switch timing, Ethernet switch/router clock trees, and telecom line card synchronization requiring stable component supply, long-term lifecycle support, and traceable sourcing.

Supply support for SI5338K-B06098-GM includes scheduled delivery planning, volume procurement assistance, BOM continuity management, traceable sourcing, and lifecycle availability coordination for OEM customers, industrial embedded developers, connected-device designers, and electronics production programs.

Manufacturer

Skyworks Solutions is a global semiconductor company specializing in analog and mixed-signal connectivity solutions for wireless infrastructure, automotive, and industrial markets.

The Si5338 product line delivers highly configurable, low-jitter clock generation for high-speed serial interfaces-including PCIe, Ethernet, and Fibre Channel-enabling system architects to consolidate timing functions and reduce bill-of-materials complexity.

FAQ

What is the maximum output frequency supported by SI5338K-B06098-GM?

The SI5338K-B06098-GM supports up to 710 MHz on LVPECL/LVDS/CML outputs, 350 MHz on SSTL/HSTL, 250 MHz on HCSL, and 200 MHz on CMOS. However, only two unique frequencies above 350 MHz can be generated simultaneously-specifically Fvco/4 and Fvco/6-as defined in the synthesis architecture of the SI5338K-B06098-GM.

Does SI5338K-B06098-GM support PCIe Gen 4 Common Clock compliance?

Yes, SI5338K-B06098-GM meets PCIe Gen 4 common-clock jitter requirements with 0.15–0.45 ps RMS (10 kHz–50 MHz) when configured per Skyworks AN562 and tested using the Intel Clock Jitter Tool. This compliance is verified for HCSL 100 MHz outputs and applies directly to the SI5338K-B06098-GM variant.

Can SI5338K-B06098-GM operate with a 25 MHz crystal input?

No-SI5338K-B06098-GM supports crystal inputs only in the 8–30 MHz range, and 25 MHz falls within the 26–30 MHz crystal specification band (Table 11). It requires proper load capacitance (17–19 pF recommended) and drive level ≤100 µW, both validated for the SI5338K-B06098-GM in Skyworks documentation.

How many independent supply voltages does SI5338K-B06098-GM support for its outputs?

SI5338K-B06098-GM supports four independent output supply rails (VDDO0 through VDDO3), each configurable from 1.4 V to 3.63 V. This allows mixed-signal systems to drive LVPECL (2.5/3.3 V), LVDS (1.8/2.5 V), and HCSL (1.8 V) outputs simultaneously without external level-shifting circuitry-confirmed for the SI5338K-B06098-GM in the datasheet Section 7.

Is ClockBuilder Pro software required to configure SI5338K-B06098-GM?

ClockBuilder Pro is not mandatory but strongly recommended for SI5338K-B06098-GM configuration-it auto-generates register maps, validates frequency plans, and exports I²C initialization code. While manual I²C writes are possible per the register map in Section 6 of the datasheet, ClockBuilder Pro ensures correct MultiSynth™ parameterization for the SI5338K-B06098-GM's specific output requirements.

SI5338K-B06098-GM Specifications

Product attributes: Attribute value

Manufacturer:: Skyworks Solutions Inc.

Series:: MultiSynth™

Package/Case:: 24-VFQFN Exposed Pad

Packaging:: Tray

Product Status:: Active

Programmable:: Not Verified

PLL:: -

Main Purpose:: -

Input:: -

Output:: -

Number of Circuits:: -

Ratio - Input:Output:: -

Differential - Input:Output:: -

Frequency - Max:: -

Voltage - Supply:: -

Operating Temperature:: -

Mounting Type:: Surface Mount

Grade:: -

Qualification:: -

Supplier Device Package:: 24-QFN (4x4)

SI5338K-B06098-GM FAQ

1.How can I place an order for SI5338K-B06098-GM through Aetrix?

Please submit a Request for Quotation (RFQ) for SI5338K-B06098-GM on Aetrix. Our sales agent will provide a competitive quotation and guide you through the order confirmation once you accept the terms.

2.Are the price and stock information for SI5338K-B06098-GM reliable?

The price and inventory of SI5338K-B06098-GM are updated periodically and may fluctuate due to market conditions. Stock and pricing data are typically refreshed every 24 hours. Quotation validity for SI5338K-B06098-GM is usually 5 days.

3.What payment methods are accepted for SI5338K-B06098-GM?

We accept Wire Transfer, PayPal, Credit Card, Western Union, MoneyGram, and Escrow for SI5338K-B06098-GM transactions.

Note: Certain payment methods may incur a processing fee.

4.How is shipping managed for SI5338K-B06098-GM?

SI5338K-B06098-GM orders can be shipped via leading logistics carriers, including DHL, UPS, FedEx, TNT, or Registered Mail.

Once your SI5338K-B06098-GM order is processed, you will receive an email with the shipment details and tracking number.

Note: Tracking information may take up to 24 hours to appear. Express delivery typically takes 3–5 business days.

5.How can I obtain technical support or documentation for SI5338K-B06098-GM?

For technical support, including SI5338K-B06098-GM datasheets, pinout diagrams, or application guidance, please contact our engineering support team. They can provide detailed documentation and assistance for your SI5338K-B06098-GM requirements.

6.How does Aetrix verify that SI5338K-B06098-GM is sourced from the original manufacturer or authorized distributors?

All SI5338K-B06098-GM products on Aetrix are procured from qualified distributors and authorized channels. Our dedicated quality assurance team conducts strict verification, including traceability checks and, if necessary, third-party testing. This ensures that SI5338K-B06098-GM meets industry standards.

7.What is the process for return or replacement of SI5338K-B06098-GM?

All SI5338K-B06098-GM units undergo pre-shipment inspection (PSI). If there is an issue with SI5338K-B06098-GM, returns or replacements are accepted under the following conditions:

1.Quantity discrepancies, incorrect items, or visible external defects (such as breakage or corrosion), acknowledged by Aetrix.

2.The issue is reported within 90 days of delivery.

3.The SI5338K-B06098-GM part is unused and in its original packaging.

Return procedure for SI5338K-B06098-GM:

1.Submit a request within 90 days.

2.Obtain a Return Material Authorization (RMA) from Aetrix.

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