Send an Inquiry

To receive a quote for your project, please fill in the following information, and we’ll get back to you promptly.

Submit Inventory List

Please fill in the following information, and we’ll get back to you promptly.

Home > Products > Integrated Circuits (ICs) > Clock/Timing > Application Specific Clock/Timing

Skyworks Solutions Inc. SI5338K-B10419-GMR

Name: SI5338K-B10419-GMR
Brand: Skyworks Solutions Inc.
SKU: SI5338K-B10419-GMR
Price: 2.40 USD
Availability: InStock
Rating: 5 (2 reviews)

Compare

Part No.:: SI5338K-B10419-GMR

Manufacturer:: Skyworks Solutions Inc.

Category:: Application Specific Clock/Timing

Package:: -

Datasheet:: SI5338K-B10419-GMR.pdf

Description:: IC CLOCK GENERATOR QUAD 24QFN

Quantity:: RFQ Add To RFQ list

Payment:

Shipping:

Inventory:4,910

Please send an inquiry. Send us your inquiry, and we will respond immediately.

Product details

Overview

SI5338K-B10419-GMR from Skyworks Solutions is an I²C-programmable quad clock generator with four independent differential output drivers, 0.7 ps RMS typical phase jitter, PCIe Gen 1–4 and SRNS compliance, and support for LVPECL/LVDS/HCSL/CMOS/SSTL/HSTL output formats across 0.16–710 MHz. It replaces up to four crystal oscillators in high-speed serial interface timing applications such as PCIe root complexes and Ethernet switch fabric.

For engineers reviewing the SI5338K-B10419-GMR datasheet, SI5338K-B10419-GMR pinout, SI5338K-B10419-GMR application, or SI5338K-B10419-GMR equivalent, key selection considerations include its MultiSynth™ fractional-N synthesis architecture, per-output voltage configuration (1.5/1.8/2.5/3.3 V), independent phase/frequency adjustment (±45 ns / 1 ppm steps), spread-spectrum capability (0.5–5.0% down-spread), and 24-QFN 4×4 mm package with 24-pin terminal mapping.

Technical Context

The SI5338K-B10419-GMR implements a two-stage PLL architecture: a high-stability reference stage (with crystal or external clock input) feeding a programmable MultiSynth™ VCO-based synthesis stage that generates four independent output clocks. Each output path includes configurable dividers, format-selectable drivers, and per-output supply rails (VDDO0–VDDO3).

It supports flexible reference inputs - including 8–30 MHz crystals, 5–200 MHz CMOS, 5–350 MHz SSTL/HSTL, and 5–710 MHz differential - and enables zero-delay mode via external feedback. Loss-of-lock and loss-of-signal alarms provide real-time status monitoring over the I²C/SMBus interface.

Key Specifications

Parameter	Value and Actual Design Meaning
Phase Jitter (RMS)	0.7 ps typ (12 kHz–20 MHz); meets PCIe Gen 3 SRNS and Gen 4 common clock jitter requirements
Output Frequency Range	0.16–710 MHz per channel; supports LVPECL/LVDS up to 710 MHz, HCSL up to 250 MHz, CMOS up to 200 MHz
Input Reference Support	Crystal (8–30 MHz), CMOS (5–200 MHz), SSTL/HSTL (5–350 MHz), differential (5–710 MHz)
Supply Voltages	Core: 1.8/2.5/3.3 V; Output buffers: independently configurable 1.5/1.8/2.5/3.3 V per driver
Package	24-pin QFN, 4 × 4 mm, 0.5 mm pitch; RoHS-compliant, moisture sensitivity level 3
Operating Temperature	–40 °C to +85 °C ambient; qualified for industrial and telecom line card environments
Power Consumption	45 mA typ core current at 100 MHz on all outputs with 25 MHz reference

Pinout & Package

SI5338K-B10419-GMR is housed in a 24-lead QFN package (4 mm × 4 mm, 0.5 mm pitch) with exposed thermal pad. Pin assignments are fixed per the Si5338 family: IN1/IN2 (diff clk 1), IN3/IN4 (SE clk 1/2), IN5/IN6 (diff clk 2/3), CLK0A/CLK0B through CLK3A/CLK3B (four differential output pairs), VDD (core supply), VDDO0–VDDO3 (output buffer supplies), SCL/SDA/INTR (I²C interface), and RSVD_GND (reserved ground).

Pin/Terminal	Circuit Role	Design Meaning
IN1, IN2	Differential reference input 1	Accepts 5–710 MHz AC-coupled differential clock; internal 100 Ω termination enabled
IN3, IN4	Single-ended reference inputs	Support 5–200 MHz CMOS; VIH = 0.7×VDD, VIL = 0.3×VDD; 4 pF input capacitance
CLK0A, CLK0B – CLK3A, CLK3B	Differential clock outputs (4 pairs)	Configurable per-channel format (LVPECL/LVDS/HCSL/CML) and voltage (1.5–3.3 V)
VDDO0 – VDDO3	Output buffer supply rails	Independent 1.5/1.8/2.5/3.3 V supplies per output pair; decoupling required per rail
SCL, SDA, INTR	I²C control interface	Standard SMBus-compatible 100/400 kHz operation; INTR is open-drain interrupt output

Key Features

Feature	Design Value
MultiSynth™ synthesis	Four independent fractional-N synthesizers enabling any-frequency generation with true 0 ppm accuracy per output
Per-output voltage configuration	Each of four output drivers supports independent 1.5 V, 1.8 V, 2.5 V, or 3.3 V supply for mixed-voltage system interfacing
Glitchless frequency tuning	1 ppm step size with pin-controlled increment/decrement; update time ≤667 ns above 18 MHz
Programmable phase offset	±45 ns range in <20 ps steps; enables precise skew alignment between high-speed serial lanes
Spread-spectrum clocking	Configurable 0.5–5.0% down-spread at 33–63 kHz modulation rate on any output to reduce EMI

Applications

PCIe Gen 3/4 Root Complex	Ethernet Switch Fabric Timing
Use Scenario: Providing synchronized 100 MHz reference clocks to multiple PCIe endpoints and switches in server backplanes. IC Role / Device Role / Timing Role: Quad-output common clock generator meeting PCIe Gen 3 SRNS and Gen 4 jitter specs (≤0.32 ps RMS). Use Value: Eliminates need for four discrete oscillators; reduces board area and BOM count while ensuring deterministic inter-lane skew <100 ps.	Use Scenario: Delivering low-jitter 125 MHz, 156.25 MHz, and 312.5 MHz clocks to 1/10 GbE PHYs and packet processors in Layer-2/Layer-3 switches. IC Role / Device Role / Timing Role: Programmable any-frequency clock source supporting IEEE 802.3 standards with <0.7 ps RMS jitter. Use Value: Enables single-device timing for multi-rate Ethernet interfaces; simplifies layout with differential LVDS outputs and independent VDDO rails.
Broadcast Video Synchronization	FPGA/ASIC Clock Domain Bridging
Use Scenario: Generating SMPTE ST 2082 (12G-SDI) 594 MHz, ST 2081 (6G-SDI) 297 MHz, and auxiliary 27 MHz clocks from a single 27 MHz crystal reference. IC Role / Device Role / Timing Role: High-precision quad clock synthesizer with sub-ps jitter and integer-mode MultiSynth™ for broadcast-grade stability. Use Value: Replaces multiple crystal oscillators and fanout buffers; maintains frame-accurate sync across HD/4K/8K video processing pipelines.	Use Scenario: Supplying distinct clocks (e.g., 100 MHz AXI, 200 MHz DDR, 300 MHz transceiver, 500 MHz logic) to heterogeneous FPGA domains from one device. IC Role / Device Role / Timing Role: Configurable quad clock generator with independent output format/voltage per domain (LVDS, HCSL, CMOS). Use Value: Reduces power and routing complexity versus discrete clock ICs; supports dynamic frequency scaling via I²C command.

PCIe Gen 3/4 Root Complex

Ethernet Switch Fabric Timing

Use Scenario: Providing synchronized 100 MHz reference clocks to multiple PCIe endpoints and switches in server backplanes.

IC Role / Device Role / Timing Role: Quad-output common clock generator meeting PCIe Gen 3 SRNS and Gen 4 jitter specs (≤0.32 ps RMS).

Use Value: Eliminates need for four discrete oscillators; reduces board area and BOM count while ensuring deterministic inter-lane skew <100 ps.

Use Scenario: Delivering low-jitter 125 MHz, 156.25 MHz, and 312.5 MHz clocks to 1/10 GbE PHYs and packet processors in Layer-2/Layer-3 switches.

IC Role / Device Role / Timing Role: Programmable any-frequency clock source supporting IEEE 802.3 standards with <0.7 ps RMS jitter.

Use Value: Enables single-device timing for multi-rate Ethernet interfaces; simplifies layout with differential LVDS outputs and independent VDDO rails.

Broadcast Video Synchronization

FPGA/ASIC Clock Domain Bridging

Use Scenario: Generating SMPTE ST 2082 (12G-SDI) 594 MHz, ST 2081 (6G-SDI) 297 MHz, and auxiliary 27 MHz clocks from a single 27 MHz crystal reference.

IC Role / Device Role / Timing Role: High-precision quad clock synthesizer with sub-ps jitter and integer-mode MultiSynth™ for broadcast-grade stability.

Use Value: Replaces multiple crystal oscillators and fanout buffers; maintains frame-accurate sync across HD/4K/8K video processing pipelines.

Use Scenario: Supplying distinct clocks (e.g., 100 MHz AXI, 200 MHz DDR, 300 MHz transceiver, 500 MHz logic) to heterogeneous FPGA domains from one device.

IC Role / Device Role / Timing Role: Configurable quad clock generator with independent output format/voltage per domain (LVDS, HCSL, CMOS).

Use Value: Reduces power and routing complexity versus discrete clock ICs; supports dynamic frequency scaling via I²C command.

Equivalent & Alternatives

The following parts are listed as comparable options for similar quad clock generator applications.

Alternative Part	Technical Difference	Application Difference	Selection Advice
Si5332A-D06414-GM	Higher integration: 6 outputs, integrated LDOs, lower jitter (0.35 ps RMS), supports JESD204B deterministic latency	Targeted at JESD204B ADC/DAC timing and 5G wireless infrastructure where deterministic delay matters	Choose when >4 outputs, ultra-low jitter, or JESD204B compliance are required; not drop-in compatible due to different pinout and register map
ICS8430I-01T	Fixed-frequency 4-output LVDS generator; no I²C programming; 1.2 ps RMS jitter; 3.3 V only	Cost-sensitive applications requiring static clock trees without frequency agility	Choose for simple, low-cost clock fanout where programmability and multi-format support are unnecessary

Compared with Si5332A-D06414-GM and ICS8430I-01T, SI5338K-B10419-GMR delivers optimal balance of programmability, jitter performance, and output flexibility for PCIe, Ethernet, and broadcast systems-without requiring LDOs or sacrificing I²C configurability.

Availability

SI5338K-B10419-GMR is available at Aetrix Electronics and suitable for PCIe Gen 4 root complexes, 10 GbE switch fabric timing, and broadcast video synchronization requiring stable component supply, long-term lifecycle support, and traceable sourcing.

Supply support for SI5338K-B10419-GMR includes scheduled delivery planning, volume procurement assistance, BOM continuity management, traceable sourcing, and lifecycle availability coordination for OEM customers, industrial embedded developers, connected-device designers, and electronics production programs.

Manufacturer

Skyworks Solutions is a global semiconductor company specializing in analog and mixed-signal connectivity solutions for wireless, broadband, automotive, and industrial markets.

The Si5338 product line was designed to replace multiple discrete oscillators and clock buffers in high-speed digital systems, delivering programmable, low-jitter timing with minimal footprint and power.

FAQ

What is the maximum output frequency supported by SI5338K-B10419-GMR in LVPECL mode?

The SI5338K-B10419-GMR supports LVPECL output frequencies up to 710 MHz. This capability is validated per Table 6 of the datasheet and applies when using differential outputs with appropriate termination. The device achieves this using its MultiSynth™ VCO architecture with Fvco/4 and Fvco/6 synthesis paths, enabling two unique frequencies above 350 MHz simultaneously. SI5338K-B10419-GMR maintains 0.7 ps RMS jitter even at these high rates when driven by a low-noise reference.

Does SI5338K-B10419-GMR support PCIe Gen 4 Common Clock compliance?

Yes, SI5338K-B10419-GMR meets PCIe Gen 4 Common Clock jitter specifications with ≤0.45 ps RMS (10 kHz–50 MHz) when configured per AN562 guidelines. Its phase noise profile and MultiSynth™ architecture ensure compliance under standard operating conditions (VDD = 3.3 V, TA = 25 °C). SI5338K-B10419-GMR also supports Gen 3 SRNS mode with ≤0.32 ps RMS jitter, verified using the Skyworks PCIe Clock Jitter Tool.

Can SI5338K-B10419-GMR generate four different output frequencies simultaneously?

Yes, SI5338K-B10419-GMR synthesizes four independent output frequencies simultaneously using its four dedicated MultiSynth™ engines. Each output can be set to any frequency within its supported range (e.g., 100 MHz, 125 MHz, 156.25 MHz, 312.5 MHz) with true 0 ppm precision. SI5338K-B10419-GMR allows full per-output configuration of format, voltage, and spread-spectrum parameters without cross-talk or shared divider constraints.

What reference inputs does SI5338K-B10419-GMR accept?

SI5338K-B10419-GMR accepts multiple reference types: 8–30 MHz crystals (differential), 5–200 MHz CMOS (single-ended on IN3/IN4), 5–350 MHz SSTL/HSTL (single-ended), and 5–710 MHz differential signals (on IN1/IN2 or IN5/IN6). All references feed the same PLL stage, and the device automatically detects loss-of-signal with 2.6–5 µs response time. SI5338K-B10419-GMR requires no external components for crystal drive beyond recommended load capacitors.

Is SI5338K-B10419-GMR pin-compatible with other Si5338 variants?

Yes, SI5338K-B10419-GMR shares the identical 24-QFN package and pinout with all Si5338 family members, including Si5338A/B/C/D/E/F/G/H/I/J/K/L/M/N/O/P/Q/R/S/T/U/V/W/X/Y/Z variants. Firmware and register configuration differ by variant, but PCB layout, decoupling, and signal routing are fully interchangeable. SI5338K-B10419-GMR uses the same VDD, VDDOx, CLKx, and I²C pin assignments defined in Section 8 of the datasheet.

SI5338K-B10419-GMR Specifications

Product attributes: Attribute value

Manufacturer:: Skyworks Solutions Inc.

Series:: *

Package/Case:: -

Packaging:: Tape & Reel (TR)

Product Status:: Active

Programmable:: Not Verified

PLL:: -

Main Purpose:: -

Input:: -

Output:: -

Number of Circuits:: -

Ratio - Input:Output:: -

Differential - Input:Output:: -

Frequency - Max:: -

Voltage - Supply:: -

Operating Temperature:: -

Mounting Type:: -

Grade:: -

Qualification:: -

Supplier Device Package:: -

SI5338K-B10419-GMR FAQ

1.How can I place an order for SI5338K-B10419-GMR through Aetrix?

Please submit a Request for Quotation (RFQ) for SI5338K-B10419-GMR on Aetrix. Our sales agent will provide a competitive quotation and guide you through the order confirmation once you accept the terms.

2.Are the price and stock information for SI5338K-B10419-GMR reliable?

The price and inventory of SI5338K-B10419-GMR are updated periodically and may fluctuate due to market conditions. Stock and pricing data are typically refreshed every 24 hours. Quotation validity for SI5338K-B10419-GMR is usually 5 days.

3.What payment methods are accepted for SI5338K-B10419-GMR?

We accept Wire Transfer, PayPal, Credit Card, Western Union, MoneyGram, and Escrow for SI5338K-B10419-GMR transactions.

Note: Certain payment methods may incur a processing fee.

4.How is shipping managed for SI5338K-B10419-GMR?

SI5338K-B10419-GMR orders can be shipped via leading logistics carriers, including DHL, UPS, FedEx, TNT, or Registered Mail.

Once your SI5338K-B10419-GMR order is processed, you will receive an email with the shipment details and tracking number.

Note: Tracking information may take up to 24 hours to appear. Express delivery typically takes 3–5 business days.

5.How can I obtain technical support or documentation for SI5338K-B10419-GMR?

For technical support, including SI5338K-B10419-GMR datasheets, pinout diagrams, or application guidance, please contact our engineering support team. They can provide detailed documentation and assistance for your SI5338K-B10419-GMR requirements.

6.How does Aetrix verify that SI5338K-B10419-GMR is sourced from the original manufacturer or authorized distributors?

All SI5338K-B10419-GMR products on Aetrix are procured from qualified distributors and authorized channels. Our dedicated quality assurance team conducts strict verification, including traceability checks and, if necessary, third-party testing. This ensures that SI5338K-B10419-GMR meets industry standards.

7.What is the process for return or replacement of SI5338K-B10419-GMR?

All SI5338K-B10419-GMR units undergo pre-shipment inspection (PSI). If there is an issue with SI5338K-B10419-GMR, returns or replacements are accepted under the following conditions:

1.Quantity discrepancies, incorrect items, or visible external defects (such as breakage or corrosion), acknowledged by Aetrix.

2.The issue is reported within 90 days of delivery.

3.The SI5338K-B10419-GMR part is unused and in its original packaging.

Return procedure for SI5338K-B10419-GMR:

1.Submit a request within 90 days.

2.Obtain a Return Material Authorization (RMA) from Aetrix.

Tech Hub

2026-09-09 Counterfeit Electronic Components: How to Detect, Authenticate, and Test Suspect Parts

Counterfeit components can hide behind convincing markings and passing basic function tests. This engineering reference covers source traceability, external inspection, X-ray, XRF, electrical testing, …

2026-09-08 Obsolete Electronic Components: How to Source and Evaluate Replacements

A practical engineering and sourcing framework covering lifecycle verification, lifetime-buy calculations, replacement qualification, supplier checks and counterfeit-risk controls.

2026-09-07 TTL vs CMOS Logic Levels: 74HC and 74HCT Compatibility Explained

TTL and CMOS logic families differ in thresholds, loading, output drive, power and timing. This engineering guide compares 74HC and 74HCT, calculates noise margins and checks 3.3 V/5 V compatibility.

2026-09-04 Logic Level Shifter: How to Connect 3.3V and 5V Logic Safely

A practical engineering guide to 3.3V and 5V logic compatibility, input thresholds, resistor dividers, translator ICs, MOSFET level shifting, I2C pull-ups, timing limits and power-sequencing risks.

2026-09-03 74HC595 vs TPIC6B595: Output Drive, Pinout, Current, and Load Selection

The 74HC595 uses push-pull logic outputs, while the TPIC6B595 uses 50 V open-drain DMOS sinks for higher-power loads. This guide compares timing, current limits, 3.3 V interfacing, load wiring, thermal…

2026-09-02 74HC595 Pinout, Timing, Output Current, and Applications

The 74HC595 converts serial data into eight stable parallel outputs. This guide covers pin functions, shift and storage timing, OE and MR behavior, drive-current limits, cascading, voltage compatibilit…

2026-09-01 Latch vs Flip-Flop: Timing, Differences and Design Choices

A technical comparison of level-sensitive latches and edge-triggered flip-flops, covering timing windows, setup and hold limits, master–slave operation, time borrowing, race-through, HDL inference and…

2026-08-30 D Latch Circuit: Truth Table, Timing, ICs and Applications

A D latch stores one bit while Enable controls when data can pass. This reference covers gate-level operation, truth tables, transparency, setup and hold timing, LE versus OE, common ICs and practical …

2026-08-28 SR Latch Explained: NOR and NAND Circuits, Truth Tables, and Applications

An SR latch stores one bit through cross-coupled feedback. This engineering reference covers NOR and NAND implementations, truth tables, forbidden-state recovery, gated operation, switch debouncing, fa…

2026-08-27 Latch Circuit: SR and D Latches, Truth Tables, Timing, and Applications

Latch circuits retain one bit through feedback. This technical reference covers SR and D latches, truth tables, transparency, timing limits, latch-versus-flip-flop behavior, applications and common log…