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Home > Products > Integrated Circuits (ICs) > Clock/Timing > Application Specific Clock/Timing

Skyworks Solutions Inc. SI5338K-B10518-GM

Name: SI5338K-B10518-GM
Brand: Skyworks Solutions Inc.
SKU: SI5338K-B10518-GM
Price: 2.40 USD
Availability: InStock
Rating: 5 (2 reviews)

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Part No.:: SI5338K-B10518-GM

Manufacturer:: Skyworks Solutions Inc.

Category:: Application Specific Clock/Timing

Package:: -

Datasheet:: SI5338K-B10518-GM.pdf

Description:: IC CLOCK GENERATOR QUAD 24QFN

Quantity:: RFQ Add To RFQ list

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Inventory:1,666

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Product details

Overview

SI5338K-B10518-GM from Skyworks Solutions is an I²C-programmable quad clock generator with four independently configurable differential or single-ended outputs, 0.7 ps RMS typical phase jitter, PCIe Gen 1–4 Common Clock and Gen 3 SRNS compliance, and operation across –40 to +85 °C. It replaces up to four crystal oscillators in Ethernet switch/router, processor/FPGA clocking, and broadcast video timing systems.

For engineers reviewing the SI5338K-B10518-GM datasheet, SI5338K-B10518-GM pinout, SI5338K-B10518-GM application, or SI5338K-B10518-GM equivalent, this page delivers verified specifications, validated pin functions, confirmed PCIe/10GbE timing compliance, and real-world alternative part guidance for high-speed serial interface clock design.

Technical Context

The SI5338K-B10518-GM implements a dual-stage synthesis architecture: a primary PLL with 1.6 MHz loop bandwidth locks to one of six input references (crystal, CMOS, SSTL/HSTL, or differential), followed by four independent MultiSynth™ fractional-N dividers per output channel. Each output supports integer or fractional frequency synthesis with true zero-ppm accuracy and <20 ps programmable phase step resolution.

It features full I²C/SMBus register access for dynamic frequency increment/decrement (1 ppm steps), spread-spectrum control (0.5–5.0% deviation, 33–63 kHz modulation), loss-of-lock/loss-of-signal alarms, and independent output voltage selection (1.5/1.8/2.5/3.3 V) per driver - enabling mixed-signal SoC clock tree integration without external level-shifting.

Key Specifications

Parameter	Value and Actual Design Meaning
Phase Jitter (RMS)	0.7 ps typ (12 kHz–20 MHz); meets PCIe Gen 3 SRNS & Gen 4 common clock jitter requirements
Output Channels	4 independent outputs: supports LVPECL/LVDS/HCSL/CMOS/SSTL/HSTL formats simultaneously
Frequency Range	0.16–710 MHz per output; supports >350 MHz on two outputs concurrently (Fvco/4 & Fvco/6)
Input Reference Support	Crystal (8–30 MHz), CMOS (5–200 MHz), SSTL/HSTL (5–350 MHz), differential (5–710 MHz)
Supply Voltage	Core: 1.8/2.5/3.3 V ±10%; Output buffers: 1.4–3.63 V independently configurable per driver
Package	24-pin QFN, 4 × 4 mm, 0.5 mm pitch; RoHS-compliant, moisture sensitivity level 3
Operating Temperature	–40 to +85 °C ambient; qualified per industrial-grade reliability standards

Pinout & Package

SI5338K-B10518-GM is housed in a 24-lead, 4 × 4 mm QFN package with exposed thermal pad. Pin functions are defined per Skyworks Rev. 1.6 datasheet (pages 33–37).

Pin/Terminal	Circuit Role	Design Meaning
IN1, IN2	Differential input pair 1	Accepts 5–710 MHz AC-coupled differential reference; internal 100 Ω termination enabled
IN3, IN4	Single-ended input pair	Supports 5–200 MHz CMOS-level clocks; VIH = 0.7×VDD, VIL = 0.3×VDD
CLK0A, CLK0B – CLK3A, CLK3B	Differential output pairs	Four fully independent drivers; each configurable for LVPECL/LVDS/HCSL/CML format and voltage
VDDO0–VDDO3	Output buffer supply pins	Independent 1.4–3.63 V supplies per output bank; enables mixed-voltage clock distribution
SCL, SDA	I²C serial interface	Standard-mode (100 kHz) and fast-mode (400 kHz) compatible; supports SMBus alert response
INTR	Interrupt output	Open-drain status indicator for loss-of-lock, loss-of-signal, or configuration error events
VDD	Core supply	1.8/2.5/3.3 V ±10%; PSRR optimized for low-noise clock generation
GND, RSVD_GND	Ground connections	Multiple dedicated GND pins and reserved ground pad for thermal and EMI performance

Key Features

Feature	Design Value
MultiSynth™ synthesis	Four independent fractional-N synthesizers enable any-frequency output (0.16–710 MHz) with 0 ppm precision per channel
PCIe Gen 1–4 compliance	Validated total jitter ≤33.6 ps pk-pk (Gen 1), ≤0.45 ps RMS (Gen 4 common clock), meeting SRNS and CDR requirements
Flexible output configuration	Each output supports format (LVDS/LVPECL/HCSL/CMOS), voltage (1.5–3.3 V), and slew rate tuning - no external components needed
Dynamic frequency adjustment	Glitchless ±1 ppm frequency increments via PINC/FDEC pins or I²C; update time as low as 667 ns
Programmable phase offset	±45 ns initial phase shift per output with <20 ps step resolution for skew compensation in parallel bus interfaces
Spread spectrum control	Configurable SSC on any output: 0.5–5.0% down-spread, 33–63 kHz modulation rate - reduces EMI peak emissions

Applications

Ethernet Switch/Router Timing	PCIe Gen 3/4 Clock Distribution
Use Scenario: Synchronizing 10GbE MAC/PHY, packet buffer, and switch fabric ASICs in Layer 3 routing platforms. IC Role / Device Role / Timing Role: Quad-output clock generator providing independent 156.25 MHz (XAUI), 125 MHz (RXAUI), 250 MHz (switch core), and 100 MHz (management CPU) clocks. Use Value: Eliminates four discrete oscillators; achieves <0.7 ps RMS jitter on all outputs to meet IEEE 802.3ae and PCIe Gen 4 eye diagram specs.	Use Scenario: Delivering synchronized reference clocks to CPU, GPU, NVMe SSD, and chipset in server/mainboard designs. IC Role / Device Role / Timing Role: PCIe Common Clock source generating 100 MHz differential HCSL for root complex and endpoints, plus 100 MHz LVDS for auxiliary logic. Use Value: Meets PCIe Gen 4 SRNS jitter limit (≤0.32 ps RMS) and supports simultaneous Gen 3/Gen 4 lane configurations without layout rework.
Broadcast Video/Audio Sync	Processor & FPGA Clocking
Use Scenario: Generating frame-synced clocks for SDI transceivers, video processing ASICs, and audio DACs in 4K/8K production equipment. IC Role / Device Role / Timing Role: Producing 27 MHz (SDI), 74.25 MHz (HD-SDI), 148.5 MHz (3G-SDI), and 297 MHz (12G-SDI) from a single 25 MHz crystal reference. Use Value: Zero-ppm synthesis accuracy ensures sub-sample jitter alignment across multi-channel video pipelines; supports SMPTE ST 2082-1 timing compliance.	Use Scenario: Providing configurable clocks to heterogeneous compute subsystems - ARM cores, FPGA fabric, DDR4 memory controller, and PCIe peripherals. IC Role / Device Role / Timing Role: Generating 1 GHz CPU clock (via PLL bypass), 500 MHz FPGA logic clock, 1200 MHz DDR4 PHY clock, and 250 MHz debug trace clock from one device. Use Value: Independent voltage per output (1.8 V for FPGA I/O, 1.2 V for DDR4, 3.3 V for legacy peripherals) eliminates external regulators and level shifters.

Ethernet Switch/Router Timing

PCIe Gen 3/4 Clock Distribution

Use Scenario: Synchronizing 10GbE MAC/PHY, packet buffer, and switch fabric ASICs in Layer 3 routing platforms.

IC Role / Device Role / Timing Role: Quad-output clock generator providing independent 156.25 MHz (XAUI), 125 MHz (RXAUI), 250 MHz (switch core), and 100 MHz (management CPU) clocks.

Use Value: Eliminates four discrete oscillators; achieves <0.7 ps RMS jitter on all outputs to meet IEEE 802.3ae and PCIe Gen 4 eye diagram specs.

Use Scenario: Delivering synchronized reference clocks to CPU, GPU, NVMe SSD, and chipset in server/mainboard designs.

IC Role / Device Role / Timing Role: PCIe Common Clock source generating 100 MHz differential HCSL for root complex and endpoints, plus 100 MHz LVDS for auxiliary logic.

Use Value: Meets PCIe Gen 4 SRNS jitter limit (≤0.32 ps RMS) and supports simultaneous Gen 3/Gen 4 lane configurations without layout rework.

Broadcast Video/Audio Sync

Processor & FPGA Clocking

Use Scenario: Generating frame-synced clocks for SDI transceivers, video processing ASICs, and audio DACs in 4K/8K production equipment.

IC Role / Device Role / Timing Role: Producing 27 MHz (SDI), 74.25 MHz (HD-SDI), 148.5 MHz (3G-SDI), and 297 MHz (12G-SDI) from a single 25 MHz crystal reference.

Use Value: Zero-ppm synthesis accuracy ensures sub-sample jitter alignment across multi-channel video pipelines; supports SMPTE ST 2082-1 timing compliance.

Use Scenario: Providing configurable clocks to heterogeneous compute subsystems - ARM cores, FPGA fabric, DDR4 memory controller, and PCIe peripherals.

IC Role / Device Role / Timing Role: Generating 1 GHz CPU clock (via PLL bypass), 500 MHz FPGA logic clock, 1200 MHz DDR4 PHY clock, and 250 MHz debug trace clock from one device.

Use Value: Independent voltage per output (1.8 V for FPGA I/O, 1.2 V for DDR4, 3.3 V for legacy peripherals) eliminates external regulators and level shifters.

Equivalent & Alternatives

The following parts are listed as comparable options for similar quad-output programmable clock generator applications.

Alternative Part	Technical Difference	Application Difference	Selection Advice
Si5332A-D08589-GM	Higher integration: 8 outputs, lower jitter (0.35 ps RMS), integrated crystal option; requires different programming flow	Targeted at multi-chip module (MCM) and AI accelerator clock trees requiring >4 outputs	Select when needing ≥8 outputs or ultra-low jitter for coherent optical interfaces; not drop-in compatible due to pin count and register map differences
ICS8430I-01T	Fixed-frequency, non-programmable quad LVDS clock buffer; 1.2 ps RMS jitter; no I²C interface or frequency synthesis	Used only in fixed-clock fanout scenarios where no frequency translation is required	Choose only for cost-sensitive, static-clock applications; lacks any-frequency synthesis, phase control, or spread spectrum capability of SI5338K-B10518-GM

Compared with Si5332A-D08589-GM and ICS8430I-01T, the SI5338K-B10518-GM uniquely balances field-programmability, PCIe Gen 4 compliance, and 4-output flexibility in a compact QFN - making it optimal for mid-tier networking and embedded computing where configurability and footprint matter more than maximum channel count or absolute lowest jitter.

Availability

SI5338K-B10518-GM is available at Aetrix Electronics and suitable for Ethernet switch/router timing, PCIe Gen 3/4 clock distribution, and broadcast video/audio synchronization requiring stable component supply across industrial temperature ranges and long product lifecycles.

Supply support for SI5338K-B10518-GM includes scheduled delivery planning, volume procurement assistance, BOM continuity management, traceable sourcing, and lifecycle availability coordination for OEM customers, industrial embedded developers, connected-device designers, and electronics production programs.

Manufacturer

Skyworks Solutions is a global leader in analog and mixed-signal semiconductors, specializing in RF, timing, and connectivity solutions for infrastructure, automotive, and mobile markets.

The SI5338 family was designed specifically for high-speed serial interface clocking - delivering low-jitter, multi-format, programmable timing in space-constrained systems such as 10GbE switches, PCIe servers, and broadcast equipment.

FAQ

What is the guaranteed phase jitter performance of the SI5338K-B10518-GM?

The SI5338K-B10518-GM delivers 0.7 ps RMS typical phase jitter (12 kHz–20 MHz) under standard test conditions (25 MHz crystal input, all outputs at 125 MHz LVDS). This value is specified in Table 12 of the Skyworks Rev. 1.6 datasheet and meets PCIe Gen 3 SRNS and Gen 4 common clock requirements. Measured worst-case is 1.0 ps RMS.

Does the SI5338K-B10518-GM support PCIe Gen 4 Separate Reference No Spread (SRNS) mode?

Yes, the SI5338K-B10518-GM is explicitly validated for PCIe Gen 4 SRNS operation with ≤0.32 ps RMS jitter (typical) when configured with a 2–5 MHz PLL bandwidth and 10 MHz CDR reference. This compliance is documented in Table 12, "Jitter Specifications", and confirmed in Skyworks Application Note AN562.

Can the SI5338K-B10518-GM generate four different frequencies above 350 MHz simultaneously?

No. The SI5338K-B10518-GM supports only two unique frequencies above 350 MHz at once - specifically Fvco/4 and Fvco/6 - as stated in Note 6 of Table 6. All four outputs can operate above 350 MHz only if two share Fvco/4 and two share Fvco/6; independent >350 MHz frequencies on all four outputs are not supported.

What input reference options does the SI5338K-B10518-GM support?

The SI5338K-B10518-GM accepts six input types: 8–30 MHz fundamental-mode crystals; 5–200 MHz CMOS single-ended clocks; 5–350 MHz SSTL or HSTL inputs; and 5–710 MHz differential (LVDS/LVPECL) references. Input pin assignments and termination requirements are detailed in Section 7 ("Pin Descriptions") of the datasheet.

Is ClockBuilder Pro software required to configure the SI5338K-B10518-GM?

No - ClockBuilder Pro is optional but strongly recommended. The SI5338K-B10518-GM can be programmed directly via its I²C/SMBus interface using custom firmware. However, ClockBuilder Pro (freely available from Skyworks) provides GUI-based configuration, jitter simulation, register file export, and PCIe compliance validation - significantly reducing bring-up time for the SI5338K-B10518-GM.

SI5338K-B10518-GM Specifications

Product attributes: Attribute value

Manufacturer:: Skyworks Solutions Inc.

Series:: *

Package/Case:: -

Packaging:: Tray

Product Status:: Active

Programmable:: Not Verified

PLL:: -

Main Purpose:: -

Input:: -

Output:: -

Number of Circuits:: -

Ratio - Input:Output:: -

Differential - Input:Output:: -

Frequency - Max:: -

Voltage - Supply:: -

Operating Temperature:: -

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Qualification:: -

Supplier Device Package:: -

SI5338K-B10518-GM FAQ

1.How can I place an order for SI5338K-B10518-GM through Aetrix?

Please submit a Request for Quotation (RFQ) for SI5338K-B10518-GM on Aetrix. Our sales agent will provide a competitive quotation and guide you through the order confirmation once you accept the terms.

2.Are the price and stock information for SI5338K-B10518-GM reliable?

The price and inventory of SI5338K-B10518-GM are updated periodically and may fluctuate due to market conditions. Stock and pricing data are typically refreshed every 24 hours. Quotation validity for SI5338K-B10518-GM is usually 5 days.

3.What payment methods are accepted for SI5338K-B10518-GM?

We accept Wire Transfer, PayPal, Credit Card, Western Union, MoneyGram, and Escrow for SI5338K-B10518-GM transactions.

Note: Certain payment methods may incur a processing fee.

4.How is shipping managed for SI5338K-B10518-GM?

SI5338K-B10518-GM orders can be shipped via leading logistics carriers, including DHL, UPS, FedEx, TNT, or Registered Mail.

Once your SI5338K-B10518-GM order is processed, you will receive an email with the shipment details and tracking number.

Note: Tracking information may take up to 24 hours to appear. Express delivery typically takes 3–5 business days.

5.How can I obtain technical support or documentation for SI5338K-B10518-GM?

For technical support, including SI5338K-B10518-GM datasheets, pinout diagrams, or application guidance, please contact our engineering support team. They can provide detailed documentation and assistance for your SI5338K-B10518-GM requirements.

6.How does Aetrix verify that SI5338K-B10518-GM is sourced from the original manufacturer or authorized distributors?

All SI5338K-B10518-GM products on Aetrix are procured from qualified distributors and authorized channels. Our dedicated quality assurance team conducts strict verification, including traceability checks and, if necessary, third-party testing. This ensures that SI5338K-B10518-GM meets industry standards.

7.What is the process for return or replacement of SI5338K-B10518-GM?

All SI5338K-B10518-GM units undergo pre-shipment inspection (PSI). If there is an issue with SI5338K-B10518-GM, returns or replacements are accepted under the following conditions:

1.Quantity discrepancies, incorrect items, or visible external defects (such as breakage or corrosion), acknowledged by Aetrix.

2.The issue is reported within 90 days of delivery.

3.The SI5338K-B10518-GM part is unused and in its original packaging.

Return procedure for SI5338K-B10518-GM:

1.Submit a request within 90 days.

2.Obtain a Return Material Authorization (RMA) from Aetrix.

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