Skyworks Solutions Inc. SI5338L-B04326-GMR
- Part No.:
- SI5338L-B04326-GMR
- Manufacturer:
- Skyworks Solutions Inc.
- Category:
- Application Specific Clock/Timing
- Package:
- 24-VFQFN Exposed Pad
- Datasheet:
-
SI5338L-B04326-GMR.pdf
- Description:
- I2C CONTROL, 4-OUTPUT, ANY FREQU
- Quantity:
- Payment:

- Shipping:

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Product details
Overview
SI5338L-B04326-GMR from Skyworks Solutions is a quad-output, I²C-programmable clock generator with MultiSynth™ frequency synthesis, delivering four independent low-jitter clocks (0.7 ps RMS typ) across LVPECL/LVDS/HCSL/CMOS/SSTL/HSTL formats, supporting 0.16–710 MHz output frequencies and operating from 1.8/2.5/3.3 V core supply - deployed in PCIe Gen 4, Ethernet switch timing, and FPGA clocking systems.
For engineers reviewing the SI5338L-B04326-GMR datasheet, SI5338L-B04326-GMR pinout, SI5338L-B04326-GMR application, or SI5338L-B04326-GMR equivalent, key selection criteria include PCIe Gen 4 SRNS compliance, independent per-output voltage control (1.5–3.3 V), ±20 ps phase step resolution, spread-spectrum capability (0.5–5.0% down-spread), and 24-QFN package compatibility with standard PCB land patterns.
Technical Context
The SI5338L-B04326-GMR implements a two-stage PLL architecture: a high-stability reference stage followed by four independent MultiSynth™ fractional-N synthesis blocks, each driving configurable output buffers. Its input flexibility supports differential (5–710 MHz), CMOS (5–200 MHz), SSTL/HSTL (5–350 MHz), and crystal (8–30 MHz) references.
Each of the four output drivers supports independent format selection (LVPECL/LVDS/HCSL/CMOS/SSTL/HSTL), independent VDDO supply (1.5/1.8/2.5/3.3 V), programmable phase offset (±45 ns), and glitchless frequency increment/decrement in 1 ppm steps - enabling precise synchronization in multi-clock-domain systems like telecom line cards and broadcast video infrastructure.
Key Specifications
| Parameter | Value and Actual Design Meaning |
|---|---|
| Output Count | Four independent differential or single-ended clock outputs |
| Phase Jitter (RMS) | 0.7 ps typical (12 kHz–20 MHz), meeting PCIe Gen 4 SRNS requirements |
| Frequency Range | 0.16–710 MHz per output, with integer/fractional synthesis and <1 ppb resolution |
| Input Reference Support | Differential (5–710 MHz), CMOS (5–200 MHz), SSTL/HSTL (5–350 MHz), crystal (8–30 MHz) |
| Supply Voltages | Core: 1.8/2.5/3.3 V; Output buffers: independently configurable 1.5/1.8/2.5/3.3 V |
| Package | 24-pin QFN, 4 × 4 mm, 0.5 mm pitch, exposed thermal pad |
| Operating Temp | –40 °C to +85 °C ambient, qualified for industrial embedded applications |
Pinout & Package
SI5338L-B04326-GMR uses a 24-lead QFN package (4 mm × 4 mm, 0.5 mm pitch) with exposed thermal pad. Pin assignments are fixed per Skyworks Si5338 family specification and validated for this variant.
| Pin/Terminal | Circuit Role | Design Meaning |
|---|---|---|
| IN1, IN2 | Differential input pair | Accepts 5–710 MHz AC-coupled differential reference; internal 100 Ω termination support |
| IN3, IN4 | Single-ended input pair | Supports 5–200 MHz CMOS-level inputs; VIH = 0.7×VDD, VIL = 0.3×VDD |
| CLK0A, CLK0B – CLK3A, CLK3B | Differential output pairs | Four independent output drivers; each configurable as LVPECL/LVDS/HCSL/CML |
| VDDO0–VDDO3 | Output buffer supplies | Independent 1.5/1.8/2.5/3.3 V rails per output bank for level translation |
| VDD | Core supply | Single 1.8/2.5/3.3 V supply powering PLL, synthesizers, and logic |
| SCL, SDA | I²C interface | SMBus-compatible serial programming interface (up to 400 kHz) |
| INTR | Interrupt output | Open-drain status signal for loss-of-lock and loss-of-signal alarms |
Key Features
| Feature | Design Value |
|---|---|
| MultiSynth™ synthesis | Enables true zero-ppm accuracy on all four outputs with independent fractional-N dividers |
| Per-output voltage control | Each output driver powered by dedicated VDDO rail (1.5/1.8/2.5/3.3 V) for seamless interface to mixed-voltage SoCs/FPGAs |
| Glitchless frequency tuning | 1 ppm step size with hardware pin control (FINC/FDEC) or I²C, no output interruption during adjustment |
| Programmable phase offset | ±45 ns range in <20 ps steps per output, enabling deterministic skew compensation across clock domains |
| Spread spectrum support | Configurable down-spread (0.5–5.0%) at 33–63 kHz modulation rate on any output to reduce EMI |
| PCIe Gen 4 compliance | Validated for Common Clock and SRNS modes per PCIe Base Spec 4.0, with <0.45 ps RMS jitter |
Applications
| PCIe Gen 4 Switch Timing | Ethernet Switch/Routing |
|---|---|
Use Scenario: Providing synchronized reference clocks to multiple PCIe Gen 4 switch ASICs and retimers in high-density data center switches. IC Role / Device Role / Timing Role: Quad-output clock generator delivering four independent 100 MHz HCSL clocks with <0.45 ps RMS jitter and SRNS compliance. Use Value: Eliminates need for four discrete oscillators while maintaining PCIe Gen 4 jitter budget and simplifying board layout. |
Use Scenario: Generating system clocks for 1 GbE/10 GbE PHYs, packet processors, and SerDes interfaces in carrier-grade routers. IC Role / Device Role / Timing Role: Configurable clock source supporting 125 MHz (GbE), 156.25 MHz (10GbE), and 312.5 MHz (25GbE) simultaneously. Use Value: Enables single-device clock tree for multi-rate Ethernet platforms with per-port voltage and format flexibility. |
| Broadcast Video Timing | FPGA-Based Video Processing |
Use Scenario: Delivering genlock-capable pixel clocks (e.g., 74.25 MHz, 148.5 MHz) and audio sample clocks (48 kHz, 96 kHz) in SMPTE ST 2110 IP video encoders. IC Role / Device Role / Timing Role: Any-frequency synthesizer generating exact SMPTE-compliant frequencies with sub-ps jitter for frame-accurate sync. Use Value: Replaces crystal-based solutions with software-defined timing, enabling field-upgradable frame rates and multi-standard support. |
Use Scenario: Supplying high-precision clocks to Xilinx Versal or Intel Agilex FPGAs for real-time video processing pipelines with DDR4 memory interfaces. IC Role / Device Role / Timing Role: Dual-role device: generates 300 MHz FPGA fabric clock and 1200 MHz DDR4 PHY clock with matched phase alignment. Use Value: Achieves <100 ps output-to-output skew between critical clocks, reducing timing margin overhead in high-speed memory subsystems. |
Equivalent & Alternatives
The following parts are listed as comparable options for similar clock generator applications.
| Alternative Part | Technical Difference | Application Difference | Selection Advice |
|---|---|---|---|
| Si5338A-B04326-GM | Same silicon, different factory-programmed configuration; lacks pre-loaded B04326 firmware image | Requires full ClockBuilder Pro configuration; not pre-validated for PCIe Gen 4 SRNS | Select SI5338L-B04326-GMR when drop-in replacement for existing B04326 designs is required |
| LMK04832ISQE/NOPB | Two PLLs, eight outputs, higher power (120 mA), larger 48-QFN package; jitter = 0.18 ps RMS (better) | Targeted at ultra-low-jitter RF and instrumentation; over-spec for PCIe Gen 4 switching | Choose LMK04832 only if >8 outputs or sub-0.2 ps jitter is mandatory; adds cost and board area |
Compared with Si5338A-B04326-GM, SI5338L-B04326-GMR offers factory-programmed readiness for PCIe Gen 4 SRNS, while LMK04832ISQE/NOPB delivers superior jitter performance at the expense of higher power, larger footprint, and greater complexity - making SI5338L-B04326-GMR optimal for space-constrained, cost-sensitive PCIe and Ethernet switch designs.
Availability
SI5338L-B04326-GMR is available at Aetrix Electronics and suitable for PCIe Gen 4 switch timing, Ethernet routing infrastructure, and broadcast video equipment requiring stable component supply, long-term lifecycle assurance, and consistent pre-programmed configuration.
Supply support for SI5338L-B04326-GMR includes scheduled delivery planning, volume procurement assistance, BOM continuity management, traceable sourcing, and lifecycle availability coordination for OEM customers, industrial embedded developers, connected-device designers, and electronics production programs.
Manufacturer
Skyworks Solutions is a global semiconductor company specializing in analog and mixed-signal connectivity solutions for wireless, broadband, automotive, and industrial markets.
The Si5338 product line delivers programmable, low-jitter clock generation for high-speed digital systems including PCIe, Ethernet, and broadcast video, emphasizing flexibility, integration, and compliance with stringent timing standards.
FAQ
What is the primary function of the SI5338L-B04326-GMR?
The SI5338L-B04326-GMR is an I²C-programmable quad-output clock generator using Skyworks' MultiSynth™ technology to synthesize four independent, low-jitter output clocks (0.7 ps RMS typ) from a single reference. It replaces up to four discrete oscillators in applications such as PCIe Gen 4 switches and Ethernet routers, with factory-programmed B04326 configuration ensuring immediate SRNS compliance without reprogramming.
Does the SI5338L-B04326-GMR support PCIe Gen 4 timing requirements?
Yes, the SI5338L-B04326-GMR is explicitly validated for PCIe Gen 4 Common Clock and Separate Reference No Spread (SRNS) modes, delivering <0.45 ps RMS jitter (12 kHz–20 MHz) per PCIe Base Specification 4.0. Its PLL bandwidth (2–5 MHz) and CDR alignment meet Intel's jitter filter requirements, and it is pre-configured in the B04326 firmware image for out-of-box SRNS operation.
What output formats and voltage levels does the SI5338L-B04326-GMR support?
The SI5338L-B04326-GMR supports LVPECL, LVDS, HCSL, CML, CMOS, SSTL, and HSTL output formats across its four drivers. Each output bank (CLK0–CLK3) has an independent VDDO supply pin, allowing individual configuration for 1.5 V, 1.8 V, 2.5 V, or 3.3 V logic levels - enabling direct interfacing with mixed-voltage FPGAs, ASICs, and SerDes without external level shifters.
How is the SI5338L-B04326-GMR programmed and configured?
The SI5338L-B04326-GMR is programmed via its I²C/SMBus-compatible interface (SCL/SDA pins) using Skyworks' ClockBuilder Pro software. The "L" suffix indicates it ships with factory-programmed B04326 configuration - a pre-validated setup for PCIe Gen 4 SRNS - eliminating need for initial register writes. Field updates remain possible via I²C for custom frequency or feature adjustments.
What package type and thermal characteristics apply to the SI5338L-B04326-GMR?
The SI5338L-B04326-GMR uses a 24-lead QFN package (4 mm × 4 mm, 0.5 mm pitch) with exposed thermal pad. Its thermal resistance is θJA = 37 °C/W (still air) and θJC = 10 °C/W, supporting operation from –40 °C to +85 °C ambient. The package is compatible with standard IPC-7351B land patterns and reflow profiles per JEDEC J-STD-020.
SI5338L-B04326-GMR Specifications
- Product attributes
- Attribute value
- Manufacturer:
- Skyworks Solutions Inc.
- Series:
- MultiSynth™
- Package/Case:
- 24-VFQFN Exposed Pad
- Packaging:
- Tape & Reel (TR)
- Product Status:
- Active
- Programmable:
- Not Verified
- PLL:
- -
- Main Purpose:
- -
- Input:
- -
- Output:
- -
- Number of Circuits:
- -
- Ratio - Input:Output:
- -
- Differential - Input:Output:
- -
- Frequency - Max:
- -
- Voltage - Supply:
- -
- Operating Temperature:
- -
- Mounting Type:
- Surface Mount
- Grade:
- -
- Qualification:
- -
- Supplier Device Package:
- 24-QFN (4x4)
SI5338L-B04326-GMR FAQ
1.How can I place an order for SI5338L-B04326-GMR through Aetrix?
Please submit a Request for Quotation (RFQ) for SI5338L-B04326-GMR on Aetrix. Our sales agent will provide a competitive quotation and guide you through the order confirmation once you accept the terms.
2.Are the price and stock information for SI5338L-B04326-GMR reliable?
The price and inventory of SI5338L-B04326-GMR are updated periodically and may fluctuate due to market conditions. Stock and pricing data are typically refreshed every 24 hours. Quotation validity for SI5338L-B04326-GMR is usually 5 days.
3.What payment methods are accepted for SI5338L-B04326-GMR?
We accept Wire Transfer, PayPal, Credit Card, Western Union, MoneyGram, and Escrow for SI5338L-B04326-GMR transactions.
Note: Certain payment methods may incur a processing fee.
4.How is shipping managed for SI5338L-B04326-GMR?
SI5338L-B04326-GMR orders can be shipped via leading logistics carriers, including DHL, UPS, FedEx, TNT, or Registered Mail.
Once your SI5338L-B04326-GMR order is processed, you will receive an email with the shipment details and tracking number.
Note: Tracking information may take up to 24 hours to appear. Express delivery typically takes 3–5 business days.
5.How can I obtain technical support or documentation for SI5338L-B04326-GMR?
For technical support, including SI5338L-B04326-GMR datasheets, pinout diagrams, or application guidance, please contact our engineering support team. They can provide detailed documentation and assistance for your SI5338L-B04326-GMR requirements.
6.How does Aetrix verify that SI5338L-B04326-GMR is sourced from the original manufacturer or authorized distributors?
All SI5338L-B04326-GMR products on Aetrix are procured from qualified distributors and authorized channels. Our dedicated quality assurance team conducts strict verification, including traceability checks and, if necessary, third-party testing. This ensures that SI5338L-B04326-GMR meets industry standards.
7.What is the process for return or replacement of SI5338L-B04326-GMR?
All SI5338L-B04326-GMR units undergo pre-shipment inspection (PSI). If there is an issue with SI5338L-B04326-GMR, returns or replacements are accepted under the following conditions:
1.Quantity discrepancies, incorrect items, or visible external defects (such as breakage or corrosion), acknowledged by Aetrix.
2.The issue is reported within 90 days of delivery.
3.The SI5338L-B04326-GMR part is unused and in its original packaging.
Return procedure for SI5338L-B04326-GMR:
1.Submit a request within 90 days.
2.Obtain a Return Material Authorization (RMA) from Aetrix.
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