Skyworks Solutions Inc. SI5338L-B04358-GM
- Part No.:
- SI5338L-B04358-GM
- Manufacturer:
- Skyworks Solutions Inc.
- Category:
- Application Specific Clock/Timing
- Package:
- 24-VFQFN Exposed Pad
- Datasheet:
-
SI5338L-B04358-GM.pdf
- Description:
- I2C CONTROL, 4-OUTPUT, ANY FREQU
- Quantity:
- Payment:

- Shipping:

Inventory:2,144
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Product details
Overview
SI5338L-B04358-GM from Skyworks Solutions is an I²C-programmable quad clock generator with four independently configurable differential or single-ended outputs, 0.7 ps RMS typical phase jitter, PCIe Gen 1–4 Common Clock and Gen 3 SRNS compliance, and operation across –40 to +85 °C. It replaces up to four crystal oscillators in high-speed serial interface timing applications such as PCIe root complexes and FPGA-based compute platforms.
For engineers reviewing the SI5338L-B04358-GM datasheet, SI5338L-B04358-GM pinout, SI5338L-B04358-GM application, or SI5338L-B04358-GM equivalent, key selection criteria include its MultiSynth™-based any-frequency synthesis (0.16–710 MHz per output), independent output voltage support (1.5/1.8/2.5/3.3 V), spread-spectrum capability (0.5–5.0% down-spread), and 24-pin 4×4 mm QFN package with I²C/SMBus control interface.
Technical Context
The SI5338L-B04358-GM implements a two-stage PLL architecture: a high-stability input stage with programmable R-divider followed by a fractional-N MultiSynth™ synthesis stage per output path. Each of the four output drivers supports independent format selection (LVPECL/LVDS/HCSL/CMOS/SSTL/HSTL) and voltage rail (VDDO0–VDDO3).
It accepts multiple reference inputs - external 8–30 MHz crystal, CMOS (5–200 MHz), SSTL/HSTL (5–350 MHz), or differential (5–710 MHz) - and enables glitchless frequency adjustment in 1 ppm steps and phase tuning in <20 ps increments. Loss-of-lock and loss-of-signal alarms are integrated for system monitoring.
Key Specifications
| Parameter | Value and Actual Design Meaning |
|---|---|
| Phase Jitter (RMS) | 0.7 ps typ (12 kHz–20 MHz); meets PCIe Gen 3 SRNS and Gen 4 common clock jitter requirements |
| Output Frequency Range | 0.16–710 MHz per channel; supports LVPECL/LVDS up to 710 MHz, HCSL up to 250 MHz, CMOS up to 200 MHz |
| Input Reference Support | Crystal (8–30 MHz), CMOS (5–200 MHz), differential (5–710 MHz); enables flexible system clock tree design |
| Supply Voltages | Core: 1.8/2.5/3.3 V; Output buffers: independently configurable 1.5/1.8/2.5/3.3 V per driver |
| Package | 24-pin QFN, 4 × 4 mm, 0.5 mm pitch; RoHS-compliant, thermally enhanced for industrial ambient (–40 to +85 °C) |
| I²C Interface | Standard-mode (100 kHz) and fast-mode (400 kHz) compatible; supports SMBus alert response protocol via INTR pin |
| Spread Spectrum | Configurable on any output: 0.5–5.0% down-spread, 33–63 kHz modulation rate; reduces EMI in dense PCB layouts |
Pinout & Package
SI5338L-B04358-GM is housed in a 24-lead, 4 × 4 mm QFN package with exposed thermal pad. Pin assignments follow Skyworks' standard Si5338 pinout: six input pins (IN1–IN6), eight clock output terminals (CLK0A/B through CLK3A/B), four VDDO supply rails (VDDO0–VDDO3), dual core VDD, SCL/SDA/I²C interface, INTR interrupt, and ground/pad connections.
| Pin/Terminal | Circuit Role | Design Meaning |
|---|---|---|
| IN1/IN2, IN5/IN6 | Differential reference inputs | Accept AC-coupled LVPECL/LVDS/CML clocks up to 710 MHz; require external 100 Ω termination |
| IN3/IN4 | Single-ended reference inputs | Support CMOS/SSTL/HSTL signals (5–350 MHz); internally biased; slew-rate sensitive for jitter performance |
| CLK0A/CLK0B – CLK3A/CLK3B | Differential clock outputs | Four independent pairs; each configurable for LVPECL/LVDS/HCSL/CML with dedicated VDDO supply |
| VDDO0–VDDO3 | Output buffer supply rails | Enable per-output voltage setting (1.5/1.8/2.5/3.3 V); decoupling required per rail for low-noise operation |
| SCL/SDA | I²C serial interface | Standard bidirectional bus; supports device configuration, status readback, and dynamic frequency/phase updates |
| INTR | Interrupt output | Open-drain active-low signal indicating loss-of-lock, loss-of-signal, or other fault conditions |
Key Features
| Feature | Design Value |
|---|---|
| MultiSynth™ synthesis engine | Enables true zero-ppm frequency accuracy on all four outputs simultaneously, eliminating need for multiple crystals |
| Independent output format & voltage | Each of four outputs supports mixed signaling (e.g., LVDS + HCSL + CMOS) at different voltages-critical for multi-chip SoC/FPGA interfaces |
| Glitchless frequency stepping | 1 ppm resolution increment/decrement via PINC/FDEC pins or I²C; no output interruption during real-time clock adjustments |
| Programmable phase offset | ±45 ns range with <20 ps step resolution per output; enables precise skew alignment across high-speed SerDes lanes |
| PCIe Gen 1–4 compliance | Fully validated for PCIe Common Clock (Gen 1–4) and Gen 3 Separate Reference No Spread (SRNS) modes per specification |
| External feedback mode | Supports zero-delay buffer operation using external clock feedback path-ideal for clock distribution fanout |
Applications
| PCIe Root Complex Timing | Ethernet Switch Clocking |
|---|---|
Use Scenario: Providing synchronized 100 MHz reference clocks to multiple PCIe endpoints and switch fabric in enterprise servers. IC Role / Device Role / Timing Role: Quad-output clock generator delivering four independent, low-jitter PCIe-compliant clocks with matched phase alignment. Use Value: Eliminates four discrete oscillators; reduces board area and BOM count while meeting PCIe Gen 4 common clock jitter limit of ≤0.45 ps RMS. |
Use Scenario: Generating 125 MHz, 156.25 MHz, and 312.5 MHz clocks for 1/10 GbE PHYs and packet processors in Layer-3 switches. IC Role / Device Role / Timing Role: Any-frequency synthesizer producing exact Ethernet line rates with independent output formats (LVDS for PHYs, CMOS for controllers). Use Value: Enables single-device support for mixed-speed Ethernet ports without external dividers or level shifters. |
| FPGA-Based Video Processing | Telecom Line Card Synchronization |
Use Scenario: Supplying pixel clock (148.5 MHz), DDR memory clock (400 MHz), and video processing core clock (300 MHz) to broadcast-grade FPGA video pipelines. IC Role / Device Role / Timing Role: Configurable quad clock source with independent voltage rails and phase tuning per output. Use Value: Achieves sub-20 ps inter-output skew and <0.7 ps RMS jitter-meeting SMPTE ST 2082-1 jitter budgets for 12G-SDI systems. |
Use Scenario: Delivering synchronous 155.52 MHz (OC-3), 622.08 MHz (OC-12), and 2.488 GHz (OC-48) clocks to multiple DSPs and framer ICs on telecom line cards. IC Role / Device Role / Timing Role: High-stability clock generator with OC-12 random jitter ≤0.7 ps RMS and loss-of-signal detection. Use Value: Meets Telcordia GR-1244-CORE jitter requirements while enabling hot-swap-aware alarm signaling via INTR pin. |
Equivalent & Alternatives
The following parts are listed as comparable options for similar quad clock generator applications.
| Alternative Part | Technical Difference | Application Difference | Selection Advice |
|---|---|---|---|
| Si5332A-D06989-GM | Higher integration: includes integrated crystal, lower jitter (0.35 ps RMS), supports up to 10 outputs; larger 32-QFN package | Better suited for space-constrained designs requiring ultra-low jitter and crystal-free BOM | Select when crystal integration and sub-0.4 ps jitter are mandatory; not drop-in due to pinout and footprint change |
| ICS8430I-01LG | Fixed-frequency quad LVDS generator; no I²C programming; 1.2 ps RMS jitter; 3.3 V only; 32-TQFP package | Limited to pre-defined frequencies; no spread spectrum or phase tuning; simpler control but inflexible | Choose for cost-sensitive, fixed-clock applications where programmability is unnecessary and TQFP assembly is preferred |
Compared with SI5338L-B04358-GM, the Si5332A-D06989-GM offers superior jitter and integrated crystal but requires PCB redesign, while the ICS8430I-01LG provides lower cost and simpler interface at the expense of configurability and jitter performance.
Availability
SI5338L-B04358-GM is available at Aetrix Electronics and suitable for PCIe Gen 4 server motherboards, 10 GbE switching infrastructure, and FPGA-based broadcast video equipment requiring stable component supply, long-term lifecycle support, and traceable sourcing.
Supply support for SI5338L-B04358-GM includes scheduled delivery planning, volume procurement assistance, BOM continuity management, traceable sourcing, and lifecycle availability coordination for OEM customers, industrial embedded developers, connected-device designers, and electronics production programs.
Manufacturer
Skyworks Solutions is a global leader in analog and mixed-signal semiconductors, specializing in RF, timing, and connectivity solutions for communications, automotive, and industrial markets.
The Si5338 family is designed for high-performance, programmable clock generation in datacenter, networking, and broadcast video systems where flexibility, low jitter, and multi-format output capability are critical.
FAQ
What is the maximum output frequency supported by SI5338L-B04358-GM in LVPECL mode?
The SI5338L-B04358-GM supports LVPECL outputs up to 710 MHz, as confirmed in Table 6 of the datasheet. This applies when operating in integer synthesis mode with appropriate VDDO supply (2.5 V or 3.3 V) and proper termination (50 Ω to VDDO–2 V). Frequencies above 350 MHz are limited to two unique values simultaneously (Fvco/4 and Fvco/6).
Does SI5338L-B04358-GM support PCIe Gen 4 Separate Reference No Spread (SRNS) mode?
No - SI5338L-B04358-GM is compliant with PCIe Gen 4 Common Clock mode (≤0.45 ps RMS jitter), but it does not support Gen 4 SRNS. The datasheet explicitly lists SRNS compliance only for PCIe Gen 3. For Gen 4 SRNS, Skyworks recommends the Si5332 or Si534x families.
Can SI5338L-B04358-GM generate four different output frequencies simultaneously?
Yes - the SI5338L-B04358-GM uses four independent MultiSynth™ engines, allowing simultaneous synthesis of four distinct frequencies (e.g., 100 MHz, 125 MHz, 156.25 MHz, and 312.5 MHz), each with independent format, voltage, phase, and spread-spectrum settings.
What is the minimum input clock frequency supported in PLL bypass (buffer) mode for SI5338L-B04358-GM?
In PLL bypass mode, SI5338L-B04358-GM supports input frequencies as low as 1 MHz on single-ended inputs (IN3/IN4), though loss-of-signal detection is disabled below 5 MHz. Differential inputs (IN1/IN2, IN5/IN6) require ≥5 MHz for full functionality including LOS monitoring.
Is an external crystal required for SI5338L-B04358-GM operation?
No - SI5338L-B04358-GM supports multiple reference sources: external 8–30 MHz crystal, CMOS clock (5–200 MHz), or differential clock (5–710 MHz). Crystal use is optional; the device can operate entirely from an external clock source without any crystal.
SI5338L-B04358-GM Specifications
- Product attributes
- Attribute value
- Manufacturer:
- Skyworks Solutions Inc.
- Series:
- MultiSynth™
- Package/Case:
- 24-VFQFN Exposed Pad
- Packaging:
- Tray
- Product Status:
- Active
- Programmable:
- Not Verified
- PLL:
- -
- Main Purpose:
- -
- Input:
- -
- Output:
- -
- Number of Circuits:
- -
- Ratio - Input:Output:
- -
- Differential - Input:Output:
- -
- Frequency - Max:
- -
- Voltage - Supply:
- -
- Operating Temperature:
- -
- Mounting Type:
- Surface Mount
- Grade:
- -
- Qualification:
- -
- Supplier Device Package:
- 24-QFN (4x4)
SI5338L-B04358-GM FAQ
1.How can I place an order for SI5338L-B04358-GM through Aetrix?
Please submit a Request for Quotation (RFQ) for SI5338L-B04358-GM on Aetrix. Our sales agent will provide a competitive quotation and guide you through the order confirmation once you accept the terms.
2.Are the price and stock information for SI5338L-B04358-GM reliable?
The price and inventory of SI5338L-B04358-GM are updated periodically and may fluctuate due to market conditions. Stock and pricing data are typically refreshed every 24 hours. Quotation validity for SI5338L-B04358-GM is usually 5 days.
3.What payment methods are accepted for SI5338L-B04358-GM?
We accept Wire Transfer, PayPal, Credit Card, Western Union, MoneyGram, and Escrow for SI5338L-B04358-GM transactions.
Note: Certain payment methods may incur a processing fee.
4.How is shipping managed for SI5338L-B04358-GM?
SI5338L-B04358-GM orders can be shipped via leading logistics carriers, including DHL, UPS, FedEx, TNT, or Registered Mail.
Once your SI5338L-B04358-GM order is processed, you will receive an email with the shipment details and tracking number.
Note: Tracking information may take up to 24 hours to appear. Express delivery typically takes 3–5 business days.
5.How can I obtain technical support or documentation for SI5338L-B04358-GM?
For technical support, including SI5338L-B04358-GM datasheets, pinout diagrams, or application guidance, please contact our engineering support team. They can provide detailed documentation and assistance for your SI5338L-B04358-GM requirements.
6.How does Aetrix verify that SI5338L-B04358-GM is sourced from the original manufacturer or authorized distributors?
All SI5338L-B04358-GM products on Aetrix are procured from qualified distributors and authorized channels. Our dedicated quality assurance team conducts strict verification, including traceability checks and, if necessary, third-party testing. This ensures that SI5338L-B04358-GM meets industry standards.
7.What is the process for return or replacement of SI5338L-B04358-GM?
All SI5338L-B04358-GM units undergo pre-shipment inspection (PSI). If there is an issue with SI5338L-B04358-GM, returns or replacements are accepted under the following conditions:
1.Quantity discrepancies, incorrect items, or visible external defects (such as breakage or corrosion), acknowledged by Aetrix.
2.The issue is reported within 90 days of delivery.
3.The SI5338L-B04358-GM part is unused and in its original packaging.
Return procedure for SI5338L-B04358-GM:
1.Submit a request within 90 days.
2.Obtain a Return Material Authorization (RMA) from Aetrix.
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