Send an Inquiry

To receive a quote for your project, please fill in the following information, and we’ll get back to you promptly.

Submit Inventory List

Please fill in the following information, and we’ll get back to you promptly.

Home > Products > Integrated Circuits (ICs) > Clock/Timing > Application Specific Clock/Timing

Skyworks Solutions Inc. SI5338L-B04358-GMR

Name: SI5338L-B04358-GMR
Brand: Skyworks Solutions Inc.
SKU: SI5338L-B04358-GMR
Price: 2.40 USD
Availability: InStock
Rating: 5 (2 reviews)

Compare

Part No.:: SI5338L-B04358-GMR

Manufacturer:: Skyworks Solutions Inc.

Category:: Application Specific Clock/Timing

Package:: 24-VFQFN Exposed Pad

Datasheet:: SI5338L-B04358-GMR.pdf

Description:: I2C CONTROL, 4-OUTPUT, ANY FREQU

Quantity:: RFQ Add To RFQ list

Payment:

Shipping:

Inventory:1,749

Please send an inquiry. Send us your inquiry, and we will respond immediately.

Product details

Overview

SI5338L-B04358-GMR from Skyworks Solutions is an I²C-programmable quad clock generator with four independently configurable differential or single-ended outputs, 0.7 ps RMS typical phase jitter, PCIe Gen 1–4 and SRNS compliance, and MultiSynth™ frequency synthesis supporting 0.16–710 MHz output ranges across LVPECL/LVDS/HCSL/CMOS/SSTL/HSTL formats. It replaces up to four crystal oscillators in high-speed serial interface timing applications.

For engineers reviewing the SI5338L-B04358-GMR datasheet, SI5338L-B04358-GMR pinout, SI5338L-B04358-GMR application, or SI5338L-B04358-GMR equivalent, key selection considerations include its 24-QFN package, 4× independent output voltage control (1.5/1.8/2.5/3.3 V), ±20 ps phase step resolution, 1 ppm frequency increment/decrement capability, and support for external crystal (8–30 MHz), CMOS (5–200 MHz), or differential (5–710 MHz) reference inputs.

Technical Context

The SI5338L-B04358-GMR implements a two-stage PLL architecture: a high-stability integer-N PLL (Stage 1) locks to one of six input references, followed by four independent MultiSynth™ fractional-N synthesizers (Stage 2) generating each output with zero-ppm accuracy. Its output stage supports per-driver voltage selection and format configuration without shared resource constraints.

It features loss-of-signal and loss-of-lock monitoring, programmable spread spectrum (0.5–5.0% deviation, 33–63 kHz modulation), independent phase offset (±45 ns), and glitchless frequency tuning via dedicated pins or I²C. The device operates across –40 to +85 °C with core supply options at 1.8/2.5/3.3 V and output buffers powered separately at 1.4–3.63 V.

Key Specifications

Parameter	Value and Actual Design Meaning
Phase Jitter (RMS)	0.7 ps - meets PCIe Gen 3/4 common clock and SRNS requirements for low-noise serial link timing
Output Frequency Range	0.16–710 MHz - covers Ethernet (125/156.25 MHz), PCIe (100 MHz), Fibre Channel (1.0625 GHz ÷2), and processor clocks
Input Reference Support	8–30 MHz crystal, 5–200 MHz CMOS, 5–350 MHz SSTL/HSTL, 5–710 MHz differential - enables flexible system-level clock sourcing
Output Format Flexibility	LVPECL/LVDS/HCSL/CMOS/SSTL/HSTL - allows direct interface to FPGAs, ASICs, SerDes, and memory controllers without level-shifting
Supply Configuration	Single-core VDD (1.8/2.5/3.3 V) + four independent VDDOx (1.4–3.63 V) - decouples noise-sensitive core from output driver domains
Temperature Range	–40 to +85 °C - qualified for industrial and telecom line card deployment
Package	24-pin QFN, 4 × 4 mm - space-efficient footprint compatible with high-density PCB layouts

Pinout & Package

SI5338L-B04358-GMR uses a 24-lead, 4 × 4 mm QFN package with exposed thermal pad. Pin functions are defined per Skyworks Rev. 1.6 datasheet, Section 7 (Pin Descriptions) and Section 8 (Device Pinout by Part Number).

Pin/Terminal	Circuit Role	Design Meaning
IN1/IN2, IN5/IN6	Differential input pairs	Accept 5–710 MHz AC-coupled differential clocks; require external 100 Ω termination
IN3/IN4	Single-ended CMOS/SSTL/HSTL inputs	Support 5–200 MHz (CMOS) or 5–350 MHz (SSTL/HSTL); VIH/VIL referenced to local VDD
CLK0A/CLK0B–CLK3A/CLK3B	Differential output pairs	Four independent outputs; each configurable for LVPECL/LVDS/HCSL/CML with per-driver VDDOx
VDDO0–VDDO3	Output buffer supplies	Enable independent 1.5/1.8/2.5/3.3 V output voltage per channel for mixed-voltage system interfacing
SCL/SDA	I²C interface	Standard SMBus-compatible 100/400 kHz bus for configuration and status readback
INTR	Interrupt output	Open-drain signal indicating loss-of-lock, loss-of-signal, or other fault conditions

Key Features

Feature	Design Value
MultiSynth™ synthesis	Enables true zero-ppm frequency accuracy on all four outputs simultaneously, eliminating need for multiple crystals
Independent output voltage control	Each of four output drivers supports selectable 1.5/1.8/2.5/3.3 V supply, enabling direct connection to diverse logic families
Glitchless frequency tuning	1 ppm step size with pin-controlled increment/decrement allows real-time clock rate adaptation without output interruption
Programmable phase offset	±45 ns range with <20 ps step resolution supports precise skew management across multi-lane interfaces like PCIe or DDR
Spread spectrum capability	Configurable 0.5–5.0% down-spread at 33–63 kHz on any output reduces EMI in dense board environments

Applications

PCIe Gen 3/4 Timing	Ethernet Switch Clocking
Use Scenario: Providing synchronized 100 MHz common clock and separate 100 MHz reference for PCIe Gen 3/4 root complex and endpoint devices in server backplanes. IC Role / Device Role / Timing Role: Quad-output clock generator delivering PCIe-compliant common clock and SRNS reference with sub-0.32 ps RMS jitter. Use Value: Meets PCIe Gen 4 SRNS jitter spec (0.11–0.32 ps RMS) while consolidating four discrete oscillators into one IC, reducing BOM count and layout area.	Use Scenario: Generating 125 MHz, 156.25 MHz, and 312.5 MHz clocks for 1/10 GbE PHYs, switch fabric, and packet buffer interfaces in enterprise switches. IC Role / Device Role / Timing Role: Programmable frequency translator converting a single 25 MHz crystal into multiple Ethernet-standard frequencies with low additive jitter. Use Value: Achieves <0.7 ps RMS jitter at 125 MHz, satisfying IEEE 802.3 clause 49 requirements without external jitter cleaners.
FPGA/ASIC Clock Distribution	Broadcast Video Synchronization
Use Scenario: Supplying independent clocks to FPGA transceivers (e.g., 148.5 MHz for HDMI), logic fabric (100 MHz), DDR3 memory (400 MHz), and PCIe core (100 MHz) from a single source. IC Role / Device Role / Timing Role: Configurable quad clock generator with per-output format and voltage selection for heterogeneous SoC/FPGA subsystems. Use Value: Eliminates inter-clock skew between domains via programmable phase offset (<20 ps steps) and supports mixed-voltage I/O (1.8 V transceiver, 1.5 V DDR).	Use Scenario: Delivering SMPTE ST 2059-2–compliant 27 MHz, 74.25 MHz, and 148.5 MHz reference clocks to video encoders, decoders, and genlock circuits in broadcast infrastructure. IC Role / Device Role / Timing Role: Low-jitter any-frequency synthesizer replacing TCXOs and fanout buffers in timing-critical video processing chains. Use Value: Maintains <10 ps pk-pk period jitter at 148.5 MHz, ensuring frame-accurate synchronization across distributed video nodes.

PCIe Gen 3/4 Timing

Ethernet Switch Clocking

Use Scenario: Providing synchronized 100 MHz common clock and separate 100 MHz reference for PCIe Gen 3/4 root complex and endpoint devices in server backplanes.

IC Role / Device Role / Timing Role: Quad-output clock generator delivering PCIe-compliant common clock and SRNS reference with sub-0.32 ps RMS jitter.

Use Value: Meets PCIe Gen 4 SRNS jitter spec (0.11–0.32 ps RMS) while consolidating four discrete oscillators into one IC, reducing BOM count and layout area.

Use Scenario: Generating 125 MHz, 156.25 MHz, and 312.5 MHz clocks for 1/10 GbE PHYs, switch fabric, and packet buffer interfaces in enterprise switches.

IC Role / Device Role / Timing Role: Programmable frequency translator converting a single 25 MHz crystal into multiple Ethernet-standard frequencies with low additive jitter.

Use Value: Achieves <0.7 ps RMS jitter at 125 MHz, satisfying IEEE 802.3 clause 49 requirements without external jitter cleaners.

FPGA/ASIC Clock Distribution

Broadcast Video Synchronization

Use Scenario: Supplying independent clocks to FPGA transceivers (e.g., 148.5 MHz for HDMI), logic fabric (100 MHz), DDR3 memory (400 MHz), and PCIe core (100 MHz) from a single source.

IC Role / Device Role / Timing Role: Configurable quad clock generator with per-output format and voltage selection for heterogeneous SoC/FPGA subsystems.

Use Value: Eliminates inter-clock skew between domains via programmable phase offset (<20 ps steps) and supports mixed-voltage I/O (1.8 V transceiver, 1.5 V DDR).

Use Scenario: Delivering SMPTE ST 2059-2–compliant 27 MHz, 74.25 MHz, and 148.5 MHz reference clocks to video encoders, decoders, and genlock circuits in broadcast infrastructure.

IC Role / Device Role / Timing Role: Low-jitter any-frequency synthesizer replacing TCXOs and fanout buffers in timing-critical video processing chains.

Use Value: Maintains <10 ps pk-pk period jitter at 148.5 MHz, ensuring frame-accurate synchronization across distributed video nodes.

Equivalent & Alternatives

The following parts are listed as comparable options for similar quad clock generator applications.

Alternative Part	Technical Difference	Application Difference	Selection Advice
Si5332A-D06189-GM	Higher integration: includes integrated crystal, smaller 3 × 3 mm QFN, lower power (32 mA typ), but limited to three outputs	Best suited for space-constrained designs where crystal integration and reduced output count are acceptable	Select when board area and bill-of-materials simplicity outweigh need for fourth output or external crystal flexibility
ICS853S01AGI-01LFT	Fixed-frequency, non-programmable quad LVDS clock generator; no I²C interface or MultiSynth™; 0.9 ps RMS jitter	Applicable only where exact standard frequencies (e.g., 100/125/156.25 MHz) are required without runtime reconfiguration	Choose for cost-sensitive, high-volume applications with static clock requirements and no need for field programming

Compared with Si5332A-D06189-GM and ICS853S01AGI-01LFT, SI5338L-B04358-GMR provides full I²C programmability, four independent outputs with voltage/format flexibility, and broader frequency coverage (0.16–710 MHz), making it optimal for systems requiring dynamic clock provisioning and multi-protocol support.

Availability

SI5338L-B04358-GMR is available at Aetrix Electronics and suitable for PCIe Gen 4 timing, 10 GbE switch clocking, and FPGA/ASIC clock distribution requiring stable component supply, long-term lifecycle assurance, and traceable sourcing.

Supply support for SI5338L-B04358-GMR includes scheduled delivery planning, volume procurement assistance, BOM continuity management, traceable sourcing, and lifecycle availability coordination for OEM customers, industrial embedded developers, connected-device designers, and electronics production programs.

Manufacturer

Skyworks Solutions is a global semiconductor company specializing in analog and mixed-signal connectivity solutions for wireless, broadband, automotive, and industrial markets.

The Si5338 product line delivers high-performance, software-configurable clock generation for datacenter, telecom, and computing systems demanding ultra-low jitter, multi-format outputs, and flexible reference input support.

FAQ

What is the maximum output frequency supported by SI5338L-B04358-GMR?

The SI5338L-B04358-GMR supports up to 710 MHz on LVPECL/LVDS/CML outputs, 350 MHz on SSTL/HSTL, and 250 MHz on HCSL. For frequencies above 350 MHz, only two unique outputs may operate simultaneously at Fvco/4 and Fvco/6 rates. This capability enables direct clocking of high-speed SerDes lanes without external frequency multiplication.

Does SI5338L-B04358-GMR support PCIe Gen 4 Separate Reference No Spread (SRNS) compliance?

Yes, SI5338L-B04358-GMR meets PCIe Gen 4 SRNS requirements with 0.11–0.32 ps RMS jitter when configured with a PLL bandwidth of 2–4 MHz or 2–5 MHz and CDR set to 10 MHz. This is verified per PCI-Express Base Specification 4.0 rev. 0.5 and measured using the Skyworks PCIe Clock Jitter Tool.

Can SI5338L-B04358-GMR generate different output voltages on each channel?

Yes, SI5338L-B04358-GMR provides four independent VDDOx supplies (VDDO0–VDDO3), each configurable for 1.5 V, 1.8 V, 2.5 V, or 3.3 V. This allows simultaneous LVDS (2.5 V), HCSL (1.8 V), and CMOS (3.3 V) outputs, simplifying interface to mixed-voltage FPGAs and ASICs without external level shifters.

How is SI5338L-B04358-GMR programmed, and what tools are required?

SI5338L-B04358-GMR is programmed via its I²C/SMBus-compatible interface using Skyworks' ClockBuilder Pro software. This GUI tool enables full register configuration, jitter simulation, and .c file generation for embedded initialization. No external hardware programmer is needed-standard I²C host controllers suffice.

What reference inputs does SI5338L-B04358-GMR accept?

SI5338L-B04358-GMR accepts six reference inputs: two differential pairs (IN1/IN2, IN5/IN6) for 5–710 MHz; two single-ended pins (IN3/IN4) for CMOS (5–200 MHz), SSTL (5–350 MHz), or HSTL (5–350 MHz); and on-chip crystal oscillator support for 8–30 MHz fundamental-mode crystals.

SI5338L-B04358-GMR Specifications

Product attributes: Attribute value

Manufacturer:: Skyworks Solutions Inc.

Series:: MultiSynth™

Package/Case:: 24-VFQFN Exposed Pad

Packaging:: Tape & Reel (TR)

Product Status:: Active

Programmable:: Not Verified

PLL:: -

Main Purpose:: -

Input:: -

Output:: -

Number of Circuits:: -

Ratio - Input:Output:: -

Differential - Input:Output:: -

Frequency - Max:: -

Voltage - Supply:: -

Operating Temperature:: -

Mounting Type:: Surface Mount

Grade:: -

Qualification:: -

Supplier Device Package:: 24-QFN (4x4)

SI5338L-B04358-GMR FAQ

1.How can I place an order for SI5338L-B04358-GMR through Aetrix?

Please submit a Request for Quotation (RFQ) for SI5338L-B04358-GMR on Aetrix. Our sales agent will provide a competitive quotation and guide you through the order confirmation once you accept the terms.

2.Are the price and stock information for SI5338L-B04358-GMR reliable?

The price and inventory of SI5338L-B04358-GMR are updated periodically and may fluctuate due to market conditions. Stock and pricing data are typically refreshed every 24 hours. Quotation validity for SI5338L-B04358-GMR is usually 5 days.

3.What payment methods are accepted for SI5338L-B04358-GMR?

We accept Wire Transfer, PayPal, Credit Card, Western Union, MoneyGram, and Escrow for SI5338L-B04358-GMR transactions.

Note: Certain payment methods may incur a processing fee.

4.How is shipping managed for SI5338L-B04358-GMR?

SI5338L-B04358-GMR orders can be shipped via leading logistics carriers, including DHL, UPS, FedEx, TNT, or Registered Mail.

Once your SI5338L-B04358-GMR order is processed, you will receive an email with the shipment details and tracking number.

Note: Tracking information may take up to 24 hours to appear. Express delivery typically takes 3–5 business days.

5.How can I obtain technical support or documentation for SI5338L-B04358-GMR?

For technical support, including SI5338L-B04358-GMR datasheets, pinout diagrams, or application guidance, please contact our engineering support team. They can provide detailed documentation and assistance for your SI5338L-B04358-GMR requirements.

6.How does Aetrix verify that SI5338L-B04358-GMR is sourced from the original manufacturer or authorized distributors?

All SI5338L-B04358-GMR products on Aetrix are procured from qualified distributors and authorized channels. Our dedicated quality assurance team conducts strict verification, including traceability checks and, if necessary, third-party testing. This ensures that SI5338L-B04358-GMR meets industry standards.

7.What is the process for return or replacement of SI5338L-B04358-GMR?

All SI5338L-B04358-GMR units undergo pre-shipment inspection (PSI). If there is an issue with SI5338L-B04358-GMR, returns or replacements are accepted under the following conditions:

1.Quantity discrepancies, incorrect items, or visible external defects (such as breakage or corrosion), acknowledged by Aetrix.

2.The issue is reported within 90 days of delivery.

3.The SI5338L-B04358-GMR part is unused and in its original packaging.

Return procedure for SI5338L-B04358-GMR:

1.Submit a request within 90 days.

2.Obtain a Return Material Authorization (RMA) from Aetrix.

Tech Hub

2026-09-09 Counterfeit Electronic Components: How to Detect, Authenticate, and Test Suspect Parts

Counterfeit components can hide behind convincing markings and passing basic function tests. This engineering reference covers source traceability, external inspection, X-ray, XRF, electrical testing, …

2026-09-08 Obsolete Electronic Components: How to Source and Evaluate Replacements

A practical engineering and sourcing framework covering lifecycle verification, lifetime-buy calculations, replacement qualification, supplier checks and counterfeit-risk controls.

2026-09-07 TTL vs CMOS Logic Levels: 74HC and 74HCT Compatibility Explained

TTL and CMOS logic families differ in thresholds, loading, output drive, power and timing. This engineering guide compares 74HC and 74HCT, calculates noise margins and checks 3.3 V/5 V compatibility.

2026-09-04 Logic Level Shifter: How to Connect 3.3V and 5V Logic Safely

A practical engineering guide to 3.3V and 5V logic compatibility, input thresholds, resistor dividers, translator ICs, MOSFET level shifting, I2C pull-ups, timing limits and power-sequencing risks.

2026-09-03 74HC595 vs TPIC6B595: Output Drive, Pinout, Current, and Load Selection

The 74HC595 uses push-pull logic outputs, while the TPIC6B595 uses 50 V open-drain DMOS sinks for higher-power loads. This guide compares timing, current limits, 3.3 V interfacing, load wiring, thermal…

2026-09-02 74HC595 Pinout, Timing, Output Current, and Applications

The 74HC595 converts serial data into eight stable parallel outputs. This guide covers pin functions, shift and storage timing, OE and MR behavior, drive-current limits, cascading, voltage compatibilit…

2026-09-01 Latch vs Flip-Flop: Timing, Differences and Design Choices

A technical comparison of level-sensitive latches and edge-triggered flip-flops, covering timing windows, setup and hold limits, master–slave operation, time borrowing, race-through, HDL inference and…

2026-08-30 D Latch Circuit: Truth Table, Timing, ICs and Applications

A D latch stores one bit while Enable controls when data can pass. This reference covers gate-level operation, truth tables, transparency, setup and hold timing, LE versus OE, common ICs and practical …

2026-08-28 SR Latch Explained: NOR and NAND Circuits, Truth Tables, and Applications

An SR latch stores one bit through cross-coupled feedback. This engineering reference covers NOR and NAND implementations, truth tables, forbidden-state recovery, gated operation, switch debouncing, fa…

2026-08-27 Latch Circuit: SR and D Latches, Truth Tables, Timing, and Applications

Latch circuits retain one bit through feedback. This technical reference covers SR and D latches, truth tables, transparency, timing limits, latch-versus-flip-flop behavior, applications and common log…