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Home > Products > Integrated Circuits (ICs) > Clock/Timing > Application Specific Clock/Timing

Skyworks Solutions Inc. SI5338L-B04837-GMR

Name: SI5338L-B04837-GMR
Brand: Skyworks Solutions Inc.
SKU: SI5338L-B04837-GMR
Price: 2.40 USD
Availability: InStock
Rating: 5 (2 reviews)

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Part No.:: SI5338L-B04837-GMR

Manufacturer:: Skyworks Solutions Inc.

Category:: Application Specific Clock/Timing

Package:: 24-VFQFN Exposed Pad

Datasheet:: SI5338L-B04837-GMR.pdf

Description:: I2C CONTROL, 4-OUTPUT, ANY FREQU

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Product details

Overview

SI5338L-B04837-GMR from Skyworks Solutions is a quad-output, I²C-programmable clock generator with MultiSynth™ frequency synthesis. It delivers four independent, any-frequency outputs (0.16–710 MHz), supports LVPECL/LVDS/HCSL/CMOS/SSTL/HSTL formats, achieves 0.7 ps RMS phase jitter (typ), and operates from 1.8/2.5/3.3 V core supply in PCIe Gen 1–4 and Ethernet timing applications.

For engineers reviewing the SI5338L-B04837-GMR datasheet, SI5338L-B04837-GMR pinout, SI5338L-B04837-GMR application, or SI5338L-B04837-GMR equivalent, key selection criteria include differential output jitter compliance with PCIe Gen 4 SRNS, independent per-output voltage control (1.5–3.3 V), spread-spectrum capability (0.5–5.0% at 33–63 kHz), and 24-QFN package footprint compatibility.

Technical Context

The SI5338L-B04837-GMR integrates a high-stability PLL with two synthesis stages: a reference-stage PLL (loop bandwidth 1.6 MHz) and four independent MultiSynth™ fractional-N dividers. Each output driver features programmable format, voltage, phase offset (±45 ns, <20 ps step), and frequency increment/decrement (1 ppm step, glitchless).

It accepts flexible input references: external crystal (8–30 MHz), CMOS (5–200 MHz), SSTL/HSTL (5–350 MHz), or differential (5–710 MHz). Loss-of-lock and loss-of-signal alarms, I²C/SMBus interface, and ClockBuilder Pro software support full configuration without hardware changes.

Key Specifications

Parameter	Value and Actual Design Meaning
Output count & type	Four differential outputs (CLK0A/B to CLK3A/B); supports up to eight single-ended or mixed configurations
Frequency range	0.16–710 MHz per output; integer/fractional synthesis with 1 ppb resolution
Phase jitter (RMS)	0.7 ps typical (12 kHz–20 MHz); meets PCIe Gen 4 Common Clock and SRNS requirements
Supply voltages	Core: 1.8/2.5/3.3 V ±10%; output buffers: independently configurable 1.5/1.8/2.5/3.3 V
Operating temperature	–40 °C to +85 °C; qualified for industrial embedded and telecom line card environments
Package	24-pin QFN, 4 mm × 4 mm, 0.5 mm pitch; RoHS-compliant, moisture-sensitive level 3
Control interface	I²C/SMBus-compatible (up to 400 kHz); supports ClockBuilder Pro programming and pin-controlled frequency/phase adjustment

Pinout & Package

SI5338L-B04837-GMR uses a 24-lead QFN package (4 mm × 4 mm, 0.5 mm pitch) with exposed thermal pad. Pin assignments are fixed per Si5338 family specification and validated for this variant.

Pin/Terminal	Circuit Role	Design Meaning
IN1/IN2, IN5/IN6	Differential clock inputs	Accept 5–710 MHz AC-coupled differential references; require external 100 Ω termination
IN3/IN4	Single-ended clock inputs	Support 5–200 MHz CMOS, 5–350 MHz SSTL/HSTL; DC-coupled with internal bias
CLK0A/CLK0B to CLK3A/CLK3B	Differential clock outputs	Four independent pairs; each configurable for LVPECL/LVDS/HCSL/CML with per-driver VDDO
VDDO0–VDDO3	Output buffer supplies	Independent 1.5/1.8/2.5/3.3 V rails per output pair; enable mixed-voltage system interfacing
SCL/SDA	I²C interface	Standard bidirectional bus (400 kHz max); supports device configuration and status readback
INTR	Interrupt output	Open-drain alarm signal for loss-of-lock and loss-of-signal events
VDD	Core supply	Single 1.8/2.5/3.3 V rail; PSRR optimized for low-noise clock generation
GND / RSVD_GND	Ground terminals	Eight dedicated ground pins including thermal pad connection; critical for jitter performance

Key Features

Feature	Design Value
MultiSynth™ synthesis	Enables true zero-ppm accuracy on all four outputs simultaneously via independent fractional-N dividers
PCIe Gen 4 compliance	Meets SRNS jitter spec (0.11–0.32 ps RMS) with 2–5 MHz PLL bandwidth and CDR = 10 MHz
Per-output voltage control	Each of four output drivers selectable between 1.5 V, 1.8 V, 2.5 V, or 3.3 V - eliminates level-shifting ICs
Glitchless frequency tuning	Independent ±1 ppm step frequency increment/decrement via pin or I²C; no output interruption
Programmable spread spectrum	Configurable on any output: 0.5–5.0% spread, 33–63 kHz modulation rate, down-spread default
Zero-delay mode support	External feedback path enables synchronous clock distribution with matched input-to-output latency

Applications

PCIe Gen 4 Switch Timing	Ethernet Switch/Routing
Use Scenario: High-speed PCIe Gen 4 switch fabric requiring four synchronized clocks (100 MHz, 250 MHz, 333 MHz, 500 MHz) with sub-0.35 ps RMS jitter. IC Role / Device Role / Timing Role: Primary clock generator providing common-clock architecture compliant with PCIe Base Spec 4.0 rev 0.5. Use Value: Eliminates four discrete oscillators; meets SRNS jitter requirement (0.11–0.32 ps RMS) without external jitter cleaners.	Use Scenario: 10 GbE/25 GbE switch ASIC requiring multiple low-jitter clocks (156.25 MHz, 312.5 MHz, 625 MHz) with precise phase alignment. IC Role / Device Role / Timing Role: Quad-output timing source delivering differential HCSL and LVDS clocks with <20 ps phase step resolution. Use Value: Enables deterministic skew control across SerDes lanes; supports IEEE 802.3bj KR/KP FEC timing constraints.
Broadcast Video Timing	FPGA Processor Clocking
Use Scenario: SMPTE ST 2082-1 (12G-SDI) video router needing 74.25 MHz, 148.5 MHz, and 297 MHz clocks with <1 ps RMS jitter for pixel-accurate sampling. IC Role / Device Role / Timing Role: Precision clock synthesizer generating multiple video-standard frequencies from a single 27 MHz crystal reference. Use Value: Achieves 0.7 ps RMS jitter (typ) - below SMPTE ST 2082-1 jitter mask limit of 1.2 ps RMS.	Use Scenario: Xilinx Versal ACAP and Intel Agilex FPGA platform requiring separate clocks for PL, PS, DDR, and transceivers (e.g., 100 MHz, 200 MHz, 300 MHz, 500 MHz). IC Role / Device Role / Timing Role: Configurable clock source supporting mixed-signal I/O banks with independent voltage and format per output. Use Value: Per-output VDDO selection (1.5–3.3 V) matches FPGA bank voltages; eliminates discrete LDOs and level shifters.

PCIe Gen 4 Switch Timing

Ethernet Switch/Routing

Use Scenario: High-speed PCIe Gen 4 switch fabric requiring four synchronized clocks (100 MHz, 250 MHz, 333 MHz, 500 MHz) with sub-0.35 ps RMS jitter.

IC Role / Device Role / Timing Role: Primary clock generator providing common-clock architecture compliant with PCIe Base Spec 4.0 rev 0.5.

Use Value: Eliminates four discrete oscillators; meets SRNS jitter requirement (0.11–0.32 ps RMS) without external jitter cleaners.

Use Scenario: 10 GbE/25 GbE switch ASIC requiring multiple low-jitter clocks (156.25 MHz, 312.5 MHz, 625 MHz) with precise phase alignment.

IC Role / Device Role / Timing Role: Quad-output timing source delivering differential HCSL and LVDS clocks with <20 ps phase step resolution.

Use Value: Enables deterministic skew control across SerDes lanes; supports IEEE 802.3bj KR/KP FEC timing constraints.

Broadcast Video Timing

FPGA Processor Clocking

Use Scenario: SMPTE ST 2082-1 (12G-SDI) video router needing 74.25 MHz, 148.5 MHz, and 297 MHz clocks with <1 ps RMS jitter for pixel-accurate sampling.

IC Role / Device Role / Timing Role: Precision clock synthesizer generating multiple video-standard frequencies from a single 27 MHz crystal reference.

Use Value: Achieves 0.7 ps RMS jitter (typ) - below SMPTE ST 2082-1 jitter mask limit of 1.2 ps RMS.

Use Scenario: Xilinx Versal ACAP and Intel Agilex FPGA platform requiring separate clocks for PL, PS, DDR, and transceivers (e.g., 100 MHz, 200 MHz, 300 MHz, 500 MHz).

IC Role / Device Role / Timing Role: Configurable clock source supporting mixed-signal I/O banks with independent voltage and format per output.

Use Value: Per-output VDDO selection (1.5–3.3 V) matches FPGA bank voltages; eliminates discrete LDOs and level shifters.

Equivalent & Alternatives

The following parts are listed as comparable options for similar quad-output clock generator applications.

Alternative Part	Technical Difference	Application Difference	Selection Advice
Si5332A-D06889-GM	Higher integration: includes integrated crystal; lower jitter (0.35 ps RMS typ); supports up to 10 outputs	Targeted at space-constrained designs where crystal placement is problematic; requires different PCB layout	Select when board area is constrained and ultra-low jitter is required; not drop-in compatible due to different pinout and crystal integration
ICS8430I-01LG	Fixed-frequency, non-programmable; 4 LVDS outputs; 1.2 ps RMS jitter; 3.3 V only	Limited to static clock trees; no I²C or frequency agility; no spread spectrum	Choose for cost-sensitive, fixed-frequency applications where programmability is unnecessary and jitter margin >0.5 ps is acceptable

Compared with Si5332A-D06889-GM and ICS8430I-01LG, SI5338L-B04837-GMR offers field-programmable flexibility and PCIe Gen 4 SRNS compliance at lower BOM cost than integrated-crystal alternatives, while providing significantly greater configurability than fixed-frequency solutions.

Availability

SI5338L-B04837-GMR is available at Aetrix Electronics and suitable for PCIe Gen 4 switch timing, Ethernet switching/routing, broadcast video timing, and FPGA processor clocking applications requiring stable component supply, long-term lifecycle support, and guaranteed traceable sourcing.

Supply support for SI5338L-B04837-GMR includes scheduled delivery planning, volume procurement assistance, BOM continuity management, traceable sourcing, and lifecycle availability coordination for OEM customers, industrial embedded developers, connected-device designers, and electronics production programs.

Manufacturer

Skyworks Solutions is a global semiconductor company specializing in analog and mixed-signal connectivity solutions for wireless, broadband, automotive, and industrial markets.

The Si5338 product line was designed for high-performance, multi-protocol timing in data center, telecom, and broadcast infrastructure - enabling consolidation of discrete oscillators into a single programmable clock generator with PCIe, Ethernet, and video compliance.

FAQ

What is the maximum output frequency supported by SI5338L-B04837-GMR?

The SI5338L-B04837-GMR supports up to 710 MHz on LVPECL/LVDS/CML outputs, 350 MHz on SSTL/HSTL, 250 MHz on HCSL, and 200 MHz on CMOS. Only two unique frequencies above 350 MHz may be generated simultaneously (Fvco/4 and Fvco/6), as defined in the Si5338 functional description. All frequencies are synthesized with MultiSynth™ technology and verified in the official datasheet Table 6.

Does SI5338L-B04837-GMR support PCIe Gen 4 Separate Reference No Spread (SRNS) mode?

Yes, SI5338L-B04837-GMR is explicitly qualified for PCIe Gen 4 SRNS operation with 0.11–0.32 ps RMS jitter (typ/max) when configured with 2–5 MHz PLL bandwidth and CDR = 10 MHz, as specified in Table 12 of the Skyworks Si5338 datasheet Rev. 1.6. This compliance is validated using the Skyworks PCIe Clock Jitter Tool and Intel Clock Jitter Tool v1.6.4.

How many independent supply voltages can be applied to the output buffers of SI5338L-B04837-GMR?

SI5338L-B04837-GMR provides four independent VDDO supply pins (VDDO0 to VDDO3), each configurable for 1.5 V, 1.8 V, 2.5 V, or 3.3 V. This allows direct interfacing with mixed-voltage FPGA I/O banks, ASIC SerDes, and memory controllers without external level shifters - a capability confirmed in the "Highly-configurable output drivers" feature list and Table 3 DC characteristics.

Can SI5338L-B04837-GMR generate spread-spectrum clocking (SSC) on individual outputs?

Yes, SI5338L-B04837-GMR supports independent spread-spectrum clocking on any output: spread range 0.5–5.0%, modulation rate 33–63 kHz, and down-spread default. This is implemented per-output via register configuration and verified in Table 5 (Performance Characteristics) and the "Highly configurable spread spectrum" feature bullet of the datasheet.

What is the core supply current consumption of SI5338L-B04837-GMR under typical operating conditions?

SI5338L-B04837-GMR draws 45 mA typical core supply current (IDD) when all outputs run at 100 MHz with a 25 MHz reference clock, as specified in Table 3 (DC Characteristics). In buffer mode (PLL bypass), core current drops to 12 mA typical (IDDB) with 50 MHz reference - values measured across –40 °C to +85 °C and all supported supply voltages.

SI5338L-B04837-GMR Specifications

Product attributes: Attribute value

Manufacturer:: Skyworks Solutions Inc.

Series:: MultiSynth™

Package/Case:: 24-VFQFN Exposed Pad

Packaging:: Tape & Reel (TR)

Product Status:: Active

Programmable:: Not Verified

PLL:: -

Main Purpose:: -

Input:: -

Output:: -

Number of Circuits:: -

Ratio - Input:Output:: -

Differential - Input:Output:: -

Frequency - Max:: -

Voltage - Supply:: -

Operating Temperature:: -

Mounting Type:: Surface Mount

Grade:: -

Qualification:: -

Supplier Device Package:: 24-QFN (4x4)

SI5338L-B04837-GMR FAQ

1.How can I place an order for SI5338L-B04837-GMR through Aetrix?

Please submit a Request for Quotation (RFQ) for SI5338L-B04837-GMR on Aetrix. Our sales agent will provide a competitive quotation and guide you through the order confirmation once you accept the terms.

2.Are the price and stock information for SI5338L-B04837-GMR reliable?

The price and inventory of SI5338L-B04837-GMR are updated periodically and may fluctuate due to market conditions. Stock and pricing data are typically refreshed every 24 hours. Quotation validity for SI5338L-B04837-GMR is usually 5 days.

3.What payment methods are accepted for SI5338L-B04837-GMR?

We accept Wire Transfer, PayPal, Credit Card, Western Union, MoneyGram, and Escrow for SI5338L-B04837-GMR transactions.

Note: Certain payment methods may incur a processing fee.

4.How is shipping managed for SI5338L-B04837-GMR?

SI5338L-B04837-GMR orders can be shipped via leading logistics carriers, including DHL, UPS, FedEx, TNT, or Registered Mail.

Once your SI5338L-B04837-GMR order is processed, you will receive an email with the shipment details and tracking number.

Note: Tracking information may take up to 24 hours to appear. Express delivery typically takes 3–5 business days.

5.How can I obtain technical support or documentation for SI5338L-B04837-GMR?

For technical support, including SI5338L-B04837-GMR datasheets, pinout diagrams, or application guidance, please contact our engineering support team. They can provide detailed documentation and assistance for your SI5338L-B04837-GMR requirements.

6.How does Aetrix verify that SI5338L-B04837-GMR is sourced from the original manufacturer or authorized distributors?

All SI5338L-B04837-GMR products on Aetrix are procured from qualified distributors and authorized channels. Our dedicated quality assurance team conducts strict verification, including traceability checks and, if necessary, third-party testing. This ensures that SI5338L-B04837-GMR meets industry standards.

7.What is the process for return or replacement of SI5338L-B04837-GMR?

All SI5338L-B04837-GMR units undergo pre-shipment inspection (PSI). If there is an issue with SI5338L-B04837-GMR, returns or replacements are accepted under the following conditions:

1.Quantity discrepancies, incorrect items, or visible external defects (such as breakage or corrosion), acknowledged by Aetrix.

2.The issue is reported within 90 days of delivery.

3.The SI5338L-B04837-GMR part is unused and in its original packaging.

Return procedure for SI5338L-B04837-GMR:

1.Submit a request within 90 days.

2.Obtain a Return Material Authorization (RMA) from Aetrix.

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