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Home > Products > Integrated Circuits (ICs) > Clock/Timing > Application Specific Clock/Timing

Skyworks Solutions Inc. SI5338L-B04838-GMR

Name: SI5338L-B04838-GMR
Brand: Skyworks Solutions Inc.
SKU: SI5338L-B04838-GMR
Price: 2.40 USD
Availability: InStock
Rating: 5 (2 reviews)

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Part No.:: SI5338L-B04838-GMR

Manufacturer:: Skyworks Solutions Inc.

Category:: Application Specific Clock/Timing

Package:: 24-VFQFN Exposed Pad

Datasheet:: SI5338L-B04838-GMR.pdf

Description:: I2C CONTROL, 4-OUTPUT, ANY FREQU

Quantity:: RFQ Add To RFQ list

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Product details

Overview

SI5338L-B04838-GMR from Skyworks Solutions is an I²C-programmable quad clock generator with four independently configurable differential or single-ended outputs, 0.7 ps RMS typical phase jitter, PCIe Gen 1–4 Common Clock and Gen 3 SRNS compliance, and operation from 1.8/2.5/3.3 V core supply in a 4 × 4 mm 24-QFN package. It replaces up to four crystal oscillators in high-speed serial interface timing applications.

For engineers reviewing the SI5338L-B04838-GMR datasheet, SI5338L-B04838-GMR pinout, SI5338L-B04838-GMR application, or SI5338L-B04838-GMR equivalent, key selection criteria include PCIe Gen 4 jitter compliance (0.15–0.45 ps RMS), independent output voltage per driver (1.5/1.8/2.5/3.3 V), MultiSynth™ frequency synthesis resolution (1 ppb), spread-spectrum control (0.5–5.0% spread, 33–63 kHz modulation), and loss-of-lock/loss-of-signal alarm support.

Technical Context

The SI5338L-B04838-GMR implements a two-stage PLL architecture: Stage 1 uses a VCO with programmable N-divider for reference-to-VCO frequency translation; Stage 2 employs four independent MultiSynth™ fractional-N synthesizers, each with M/P dividers, enabling integer or fractional output synthesis from 0.16 MHz to 710 MHz. Each output supports format-selectable drivers (LVPECL/LVDS/HCSL/CMOS/SSTL/HSTL) with independent VDDO supplies.

Input flexibility includes external crystal (8–30 MHz), CMOS (5–200 MHz), SSTL/HSTL (5–350 MHz), or differential (5–710 MHz) references. The device supports glitchless frequency increment/decrement in 1 ppm steps and phase adjustment in <20 ps steps per output, with external feedback mode enabling zero-delay operation.

Key Specifications

Parameter	Value and Actual Design Meaning
Phase Jitter (RMS)	0.7 ps typical (12 kHz–20 MHz); meets PCIe Gen 4 common clock jitter spec (0.15–0.45 ps RMS).
Output Count & Type	4 independent outputs; supports LVPECL/LVDS/HCSL/CMOS/SSTL/HSTL formats with selectable drive strength.
Frequency Range	0.16–710 MHz per output; up to two outputs >350 MHz simultaneously (Fvco/4 and Fvco/6).
Supply Voltages	Core: 1.8/2.5/3.3 V ±10%; Output buffers: 1.4–3.63 V per VDDOx rail - enables mixed-voltage system interfacing.
Synthesis Resolution	1 ppb frequency step size; enables precise clock alignment for SerDes CDR lock and deterministic latency control.
Spread Spectrum	Configurable on any output: 0.5–5.0% down-spread, 33–63 kHz modulation rate - reduces EMI peak emissions.
Operating Temp	–40 °C to +85 °C ambient; qualified for industrial and telecom line card deployment.

Pinout & Package

SI5338L-B04838-GMR is housed in a 4 × 4 mm, 24-lead QFN package with exposed thermal pad. Pin assignments are fixed per the Si5338 family: IN1/IN2 (diff clk 1), IN3/IN4 (SE clk 1/2), IN5/IN6 (diff clk 2/3), CLK0A/CLK0B through CLK3A/CLK3B (four differential output pairs), VDD (core supply), VDDO0–VDDO3 (independent output buffer supplies), SCL/SDA (I²C interface), INTR (interrupt output), and RSVD_GND (reserved ground).

Pin/Terminal	Circuit Role	Design Meaning
CLK0A / CLK0B	Differential Output Pair 0	LVPECL/LVDS/HCSL/CML-capable; independently configured frequency, format, and VDDO0 voltage.
CLK1A / CLK1B	Differential Output Pair 1	Supports same format/frequency range as CLK0; isolated skew path with <100 ps output-output skew (Rn=11).
CLK2A / CLK2B	Differential Output Pair 2	Configurable for PCIe Gen 4 100 MHz HCSL or broadcast video 27 MHz LVDS with independent phase offset.
CLK3A / CLK3B	Differential Output Pair 3	Enables dual-clock domain generation (e.g., 125 MHz GbE + 156.25 MHz FPGA fabric) without external buffers.
IN1 / IN2	Differential Reference Input 1	Accepts 5–710 MHz AC-coupled differential clock; internal 10 kΩ termination and 3.5 pF capacitance.
IN3 / IN4	Single-Ended Reference Inputs	CMOS/SSTL/HSTL-compatible; 5–350 MHz range; VIH = 0.7×VDD, VIL = 0.3×VDD, 4 pF input capacitance.
VDDO0–VDDO3	Independent Output Buffer Supplies	Each powers one output pair; allows mixed-voltage operation (e.g., CLK0 = 1.8 V LVDS, CLK1 = 3.3 V CMOS).
SCL / SDA	I²C/SMBus Interface	Standard 100/400 kHz operation; supports ClockBuilder Pro programming and real-time register readback.
INTR	Interrupt Output	Open-drain active-low signal indicating loss-of-lock, loss-of-signal, or configuration error events.

Key Features

Feature	Design Value
MultiSynth™ Synthesis	Four independent fractional-N synthesizers enable true zero-ppm accuracy on all outputs - eliminates frequency drift across temperature and voltage.
PCIe Gen 4 Compliance	Meets Common Clock jitter spec (0.15–0.45 ps RMS) and SRNS requirements - validated using Intel Clock Jitter Tool and Skyworks PCIe Jitter Tool.
Glitchless Frequency Tuning	1 ppm step size with pin-controlled update time of 667 ns (>18 MHz) or 10–12 periods (<18 MHz) - enables dynamic SERDES rate adaptation without clock interruption.
Programmable Phase Offset	±45 ns range in <20 ps steps per output - supports precise skew compensation between parallel data lanes (e.g., DDR, PCIe x16).
Flexible Reference Support	Simultaneous acceptance of crystal (8–30 MHz), CMOS (5–200 MHz), and differential (5–710 MHz) inputs - simplifies board-level clock tree consolidation.

Applications

Ethernet Switch/Routing	PCIe Gen 1–4 Timing
Use Scenario: 10 GbE/25 GbE switch fabric requiring low-jitter clocks for PHY and MAC layers with independent frequency domains. IC Role / Device Role / Timing Role: Quad clock generator providing 156.25 MHz (XAUI), 312.5 MHz (XFI), 125 MHz (GbE), and 100 MHz (PCIe) from single reference. Use Value: Eliminates four discrete oscillators; achieves <0.7 ps RMS jitter on all outputs - ensures IEEE 802.3bj compliance and BER <10⁻¹².	Use Scenario: Server motherboard with CPU, GPU, and NVMe SSDs requiring synchronized PCIe Gen 4 reference clocks. IC Role / Device Role / Timing Role: PCIe Common Clock generator delivering four 100 MHz HCSL outputs with matched skew and Gen 4 SRNS-compliant jitter. Use Value: Meets PCIe Base Spec 4.0 rev 0.5 jitter limits (0.15–0.45 ps RMS); enables single-board timing consolidation with no layout rework.
Broadcast Video/Audio Timing	FPGA & Processor Clocking
Use Scenario: SMPTE ST 2082/2110 IP video router needing genlock-capable 27 MHz, 74.25 MHz, and 148.5 MHz clocks with sub-ns phase alignment. IC Role / Device Role / Timing Role: Any-frequency clock synthesizer generating SMPTE-compliant frequencies from 25 MHz crystal reference with programmable initial phase offset. Use Value: Achieves ±20 ps phase step resolution and <100 ps output-output skew - enables frame-accurate multi-channel video synchronization.	Use Scenario: High-end FPGA-based test equipment requiring separate clocks for logic fabric (100 MHz), ADC sampling (125 MHz), transceiver banks (322.265625 MHz), and PCIe host interface (100 MHz). IC Role / Device Role / Timing Role: Configurable quad clock source supporting mixed-signal SoC timing with independent voltage and format per domain. Use Value: Delivers 1.8 V LVDS, 2.5 V HCSL, and 3.3 V CMOS outputs simultaneously - removes need for level translators and reduces BOM count.

Ethernet Switch/Routing

PCIe Gen 1–4 Timing

Use Scenario: 10 GbE/25 GbE switch fabric requiring low-jitter clocks for PHY and MAC layers with independent frequency domains.

IC Role / Device Role / Timing Role: Quad clock generator providing 156.25 MHz (XAUI), 312.5 MHz (XFI), 125 MHz (GbE), and 100 MHz (PCIe) from single reference.

Use Value: Eliminates four discrete oscillators; achieves <0.7 ps RMS jitter on all outputs - ensures IEEE 802.3bj compliance and BER <10⁻¹².

Use Scenario: Server motherboard with CPU, GPU, and NVMe SSDs requiring synchronized PCIe Gen 4 reference clocks.

IC Role / Device Role / Timing Role: PCIe Common Clock generator delivering four 100 MHz HCSL outputs with matched skew and Gen 4 SRNS-compliant jitter.

Use Value: Meets PCIe Base Spec 4.0 rev 0.5 jitter limits (0.15–0.45 ps RMS); enables single-board timing consolidation with no layout rework.

Broadcast Video/Audio Timing

FPGA & Processor Clocking

Use Scenario: SMPTE ST 2082/2110 IP video router needing genlock-capable 27 MHz, 74.25 MHz, and 148.5 MHz clocks with sub-ns phase alignment.

IC Role / Device Role / Timing Role: Any-frequency clock synthesizer generating SMPTE-compliant frequencies from 25 MHz crystal reference with programmable initial phase offset.

Use Value: Achieves ±20 ps phase step resolution and <100 ps output-output skew - enables frame-accurate multi-channel video synchronization.

Use Scenario: High-end FPGA-based test equipment requiring separate clocks for logic fabric (100 MHz), ADC sampling (125 MHz), transceiver banks (322.265625 MHz), and PCIe host interface (100 MHz).

IC Role / Device Role / Timing Role: Configurable quad clock source supporting mixed-signal SoC timing with independent voltage and format per domain.

Use Value: Delivers 1.8 V LVDS, 2.5 V HCSL, and 3.3 V CMOS outputs simultaneously - removes need for level translators and reduces BOM count.

Equivalent & Alternatives

The following parts are listed as comparable options for similar quad clock generator applications.

Alternative Part	Technical Difference	Application Difference	Selection Advice
Si5332A-D06899-GM	Higher integration: 8 outputs, integrated crystal, lower jitter (0.35 ps RMS), supports JESD204B deterministic latency.	Targeted at JESD204B ADC/DAC systems and 5G wireless infrastructure where deterministic delay matters more than cost.	Select when needing >4 outputs, ultra-low jitter, or crystal-integrated solution; not drop-in due to different pinout and register map.
ICS8430I-01T	Fixed-frequency quad LVDS generator (no I²C programming); 1.2 ps RMS jitter; 3.3 V only; no spread spectrum or phase adjustment.	Suitable for legacy systems with static clock trees and no requirement for dynamic tuning or EMI reduction.	Select only for cost-sensitive, non-programmable applications where frequency flexibility and advanced features are unnecessary.

Compared with Si5332A-D06899-GM and ICS8430I-01T, SI5338L-B04838-GMR offers optimal balance of programmability, PCIe Gen 4 compliance, and 4-output flexibility in a compact QFN - making it ideal for mid-tier networking and embedded computing where field-upgradable timing is required.

Availability

SI5338L-B04838-GMR is available at Aetrix Electronics and suitable for Ethernet switch/router, PCIe Gen 1–4 timing, broadcast video/audio timing, and FPGA & processor clocking applications requiring stable component supply, long-term lifecycle support, and guaranteed traceable sourcing.

Supply support for SI5338L-B04838-GMR includes scheduled delivery planning, volume procurement assistance, BOM continuity management, traceable sourcing, and lifecycle availability coordination for OEM customers, industrial embedded developers, connected-device designers, and electronics production programs.

Manufacturer

Skyworks Solutions is a global leader in analog and mixed-signal semiconductors, specializing in RF, mobile, infrastructure, and timing solutions with over 30 years of RF and clocking expertise.

The Si5338 product line was designed for high-performance, programmable clock generation in datacenter, telecom, and broadcast systems - emphasizing low jitter, multi-format output flexibility, and seamless integration into complex timing architectures.

FAQ

What is the maximum output frequency supported by SI5338L-B04838-GMR?

The SI5338L-B04838-GMR supports up to 710 MHz on LVPECL/LVDS/CML outputs, 350 MHz on SSTL/HSTL, 250 MHz on HCSL, and 200 MHz on CMOS. However, only two unique frequencies above 350 MHz can be generated simultaneously - specifically Fvco/4 and Fvco/6 - as defined by the MultiSynth™ architecture in the official Si5338 datasheet Rev. 1.6, Table 6.

Does SI5338L-B04838-GMR support PCIe Gen 4 timing requirements?

Yes, SI5338L-B04838-GMR meets PCIe Gen 4 Common Clock jitter specifications (0.15–0.45 ps RMS, 10 kHz–50 MHz) and SRNS compliance when configured per AN562 guidelines. Validation uses the Skyworks PCIe Clock Jitter Tool and Intel Clock Jitter Tool v1.6.4, with measurements performed on 100 MHz HCSL outputs under specified PLL bandwidth (2–5 MHz) and CDR (10 MHz) conditions.

Can SI5338L-B04838-GMR generate different output voltages on each channel?

Yes, SI5338L-B04838-GMR provides independent VDDO0–VDDO3 supply pins, allowing each of its four output pairs to operate at 1.5 V, 1.8 V, 2.5 V, or 3.3 V. This enables direct interfacing with mixed-voltage devices - for example, driving a 1.8 V FPGA fabric clock and a 3.3 V legacy peripheral clock simultaneously without external level shifters.

How is SI5338L-B04838-GMR programmed, and what software is required?

SI5338L-B04838-GMR is programmed via its I²C/SMBus interface using Skyworks' ClockBuilder Pro software - a free, GUI-based tool that generates configuration files, validates settings against hardware constraints, and supports in-system programming. The software auto-generates register maps and supports export to .hex or .csv for integration into production firmware.

What reference inputs does SI5338L-B04838-GMR accept?

SI5338L-B04838-GMR accepts multiple reference types: external crystal (8–30 MHz), single-ended CMOS (5–200 MHz), SSTL/HSTL (5–350 MHz), and differential (5–710 MHz). Input pins IN1/IN2 and IN5/IN6 support AC-coupled differential clocks with internal 10 kΩ termination; IN3/IN4 support DC-coupled single-ended signals with VIH = 0.7×VDD and VIL = 0.3×VDD thresholds.

SI5338L-B04838-GMR Specifications

Product attributes: Attribute value

Manufacturer:: Skyworks Solutions Inc.

Series:: MultiSynth™

Package/Case:: 24-VFQFN Exposed Pad

Packaging:: Tape & Reel (TR)

Product Status:: Active

Programmable:: Not Verified

PLL:: -

Main Purpose:: -

Input:: -

Output:: -

Number of Circuits:: -

Ratio - Input:Output:: -

Differential - Input:Output:: -

Frequency - Max:: -

Voltage - Supply:: -

Operating Temperature:: -

Mounting Type:: Surface Mount

Grade:: -

Qualification:: -

Supplier Device Package:: 24-QFN (4x4)

SI5338L-B04838-GMR FAQ

1.How can I place an order for SI5338L-B04838-GMR through Aetrix?

Please submit a Request for Quotation (RFQ) for SI5338L-B04838-GMR on Aetrix. Our sales agent will provide a competitive quotation and guide you through the order confirmation once you accept the terms.

2.Are the price and stock information for SI5338L-B04838-GMR reliable?

The price and inventory of SI5338L-B04838-GMR are updated periodically and may fluctuate due to market conditions. Stock and pricing data are typically refreshed every 24 hours. Quotation validity for SI5338L-B04838-GMR is usually 5 days.

3.What payment methods are accepted for SI5338L-B04838-GMR?

We accept Wire Transfer, PayPal, Credit Card, Western Union, MoneyGram, and Escrow for SI5338L-B04838-GMR transactions.

Note: Certain payment methods may incur a processing fee.

4.How is shipping managed for SI5338L-B04838-GMR?

SI5338L-B04838-GMR orders can be shipped via leading logistics carriers, including DHL, UPS, FedEx, TNT, or Registered Mail.

Once your SI5338L-B04838-GMR order is processed, you will receive an email with the shipment details and tracking number.

Note: Tracking information may take up to 24 hours to appear. Express delivery typically takes 3–5 business days.

5.How can I obtain technical support or documentation for SI5338L-B04838-GMR?

For technical support, including SI5338L-B04838-GMR datasheets, pinout diagrams, or application guidance, please contact our engineering support team. They can provide detailed documentation and assistance for your SI5338L-B04838-GMR requirements.

6.How does Aetrix verify that SI5338L-B04838-GMR is sourced from the original manufacturer or authorized distributors?

All SI5338L-B04838-GMR products on Aetrix are procured from qualified distributors and authorized channels. Our dedicated quality assurance team conducts strict verification, including traceability checks and, if necessary, third-party testing. This ensures that SI5338L-B04838-GMR meets industry standards.

7.What is the process for return or replacement of SI5338L-B04838-GMR?

All SI5338L-B04838-GMR units undergo pre-shipment inspection (PSI). If there is an issue with SI5338L-B04838-GMR, returns or replacements are accepted under the following conditions:

1.Quantity discrepancies, incorrect items, or visible external defects (such as breakage or corrosion), acknowledged by Aetrix.

2.The issue is reported within 90 days of delivery.

3.The SI5338L-B04838-GMR part is unused and in its original packaging.

Return procedure for SI5338L-B04838-GMR:

1.Submit a request within 90 days.

2.Obtain a Return Material Authorization (RMA) from Aetrix.

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