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Home > Products > Integrated Circuits (ICs) > Clock/Timing > Application Specific Clock/Timing

Skyworks Solutions Inc. SI5338L-B05675-GM

Name: SI5338L-B05675-GM
Brand: Skyworks Solutions Inc.
SKU: SI5338L-B05675-GM
Price: 2.40 USD
Availability: InStock
Rating: 5 (2 reviews)

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Part No.:: SI5338L-B05675-GM

Manufacturer:: Skyworks Solutions Inc.

Category:: Application Specific Clock/Timing

Package:: 24-VFQFN Exposed Pad

Datasheet:: SI5338L-B05675-GM.pdf

Description:: I2C CONTROL, 4-OUTPUT, ANY FREQU

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Product details

Overview

SI5338L-B05675-GM from Skyworks Solutions is an I²C-programmable quad clock generator with four independently configurable differential or single-ended outputs, 0.7 ps RMS typical phase jitter, PCIe Gen 1–4 Common Clock and Gen 3 SRNS compliance, and operation across –40 to +85 °C. It replaces up to four crystal oscillators in Ethernet switch/router, PCIe, and FPGA clocking systems.

For engineers reviewing the SI5338L-B05675-GM datasheet, SI5338L-B05675-GM pinout, SI5338L-B05675-GM application, or SI5338L-B05675-GM equivalent, key selection considerations include its MultiSynth™-based any-frequency synthesis (0.16–710 MHz per output), independent output voltage per driver (1.5/1.8/2.5/3.3 V), spread-spectrum capability (0.5–5.0% down-spread), and 24-pin 4×4 mm QFN package with I²C/SMBus interface.

Technical Context

The SI5338L-B05675-GM implements a two-stage PLL architecture: a high-performance integer-N PLL (Stage 1) locks to one of six input references (crystal, CMOS, SSTL/HSTL, or differential), followed by four independent MultiSynth™ fractional-N synthesis blocks (Stage 2) generating precise output frequencies. Each output supports programmable format (LVPECL/LVDS/HCSL/CMOS/SSTL/HSTL), voltage (1.5–3.3 V), phase offset (±45 ns), and spread-spectrum modulation (33–63 kHz rate, 0.5–5.0% deviation).

It features loss-of-signal and loss-of-lock alarms, glitchless frequency increment/decrement in 1 ppm steps via dedicated pins or I²C, and external feedback mode for zero-delay operation. Core supply operates at 1.8/2.5/3.3 V with 45 mA typical current draw; output buffers are powered separately (VDDOx) to support mixed-voltage system timing.

Key Specifications

Parameter	Value and Actual Design Meaning
Phase Jitter (RMS)	0.7 ps - meets PCIe Gen 4 common clock and OC-12 jitter requirements; enables clean sampling in high-speed SerDes interfaces
Output Frequency Range	0.16–710 MHz - covers Ethernet (125/156.25 MHz), PCIe (100 MHz), Fibre Channel (1.0625 GHz ÷2 = 531.25 MHz), and processor clocks
Input Reference Support	Crystal (8–30 MHz), CMOS (5–200 MHz), SSTL/HSTL (5–350 MHz), differential (5–710 MHz) - enables flexible clock tree design with legacy or new sources
Output Driver Flexibility	Up to 4 differential + 8 single-ended outputs or combinations - allows simultaneous clocking of mixed-IO devices (FPGA, ASIC, PHY, memory) on one chip
Supply Voltages	Core: 1.8/2.5/3.3 V; Output buffers: 1.5/1.8/2.5/3.3 V per channel - eliminates level-shifting ICs in multi-rail systems
Package	24-pin QFN, 4 × 4 mm, 0.5 mm pitch - compact footprint compatible with dense PCB layouts and automated assembly
Operating Temperature	–40 to +85 °C - qualified for industrial and telecom line card environments without derating

Pinout & Package

SI5338L-B05675-GM is housed in a 24-lead, 4 × 4 mm QFN package with exposed thermal pad. Pin assignments are fixed per the Si5338 family and validated for this variant.

Pin/Terminal	Circuit Role	Design Meaning
IN1, IN2, IN5, IN6	Differential Input Pairs	Accept AC-coupled LVPECL/LVDS/CML reference clocks up to 710 MHz; require external 100 Ω termination
IN3, IN4	Single-Ended Inputs	Support CMOS/SSTL/HSTL clocks (5–350 MHz); tolerate 0.7×VDD to 3.73 V logic levels
CLK0A–CLK3B	Differential Output Pairs	Four independent output drivers; each configurable as LVPECL/LVDS/HCSL/CML with separate VDDOx supplies
VDDO0–VDDO3	Output Buffer Supplies	Independent 1.5/1.8/2.5/3.3 V rails per output bank - enables mixed-voltage clock distribution
VDD	Core Supply	1.8/2.5/3.3 V core power; PSRR optimized to suppress supply noise from affecting jitter
SCL, SDA	I²C Interface	SMBus-compatible 100/400 kHz control bus; supports in-system programming and dynamic reconfiguration
INTR	Interrupt Output	Open-drain status signal indicating loss-of-lock or loss-of-signal events; simplifies system monitoring
GND, RSVD_GND	Ground Terminals	Multiple GND pins including reserved ground for noise isolation; thermal pad must be soldered for thermal performance

Key Features

Feature	Design Value
MultiSynth™ Any-Frequency Synthesis	Generates four independent, zero-ppm-accurate output frequencies simultaneously - eliminates need for multiple XO/VCXO components
PCIe Gen 1–4 & SRNS Compliance	Meets total jitter (33.6 ps pk-pk Gen 2), RMS jitter (0.15 ps Gen 3/4), and SSC requirements - certified for use in PCIe root complexes and endpoints
Independent Output Voltage per Driver	Each of four output banks powered by dedicated VDDOx rail (1.5/1.8/2.5/3.3 V) - avoids external level shifters when driving mixed-IO devices
Glitchless Frequency Adjustment	Hardware pin-controlled ±1 ppm step increments with <667 ns update time - enables real-time clock tuning without output interruption
Programmable Spread Spectrum	Configurable down-spread (0.5–5.0%) and modulation rate (33–63 kHz) on any output - reduces EMI peak emissions in FCC/CE-constrained designs
External Feedback Mode	Supports zero-delay clock buffer configuration using external feedback path - maintains deterministic latency for timing-critical applications

Applications

Ethernet Switch/Routing Timing	PCIe Gen 1–4 Clock Distribution
Use Scenario: High-density 1/10 GbE switch fabric requiring synchronous 125 MHz and 156.25 MHz clocks for MAC, PHY, and packet buffer interfaces. IC Role / Device Role / Timing Role: Quad-output clock generator providing four precisely aligned, low-jitter clocks with independent format/voltage control. Use Value: Replaces four discrete oscillators; eliminates inter-clock skew; meets IEEE 802.3 jitter limits (0.7 ps RMS) without external cleanup.	Use Scenario: Server motherboard with CPU, GPU, NVMe, and chipset all requiring compliant 100 MHz PCIe reference clocks. IC Role / Device Role / Timing Role: PCIe Common Clock generator delivering four HCSL 100 MHz outputs meeting Gen 3 SRNS and Gen 4 jitter specs. Use Value: Single-chip solution satisfies PCIe Base Spec 4.0 jitter requirements (0.15 ps RMS) and supports spread-spectrum for EMI reduction.
FPGA & Processor Clocking	Broadcast Video/Audio Timing
Use Scenario: Xilinx Versal or Intel Agilex FPGA board needing multiple clocks: 100 MHz for AXI, 200 MHz for DDR, 300 MHz for logic, and 1.2 GHz for transceivers (÷4). IC Role / Device Role / Timing Role: Programmable frequency translator synthesizing exact integer/fractional multiples from a single 25 MHz crystal. Use Value: Eliminates external PLLs; achieves <10 ps cycle-cycle jitter on 300 MHz output; supports dynamic reconfiguration via I²C during runtime.	Use Scenario: SMPTE ST 2110 IP video router requiring genlock-capable 27 MHz, 74.25 MHz, and 148.5 MHz clocks with sub-20 ps phase adjustment. IC Role / Device Role / Timing Role: Broadcast-grade clock generator with programmable initial phase offset (±45 ns, <20 ps step) and low additive jitter (<0.225 ps RMS in buffer mode). Use Value: Enables frame-accurate synchronization across multiple video processing paths; meets SMPTE RP188 timing stability requirements.

Ethernet Switch/Routing Timing

PCIe Gen 1–4 Clock Distribution

Use Scenario: High-density 1/10 GbE switch fabric requiring synchronous 125 MHz and 156.25 MHz clocks for MAC, PHY, and packet buffer interfaces.

IC Role / Device Role / Timing Role: Quad-output clock generator providing four precisely aligned, low-jitter clocks with independent format/voltage control.

Use Value: Replaces four discrete oscillators; eliminates inter-clock skew; meets IEEE 802.3 jitter limits (0.7 ps RMS) without external cleanup.

Use Scenario: Server motherboard with CPU, GPU, NVMe, and chipset all requiring compliant 100 MHz PCIe reference clocks.

IC Role / Device Role / Timing Role: PCIe Common Clock generator delivering four HCSL 100 MHz outputs meeting Gen 3 SRNS and Gen 4 jitter specs.

Use Value: Single-chip solution satisfies PCIe Base Spec 4.0 jitter requirements (0.15 ps RMS) and supports spread-spectrum for EMI reduction.

FPGA & Processor Clocking

Broadcast Video/Audio Timing

Use Scenario: Xilinx Versal or Intel Agilex FPGA board needing multiple clocks: 100 MHz for AXI, 200 MHz for DDR, 300 MHz for logic, and 1.2 GHz for transceivers (÷4).

IC Role / Device Role / Timing Role: Programmable frequency translator synthesizing exact integer/fractional multiples from a single 25 MHz crystal.

Use Value: Eliminates external PLLs; achieves <10 ps cycle-cycle jitter on 300 MHz output; supports dynamic reconfiguration via I²C during runtime.

Use Scenario: SMPTE ST 2110 IP video router requiring genlock-capable 27 MHz, 74.25 MHz, and 148.5 MHz clocks with sub-20 ps phase adjustment.

IC Role / Device Role / Timing Role: Broadcast-grade clock generator with programmable initial phase offset (±45 ns, <20 ps step) and low additive jitter (<0.225 ps RMS in buffer mode).

Use Value: Enables frame-accurate synchronization across multiple video processing paths; meets SMPTE RP188 timing stability requirements.

Equivalent & Alternatives

The following parts are listed as comparable options for similar quad clock generator applications.

Alternative Part	Technical Difference	Application Difference	Selection Advice
Si5332A-D05675-GM	Higher integration: includes integrated crystal, smaller 3×3 mm package, lower power (32 mA typ), but limited to three outputs and narrower max frequency (550 MHz)	Preferred for space-constrained, crystal-integrated designs where ≤3 outputs suffice and 710 MHz synthesis is not required	Select SI5338L-B05675-GM when four independent high-frequency outputs (up to 710 MHz), external crystal flexibility, or PCIe Gen 4 SRNS compliance are mandatory
ICS8430I-01T	Fixed-frequency quad LVDS generator (no I²C programming); 0.9 ps RMS jitter; 0.1–700 MHz range; 3.3 V only; no spread spectrum or phase adjust	Suitable for cost-sensitive, static clock trees where frequency agility and advanced features are unnecessary	Choose SI5338L-B05675-GM when field-upgradable frequency plans, mixed-voltage outputs, or EMI-reduction spread spectrum are required

Compared with Si5332A-D05675-GM and ICS8430I-01T, the SI5338L-B05675-GM uniquely delivers four fully programmable outputs up to 710 MHz with PCIe Gen 4 SRNS compliance, independent VDDOx supplies, and hardware-based glitchless frequency tuning - making it the only option for complex, high-speed, multi-protocol timing systems requiring long-term design flexibility.

Availability

SI5338L-B05675-GM is available at Aetrix Electronics and suitable for Ethernet switch/router, PCIe Gen 1–4 platform development, and FPGA-based broadcast video equipment requiring stable component supply, full traceability, and lifecycle continuity.

Supply support for SI5338L-B05675-GM includes scheduled delivery planning, volume procurement assistance, BOM continuity management, traceable sourcing, and lifecycle availability coordination for OEM customers, industrial embedded developers, connected-device designers, and electronics production programs.

Manufacturer

Skyworks Solutions is a global leader in analog and mixed-signal semiconductors, specializing in RF, timing, and connectivity solutions for infrastructure, automotive, and mobile markets.

The SI5338L-B05675-GM belongs to Skyworks' Si5338 family of I²C-programmable quad clock generators, engineered for high-speed digital systems requiring ultra-low jitter, multi-protocol compliance (PCIe, Ethernet, Fibre Channel), and flexible clock tree consolidation.

FAQ

What is the maximum output frequency supported by the SI5338L-B05675-GM?

The SI5338L-B05675-GM supports differential output frequencies up to 710 MHz (LVPECL/LVDS/CML), 350 MHz (SSTL/HSTL), 250 MHz (HCSL), and 200 MHz (CMOS). Two outputs may simultaneously operate above 350 MHz-specifically at Fvco/4 and Fvco/6-enabling high-speed SerDes clocking while maintaining jitter integrity in the SI5338L-B05675-GM.

Does the SI5338L-B05675-GM support PCIe Gen 4 timing requirements?

Yes, the SI5338L-B05675-GM meets PCIe Gen 4 Common Clock jitter specifications (0.15–0.45 ps RMS, 10 kHz–50 MHz) and supports Spread Spectrum Clocking (SSC) with user-configurable down-spread (0.5–5.0%) and modulation rate (33–63 kHz), satisfying both electrical and EMI requirements for PCIe Gen 4 root complex and endpoint designs using the SI5338L-B05675-GM.

Can the SI5338L-B05675-GM generate different output voltages on each channel?

Yes, the SI5338L-B05675-GM provides four independent VDDOx supply pins (VDDO0–VDDO3), each configurable for 1.5 V, 1.8 V, 2.5 V, or 3.3 V. This allows simultaneous LVDS (2.5 V), HCSL (1.8 V), and CMOS (3.3 V) outputs without external level shifters-directly supporting heterogeneous device interfaces in the SI5338L-B05675-GM.

How is the SI5338L-B05675-GM programmed and configured?

The SI5338L-B05675-GM is programmed via its I²C/SMBus-compatible interface (SCL/SDA pins) using Skyworks' ClockBuilder Pro software, which generates custom configuration files and supports in-system reprogramming. Hardware pin controls (PINC/FDEC) also enable real-time frequency stepping without host intervention-fully leveraging the SI5338L-B05675-GM's programmability.

What package type and thermal characteristics does the SI5338L-B05675-GM have?

The SI5338L-B05675-GM uses a 24-pin QFN package (4 × 4 mm, 0.5 mm pitch) with exposed thermal pad. Its thermal resistance is θJA = 37 °C/W (still air) and θJC = 10 °C/W, enabling reliable operation at full load across –40 to +85 °C ambient without forced airflow-critical for thermally constrained telecom and industrial applications using the SI5338L-B05675-GM.

SI5338L-B05675-GM Specifications

Product attributes: Attribute value

Manufacturer:: Skyworks Solutions Inc.

Series:: MultiSynth™

Package/Case:: 24-VFQFN Exposed Pad

Packaging:: Tray

Product Status:: Active

Programmable:: Not Verified

PLL:: -

Main Purpose:: -

Input:: -

Output:: -

Number of Circuits:: -

Ratio - Input:Output:: -

Differential - Input:Output:: -

Frequency - Max:: -

Voltage - Supply:: -

Operating Temperature:: -

Mounting Type:: Surface Mount

Grade:: -

Qualification:: -

Supplier Device Package:: 24-QFN (4x4)

SI5338L-B05675-GM FAQ

1.How can I place an order for SI5338L-B05675-GM through Aetrix?

Please submit a Request for Quotation (RFQ) for SI5338L-B05675-GM on Aetrix. Our sales agent will provide a competitive quotation and guide you through the order confirmation once you accept the terms.

2.Are the price and stock information for SI5338L-B05675-GM reliable?

The price and inventory of SI5338L-B05675-GM are updated periodically and may fluctuate due to market conditions. Stock and pricing data are typically refreshed every 24 hours. Quotation validity for SI5338L-B05675-GM is usually 5 days.

3.What payment methods are accepted for SI5338L-B05675-GM?

We accept Wire Transfer, PayPal, Credit Card, Western Union, MoneyGram, and Escrow for SI5338L-B05675-GM transactions.

Note: Certain payment methods may incur a processing fee.

4.How is shipping managed for SI5338L-B05675-GM?

SI5338L-B05675-GM orders can be shipped via leading logistics carriers, including DHL, UPS, FedEx, TNT, or Registered Mail.

Once your SI5338L-B05675-GM order is processed, you will receive an email with the shipment details and tracking number.

Note: Tracking information may take up to 24 hours to appear. Express delivery typically takes 3–5 business days.

5.How can I obtain technical support or documentation for SI5338L-B05675-GM?

For technical support, including SI5338L-B05675-GM datasheets, pinout diagrams, or application guidance, please contact our engineering support team. They can provide detailed documentation and assistance for your SI5338L-B05675-GM requirements.

6.How does Aetrix verify that SI5338L-B05675-GM is sourced from the original manufacturer or authorized distributors?

All SI5338L-B05675-GM products on Aetrix are procured from qualified distributors and authorized channels. Our dedicated quality assurance team conducts strict verification, including traceability checks and, if necessary, third-party testing. This ensures that SI5338L-B05675-GM meets industry standards.

7.What is the process for return or replacement of SI5338L-B05675-GM?

All SI5338L-B05675-GM units undergo pre-shipment inspection (PSI). If there is an issue with SI5338L-B05675-GM, returns or replacements are accepted under the following conditions:

1.Quantity discrepancies, incorrect items, or visible external defects (such as breakage or corrosion), acknowledged by Aetrix.

2.The issue is reported within 90 days of delivery.

3.The SI5338L-B05675-GM part is unused and in its original packaging.

Return procedure for SI5338L-B05675-GM:

1.Submit a request within 90 days.

2.Obtain a Return Material Authorization (RMA) from Aetrix.

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