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Home > Products > Integrated Circuits (ICs) > Clock/Timing > Application Specific Clock/Timing

Skyworks Solutions Inc. SI5338L-B05675-GMR

Name: SI5338L-B05675-GMR
Brand: Skyworks Solutions Inc.
SKU: SI5338L-B05675-GMR
Price: 2.40 USD
Availability: InStock
Rating: 5 (2 reviews)

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Part No.:: SI5338L-B05675-GMR

Manufacturer:: Skyworks Solutions Inc.

Category:: Application Specific Clock/Timing

Package:: 24-VFQFN Exposed Pad

Datasheet:: SI5338L-B05675-GMR.pdf

Description:: I2C CONTROL, 4-OUTPUT, ANY FREQU

Quantity:: RFQ Add To RFQ list

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Product details

Overview

SI5338L-B05675-GMR from Skyworks Solutions is a quad-output, I²C-programmable clock generator implementing MultiSynth™ frequency synthesis with 0 ppm precision per output. It delivers four independent differential or single-ended clocks (LVPECL/LVDS/HCSL/CMOS/SSTL/HSTL) across 0.16–710 MHz, supports PCIe Gen 1–4 common clock and SRNS compliance, and operates from 1.8/2.5/3.3 V core supply in a 4 × 4 mm 24-QFN package for FPGA, processor, and high-speed serial interface timing.

For engineers reviewing the SI5338L-B05675-GMR datasheet, SI5338L-B05675-GMR pinout, SI5338L-B05675-GMR application, or SI5338L-B05675-GMR equivalent, key selection criteria include its 0.7 ps RMS phase jitter (typ), independent per-output voltage control (1.5–3.3 V), glitchless 1 ppm frequency increment/decrement, <20 ps phase step resolution, and PCIe Gen 4-compliant jitter performance at 100 MHz HCSL.

Technical Context

The SI5338L-B05675-GMR integrates a dual-stage PLL architecture: a high-stability reference stage (with crystal or external clock input) feeding a fractional-N VCO, followed by four independent MultiSynth™ synthesis blocks. Each output path includes programmable R-divider, M-divider, and P-divider stages enabling integer or fractional frequency synthesis with sub-ppb resolution.

It supports flexible input references - 8–30 MHz crystal, 5–200 MHz CMOS, 5–350 MHz SSTL/HSTL, or 5–710 MHz differential - and provides loss-of-lock and loss-of-signal alarms, external feedback for zero-delay mode, and independent spread-spectrum control (0.5–5.0% spread, 33–63 kHz modulation) on any output.

Key Specifications

Parameter	Value and Actual Design Meaning
Phase Jitter (RMS)	0.7 ps typical over 12 kHz–20 MHz - meets PCIe Gen 3/4 and GbE jitter requirements for high-reliability serial links.
Output Frequency Range	0.16–710 MHz per channel - covers PCIe 100 MHz, Ethernet 125/156.25 MHz, Fibre Channel 1.0625 GHz (via /2 divider), and broadcast video rates.
Output Formats	LVPECL, LVDS, HCSL, CMOS, SSTL, HSTL - enables direct interface to FPGAs (e.g., Xilinx UltraScale+), CPUs, and SerDes PHYs without level-shifting.
Supply Voltages	Core: 1.8/2.5/3.3 V; Output buffers: independently configurable 1.5/1.8/2.5/3.3 V - simplifies mixed-voltage system clock distribution.
Input Reference Support	Crystal (8–30 MHz), CMOS (5–200 MHz), differential (5–710 MHz) - allows use of low-cost crystals or recovered clocks from upstream PHYs.
Programmability	I²C/SMBus interface + ClockBuilder Pro GUI - enables field reconfiguration of frequencies, formats, and SSC without hardware change.
Operating Temperature	–40 °C to +85 °C - qualified for industrial and telecom line-card environments.

Pinout & Package

SI5338L-B05675-GMR is housed in a 4 × 4 mm, 24-pin QFN package with exposed thermal pad (RoHS-compliant, lead-free). Pin 1 is top-left corner (IN1), with pins numbered counter-clockwise. The package supports standard reflow profiles and requires controlled-impedance PCB routing for differential inputs/outputs.

Pin/Terminal	Circuit Role	Design Meaning
IN1, IN2	Differential input pair #1	Accepts 5–710 MHz AC-coupled differential clock; internal 100 Ω termination enabled via register.
IN3, IN4	Single-ended input pair	Supports 5–200 MHz CMOS-level reference; VIH = 0.7×VDD, VIL = 0.3×VDD.
CLK0A, CLK0B – CLK3A, CLK3B	Differential output pairs (x4)	Each pair configurable as LVPECL/LVDS/HCSL/CML; output voltage set per bank via VDDO0–VDDO3.
VDDO0–VDDO3	Independent output buffer supplies	Enable per-output voltage selection (1.5/1.8/2.5/3.3 V) - critical for interfacing to mixed-voltage SoCs/FPGAs.
SCL, SDA	I²C serial interface	Standard 100/400 kHz operation; supports multi-drop configuration with address pins (not present on this variant).
INTR	Interrupt output	Open-drain status signal indicating loss-of-lock or loss-of-signal; pulled up externally to VDDIO.
VDD	Core supply	Accepts 1.8 V (±5%), 2.5 V (±10%), or 3.3 V (±10%) - PSRR > 60 dB minimizes supply noise coupling into jitter.
GND, RSVD_GND	Ground connections	Multiple dedicated ground pins and thermal pad ensure low-impedance return paths for high-frequency outputs and reduce EMI.

Key Features

Feature	Design Value
MultiSynth™ synthesis per output	Enables true 0 ppm frequency accuracy on all four outputs simultaneously - eliminates need for multiple discrete oscillators.
Independent per-output voltage control	Allows CLK0–CLK3 to drive devices with different I/O standards (e.g., 1.8 V FPGA bank + 3.3 V legacy ASIC) without external level shifters.
Glitchless frequency adjustment	1 ppm step size with pin-controlled or I²C-initiated increment/decrement - enables dynamic clock scaling in real-time systems.
Sub-20 ps phase step resolution	Supports precise skew alignment between outputs (e.g., DDR source-synchronous clocks or PCIe differential pairs).
PCIe Gen 4 Common Clock compliance	0.15–0.45 ps RMS jitter (10 kHz–50 MHz) at 100 MHz HCSL - satisfies PCI-SIG specification for host/controller timing.
Configurable spread spectrum	0.5–5.0% down-spread at 33–63 kHz on any output - reduces EMI peak emissions without affecting system timing margins.

Applications

PCIe Gen 4 Switch Timing	Ethernet Switch Clocking
Use Scenario: Providing synchronized 100 MHz reference clocks to a 32-lane PCIe Gen 4 switch ASIC and attached NVMe SSDs. IC Role / Device Role / Timing Role: Quad-output clock generator delivering four independent, low-jitter 100 MHz HCSL clocks with matched phase alignment. Use Value: Meets PCIe Gen 4 Common Clock jitter spec (≤0.45 ps RMS), eliminates inter-lane skew, and replaces four discrete oscillators to reduce BOM count and board area.	Use Scenario: Generating 125 MHz (1 GbE), 156.25 MHz (10 GbE), and 312.5 MHz (25 GbE) clocks for multi-rate Ethernet switch fabric. IC Role / Device Role / Timing Role: Any-frequency synthesizer producing exact IEEE 802.3-compliant rates from a single 25 MHz crystal reference. Use Value: Achieves 0.7 ps RMS jitter at 125 MHz - exceeds IEEE 802.3bj Annex 83B mask - and supports seamless rate agility without hardware changes.
FPGA-Based Video Processing	Telecom Line Card Synchronization
Use Scenario: Supplying pixel clocks (74.25 MHz), audio clocks (48 kHz), and AXI interconnect clocks (100 MHz) to an Xilinx Zynq Ultrascale+ MPSoC in broadcast video equipment. IC Role / Device Role / Timing Role: Configurable quad clock source with mixed single-ended (CMOS) and differential (LVDS) outputs. Use Value: Independent VDDO per output enables 1.8 V LVDS for FPGA transceivers and 3.3 V CMOS for legacy audio codecs - no external regulators or level shifters required.	Use Scenario: Delivering synchronous 155.52 MHz (OC-3), 622.08 MHz (OC-12), and 2.488 GHz (OC-48) clocks to SONET/SDH framer and mapper ICs in optical line cards. IC Role / Device Role / Timing Role: High-stability frequency translator accepting 19.44 MHz reference and generating OC-n line rates with <10 ps pk-pk period jitter. Use Value: 0.7 ps RMS OC-12 jitter ensures BER <1e−12 in long-haul transmission; external feedback mode enables zero-delay clock forwarding.

PCIe Gen 4 Switch Timing

Ethernet Switch Clocking

Use Scenario: Providing synchronized 100 MHz reference clocks to a 32-lane PCIe Gen 4 switch ASIC and attached NVMe SSDs.

IC Role / Device Role / Timing Role: Quad-output clock generator delivering four independent, low-jitter 100 MHz HCSL clocks with matched phase alignment.

Use Value: Meets PCIe Gen 4 Common Clock jitter spec (≤0.45 ps RMS), eliminates inter-lane skew, and replaces four discrete oscillators to reduce BOM count and board area.

Use Scenario: Generating 125 MHz (1 GbE), 156.25 MHz (10 GbE), and 312.5 MHz (25 GbE) clocks for multi-rate Ethernet switch fabric.

IC Role / Device Role / Timing Role: Any-frequency synthesizer producing exact IEEE 802.3-compliant rates from a single 25 MHz crystal reference.

Use Value: Achieves 0.7 ps RMS jitter at 125 MHz - exceeds IEEE 802.3bj Annex 83B mask - and supports seamless rate agility without hardware changes.

FPGA-Based Video Processing

Telecom Line Card Synchronization

Use Scenario: Supplying pixel clocks (74.25 MHz), audio clocks (48 kHz), and AXI interconnect clocks (100 MHz) to an Xilinx Zynq Ultrascale+ MPSoC in broadcast video equipment.

IC Role / Device Role / Timing Role: Configurable quad clock source with mixed single-ended (CMOS) and differential (LVDS) outputs.

Use Value: Independent VDDO per output enables 1.8 V LVDS for FPGA transceivers and 3.3 V CMOS for legacy audio codecs - no external regulators or level shifters required.

Use Scenario: Delivering synchronous 155.52 MHz (OC-3), 622.08 MHz (OC-12), and 2.488 GHz (OC-48) clocks to SONET/SDH framer and mapper ICs in optical line cards.

IC Role / Device Role / Timing Role: High-stability frequency translator accepting 19.44 MHz reference and generating OC-n line rates with <10 ps pk-pk period jitter.

Use Value: 0.7 ps RMS OC-12 jitter ensures BER <1e−12 in long-haul transmission; external feedback mode enables zero-delay clock forwarding.

Equivalent & Alternatives

The following parts are listed as comparable options for similar quad-output programmable clock generator applications.

Alternative Part	Technical Difference	Application Difference	Selection Advice
Si5332A-D05675-GM	Higher integration: integrated crystal option, lower 0.35 ps RMS jitter, supports up to 10 outputs (configurable), wider frequency range (up to 3.2 GHz).	Targeted at next-gen 5G infrastructure and AI accelerators requiring ultra-low jitter and multi-gigahertz synthesis.	Select Si5332A-D05675-GM when sub-0.4 ps jitter, integrated crystal, or >4 outputs are required; SI5338L-B05675-GMR remains optimal for cost-sensitive PCIe/Ethernet designs with proven qualification.
ICS8430I-01T	Fixed-frequency, non-programmable quad LVDS clock generator; no I²C interface; 1.2 ps RMS jitter; only supports 100/125/156.25 MHz outputs.	Limited to static, pre-defined clock trees - no field reconfiguration or custom frequency support.	Choose ICS8430I-01T only for simple, low-cost applications where all required frequencies are fixed and known at design-in; SI5338L-B05675-GMR offers full flexibility and future-proofing.

Compared with Si5332A-D05675-GM, SI5338L-B05675-GMR trades ultra-low jitter and higher frequency capability for lower cost and mature qualification in PCIe Gen 4 platforms; versus ICS8430I-01T, it adds full programmability and arbitrary frequency synthesis at the cost of higher complexity and BOM count.

Availability

SI5338L-B05675-GMR is available at Aetrix Electronics and suitable for PCIe Gen 4 switch timing, multi-rate Ethernet switching, and FPGA-based broadcast video processing requiring stable component supply, long-term lifecycle support, and traceable sourcing.

Supply support for SI5338L-B05675-GMR includes scheduled delivery planning, volume procurement assistance, BOM continuity management, traceable sourcing, and lifecycle availability coordination for OEM customers, industrial embedded developers, connected-device designers, and electronics production programs.

Manufacturer

Skyworks Solutions is a global leader in analog and mixed-signal semiconductors, specializing in RF, timing, and connectivity solutions for infrastructure, automotive, and mobile markets.

The SI5338 family was designed to replace multiple discrete oscillators in high-performance computing and communications systems, delivering programmable, low-jitter clock synthesis in compact QFN packages for space-constrained PCBs.

FAQ

What is the maximum output frequency supported by SI5338L-B05675-GMR?

The SI5338L-B05675-GMR supports up to 710 MHz on LVPECL/LVDS/CML outputs, 350 MHz on SSTL/HSTL, 250 MHz on HCSL, and 200 MHz on CMOS. Frequencies above 350 MHz are limited to two unique values simultaneously (Fvco/4 and Fvco/6), as defined by the VCO operating range and synthesis architecture.

Does SI5338L-B05675-GMR support PCIe Gen 4 Common Clock compliance?

Yes, SI5338L-B05675-GMR meets PCIe Gen 4 Common Clock jitter specifications: 0.15–0.45 ps RMS (10 kHz–50 MHz) when configured for 100 MHz HCSL output, verified using the Skyworks PCIe Clock Jitter Tool and Intel Clock Jitter Tool v1.6.4 per PCI-SIG Base Spec 4.0 rev 0.5.

Can SI5338L-B05675-GMR generate different output voltages on each channel?

Yes, SI5338L-B05675-GMR provides four independent output supply pins (VDDO0–VDDO3), each configurable for 1.5 V, 1.8 V, 2.5 V, or 3.3 V. This enables simultaneous driving of mixed-voltage devices - e.g., 1.8 V FPGA transceivers and 3.3 V legacy peripherals - without external level shifters.

What input reference options does SI5338L-B05675-GMR support?

SI5338L-B05675-GMR accepts multiple reference sources: 8–30 MHz crystal (differential), 5–200 MHz CMOS (single-ended), 5–350 MHz SSTL/HSTL (single-ended), or 5–710 MHz differential (AC-coupled). Input flexibility allows use of low-cost crystals or recovered clocks from upstream SerDes lanes.

How is SI5338L-B05675-GMR programmed in-system?

SI5338L-B05675-GMR is programmed via its I²C/SMBus-compatible serial interface (SCL/SDA pins) using Skyworks' ClockBuilder Pro software. Configuration files can be generated offline and loaded during manufacturing or updated dynamically in the field without hardware modification.

SI5338L-B05675-GMR Specifications

Product attributes: Attribute value

Manufacturer:: Skyworks Solutions Inc.

Series:: MultiSynth™

Package/Case:: 24-VFQFN Exposed Pad

Packaging:: Tape & Reel (TR)

Product Status:: Active

Programmable:: Not Verified

PLL:: -

Main Purpose:: -

Input:: -

Output:: -

Number of Circuits:: -

Ratio - Input:Output:: -

Differential - Input:Output:: -

Frequency - Max:: -

Voltage - Supply:: -

Operating Temperature:: -

Mounting Type:: Surface Mount

Grade:: -

Qualification:: -

Supplier Device Package:: 24-QFN (4x4)

SI5338L-B05675-GMR FAQ

1.How can I place an order for SI5338L-B05675-GMR through Aetrix?

Please submit a Request for Quotation (RFQ) for SI5338L-B05675-GMR on Aetrix. Our sales agent will provide a competitive quotation and guide you through the order confirmation once you accept the terms.

2.Are the price and stock information for SI5338L-B05675-GMR reliable?

The price and inventory of SI5338L-B05675-GMR are updated periodically and may fluctuate due to market conditions. Stock and pricing data are typically refreshed every 24 hours. Quotation validity for SI5338L-B05675-GMR is usually 5 days.

3.What payment methods are accepted for SI5338L-B05675-GMR?

We accept Wire Transfer, PayPal, Credit Card, Western Union, MoneyGram, and Escrow for SI5338L-B05675-GMR transactions.

Note: Certain payment methods may incur a processing fee.

4.How is shipping managed for SI5338L-B05675-GMR?

SI5338L-B05675-GMR orders can be shipped via leading logistics carriers, including DHL, UPS, FedEx, TNT, or Registered Mail.

Once your SI5338L-B05675-GMR order is processed, you will receive an email with the shipment details and tracking number.

Note: Tracking information may take up to 24 hours to appear. Express delivery typically takes 3–5 business days.

5.How can I obtain technical support or documentation for SI5338L-B05675-GMR?

For technical support, including SI5338L-B05675-GMR datasheets, pinout diagrams, or application guidance, please contact our engineering support team. They can provide detailed documentation and assistance for your SI5338L-B05675-GMR requirements.

6.How does Aetrix verify that SI5338L-B05675-GMR is sourced from the original manufacturer or authorized distributors?

All SI5338L-B05675-GMR products on Aetrix are procured from qualified distributors and authorized channels. Our dedicated quality assurance team conducts strict verification, including traceability checks and, if necessary, third-party testing. This ensures that SI5338L-B05675-GMR meets industry standards.

7.What is the process for return or replacement of SI5338L-B05675-GMR?

All SI5338L-B05675-GMR units undergo pre-shipment inspection (PSI). If there is an issue with SI5338L-B05675-GMR, returns or replacements are accepted under the following conditions:

1.Quantity discrepancies, incorrect items, or visible external defects (such as breakage or corrosion), acknowledged by Aetrix.

2.The issue is reported within 90 days of delivery.

3.The SI5338L-B05675-GMR part is unused and in its original packaging.

Return procedure for SI5338L-B05675-GMR:

1.Submit a request within 90 days.

2.Obtain a Return Material Authorization (RMA) from Aetrix.

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