Skyworks Solutions Inc. SI5338L-B05700-GM

Overview

SI5338L-B05700-GM from Skyworks Solutions is an I²C-programmable quad clock generator with four independently configurable differential outputs, 0.7 ps RMS typical phase jitter, PCIe Gen 1–4 Common Clock and Gen 3 SRNS compliance, and support for LVPECL/LVDS/HCSL/CMOS/SSTL/HSTL output formats across 0.16–710 MHz. It replaces up to four crystal oscillators in high-speed serial interface timing applications such as PCIe root complexes and Ethernet switch fabric.

For engineers reviewing the SI5338L-B05700-GM datasheet, SI5338L-B05700-GM pinout, SI5338L-B05700-GM application, or SI5338L-B05700-GM equivalent, key selection criteria include its MultiSynth™-based any-frequency synthesis, independent per-output voltage (1.5/1.8/2.5/3.3 V), ±20 ps phase step resolution, and 24-QFN package with I²C/SMBus programming interface.

Technical Context

The SI5338L-B05700-GM implements a two-stage PLL architecture: a high-stability integer-N PLL (Stage 1) locks to one of six input references (crystal, CMOS, SSTL/HSTL, or differential), followed by four independent MultiSynth™ fractional-N synthesizers (Stage 2) generating each output. Each MultiSynth supports integer or fractional mode, enabling true zero-ppm frequency accuracy and glitchless 1 ppm frequency increment/decrement via dedicated pins or I²C.

Its output stage provides full format and voltage configurability per driver - including LVPECL common-mode at VDDO–1.45 V, LVDS at 1.125–1.275 V (2.5/3.3 V) or 0.8–0.95 V (1.8 V), and HCSL at 0.35–0.40 V - with programmable initial phase offset (±45 ns), <100 ps output-to-output skew, and spread-spectrum capability (0.5–5.0% down-spread, 33–63 kHz modulation).

Key Specifications

Pinout & Package

SI5338L-B05700-GM is housed in a 24-lead, 4 mm × 4 mm QFN package with exposed thermal pad. Pin assignments follow the standard Si5338 top-view layout: IN1/IN2 (differential ref 1), IN3/IN4 (single-ended ref 2), IN5/IN6 (differential ref 3), CLK0A/CLK0B through CLK3A/CLK3B (four differential output pairs), VDD (core supply), VDDO0–VDDO3 (independent output buffer supplies), SCL/SDA (I²C interface), INTR (interrupt output), and RSVD_GND (reserved ground).

Key Features

Applications

Equivalent & Alternatives

The following parts are listed as comparable options for similar quad clock generator applications.

Compared with Si5338A-B-GM and ICS8430I-01LG, the SI5338L-B05700-GM delivers guaranteed PCIe Gen 3 SRNS jitter performance and factory-tuned settings for immediate deployment in high-speed serial timing, while retaining full field programmability via I²C.

Availability

SI5338L-B05700-GM is available at Aetrix Electronics and suitable for PCIe root complex timing, Ethernet switch fabric clocking, broadcast video synchronization, and FPGA/ASIC clock domain crossing requiring stable component supply, long-term lifecycle assurance, and traceable sourcing.

Supply support for SI5338L-B05700-GM includes scheduled delivery planning, volume procurement assistance, BOM continuity management, traceable sourcing, and lifecycle availability coordination for OEM customers, industrial embedded developers, connected-device designers, and electronics production programs.

Manufacturer

Skyworks Solutions is a global leader in analog and mixed-signal semiconductors, specializing in RF, timing, and connectivity solutions for infrastructure, automotive, and mobile markets.

The Si5338 family was designed specifically for high-performance, multi-protocol clock generation in data center, telecom, and broadcast systems - emphasizing ultra-low jitter, flexible output configuration, and seamless integration with PCIe, Ethernet, and video standards.

FAQ

What is the default startup configuration of the SI5338L-B05700-GM?

The SI5338L-B05700-GM ships with factory-programmed OTP memory containing PCIe Gen 3-compliant output frequencies (100 MHz, 125 MHz, 156.25 MHz, and 312.5 MHz), LVDS output format, 2.5 V VDDO rails, and SRNS-optimized PLL bandwidth. This enables immediate operation without I²C programming, though all parameters remain fully reconfigurable in-system.

Does the SI5338L-B05700-GM support spread spectrum on all four outputs simultaneously?

Yes, the SI5338L-B05700-GM supports independent spread-spectrum modulation on any or all four outputs, with user-selectable spread (0.5–5.0%), modulation rate (33–63 kHz), and direction (down-spread only). Each output's SSC engine operates autonomously, allowing mixed configurations - e.g., SSC enabled on CLK0/CLK1 for EMI reduction while CLK2/CLK3 run clean for jitter-sensitive SerDes.

Can the SI5338L-B05700-GM generate 100 MHz and 250 MHz simultaneously on differential outputs?

Yes, the SI5338L-B05700-GM can generate 100 MHz and 250 MHz simultaneously on separate differential output pairs (e.g., CLK0A/B and CLK1A/B). Both frequencies fall within the supported LVDS/HCSL ranges (0.16–350 MHz for HCSL; 0.16–350 MHz for LVDS), and the MultiSynth™ architecture ensures zero-ppm accuracy and <100 ps inter-output skew between them.

What is the minimum input reference frequency supported in PLL bypass (buffer) mode?

In PLL bypass mode, the SI5338L-B05700-GM supports a minimum input reference frequency of 5 MHz on all input types (differential, CMOS, SSTL/HSTL). While operation down to 1 MHz is possible in buffer mode, loss-of-signal detection is disabled below 5 MHz - a design consideration confirmed in Table 6 Note 3 of the official datasheet.

How does the SI5338L-B05700-GM handle power supply sequencing?

The SI5338L-B05700-GM requires VDD (core) to be stable before VDDOx (output buffers) to ensure proper initialization. The device incorporates internal power-on reset circuitry that holds outputs in tri-state until both VDD and all active VDDOx rails reach valid thresholds. Sequencing is verified per Skyworks Application Note AN360 and reflected in the recommended PCB layout guidelines on page 40 of the datasheet.