Skyworks Solutions Inc. SI5338L-B05700-GMR

Overview

SI5338L-B05700-GMR from Skyworks Solutions is an I²C-programmable quad clock generator with four independently configurable differential or single-ended outputs, 0.7 ps RMS typical phase jitter, PCIe Gen 1–4 Common Clock and Gen 3 SRNS compliance, and operation across –40 to +85 °C. It replaces up to four crystal oscillators in high-speed serial interface timing applications including PCIe, Ethernet, and FPGA clocking.

For engineers reviewing the SI5338L-B05700-GMR datasheet, SI5338L-B05700-GMR pinout, SI5338L-B05700-GMR application, or SI5338L-B05700-GMR equivalent, key selection considerations include its MultiSynth™ fractional-N synthesis architecture, independent output voltage per driver (1.5/1.8/2.5/3.3 V), 0 ppm frequency accuracy, and support for LVPECL/LVDS/HCSL/CMOS/SSTL/HSTL formats up to 710 MHz.

Technical Context

The SI5338L-B05700-GMR implements a two-stage PLL architecture: a high-stability reference stage followed by four independent MultiSynth™ fractional-N synthesis blocks, each feeding a configurable output driver. Its input flexibility supports external crystals (8–30 MHz), CMOS (5–200 MHz), SSTL/HSTL (5–350 MHz), and differential inputs (5–710 MHz).

Each output supports independent frequency, format, voltage, phase offset (±45 ns, <20 ps step), and spread-spectrum modulation (0.5–5.0% spread, 33–63 kHz rate). The device operates from a single 1.8/2.5/3.3 V core supply and delivers low power consumption (45 mA typ at 100 MHz on all outputs).

Key Specifications

Pinout & Package

The SI5338L-B05700-GMR is housed in a 24-lead, 4 × 4 mm QFN package with exposed thermal pad. Pin assignments are fixed per Skyworks' Si5338 family specification.

Key Features

Applications

Equivalent & Alternatives

The following parts are listed as comparable options for similar quad clock generator applications.

Compared with Si5332A-D05700-GM and ICS853S01AG-01, the SI5338L-B05700-GMR uniquely balances field-programmability, PCIe Gen 4 compliance, and mixed-signal output flexibility in a proven 4 × 4 mm QFN-making it optimal for mid-to-high volume industrial and networking platforms requiring post-silicon timing optimization.

Availability

SI5338L-B05700-GMR is available at Aetrix Electronics and suitable for PCIe switch timing, 10GbE PHY clocking, FPGA transceiver synchronization, and broadcast video frame sync applications requiring stable component supply and long-term lifecycle support.

Supply support for SI5338L-B05700-GMR includes scheduled delivery planning, volume procurement assistance, BOM continuity management, traceable sourcing, and lifecycle availability coordination for OEM customers, industrial embedded developers, connected-device designers, and electronics production programs.

Manufacturer

Skyworks Solutions is a global leader in analog and mixed-signal semiconductors, specializing in RF, timing, and connectivity solutions for infrastructure, automotive, and mobile markets.

The Si5338 product line was designed to replace multiple discrete oscillators and buffers in high-speed digital systems, delivering programmable, low-jitter clock synthesis for PCIe, Ethernet, and SerDes-based architectures.

FAQ

What is the maximum differential input frequency supported by the SI5338L-B05700-GMR?

The SI5338L-B05700-GMR supports differential input frequencies up to 710 MHz on pins IN1/IN2 and IN5/IN6. This enables direct use of recovered SerDes clocks or high-frequency reference sources without external division. Operation above 350 MHz requires AC coupling and proper termination with a 100 Ω resistor across the differential pair, as specified in Skyworks Application Note AN562.

Does the SI5338L-B05700-GMR support PCIe Gen 4 Common Clock compliance?

Yes, the SI5338L-B05700-GMR meets PCIe Gen 4 Common Clock total jitter specification of ≤33.6 ps pk-pk (10 kHz–1.5 MHz band) and RMS jitter ≤0.45 ps (1.5 MHz–50 MHz band) when configured per Skyworks' recommended settings-including 100 MHz HCSL outputs, PLL bandwidth of 2–4 MHz, and CDR = 10 MHz. Validation data is published in Table 12 of the Rev. 1.6 datasheet.

Can the SI5338L-B05700-GMR generate four different output frequencies simultaneously?

Yes, the SI5338L-B05700-GMR uses four independent MultiSynth™ synthesis blocks to generate four distinct output frequencies simultaneously - for example, 100 MHz (PCIe), 156.25 MHz (10GbE), 250 MHz (FPGA logic), and 500 MHz (SerDes TX) - all with 0 ppm precision and independent format/voltage configuration. Each output's frequency is set via dedicated M/N/R divider registers.

What output voltage levels does the SI5338L-B05700-GMR support per driver?

The SI5338L-B05700-GMR supports independent output supply voltages of 1.5 V, 1.8 V, 2.5 V, or 3.3 V per VDDOx pin (VDDO0–VDDO3). This allows mixed-voltage interfacing - e.g., driving 1.8 V LVDS FPGA inputs and 3.3 V CMOS microcontroller clocks from the same device - without level shifters or external regulators.

Is ClockBuilder Pro software required to configure the SI5338L-B05700-GMR?

No, ClockBuilder Pro is optional but strongly recommended for SI5338L-B05700-GMR configuration. The device can be programmed directly via I²C using register writes per the Si5338 Register Map (Rev. 1.6, Section 6), but ClockBuilder Pro automates constraint checking, jitter optimization, and configuration file generation - significantly reducing bring-up time and avoiding invalid state combinations that could cause lock failure or excessive jitter.