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Home > Products > Integrated Circuits (ICs) > Clock/Timing > Application Specific Clock/Timing

Skyworks Solutions Inc. SI5338L-B05814-GM

Name: SI5338L-B05814-GM
Brand: Skyworks Solutions Inc.
SKU: SI5338L-B05814-GM
Price: 2.40 USD
Availability: InStock
Rating: 5 (2 reviews)

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Part No.:: SI5338L-B05814-GM

Manufacturer:: Skyworks Solutions Inc.

Category:: Application Specific Clock/Timing

Package:: 24-VFQFN Exposed Pad

Datasheet:: SI5338L-B05814-GM.pdf

Description:: I2C CONTROL, 4-OUTPUT, ANY FREQU

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Product details

Overview

SI5338L-B05814-GM from Skyworks Solutions is an I²C-programmable quad clock generator with four independent differential output drivers, 0.7 ps RMS typical phase jitter, PCIe Gen 1–4 Common Clock and Gen 3 SRNS compliance, and support for LVPECL/LVDS/HCSL/CMOS/SSTL/HSTL output formats across 0.16–710 MHz. It replaces up to four crystal oscillators in high-speed serial interface timing applications such as PCIe root complexes and FPGA clock trees.

For engineers reviewing the SI5338L-B05814-GM datasheet, SI5338L-B05814-GM pinout, SI5338L-B05814-GM application, or SI5338L-B05814-GM equivalent, key selection criteria include its MultiSynth™ fractional-N synthesis architecture, per-output voltage control (1.5/1.8/2.5/3.3 V), independent phase/frequency adjustment (±45 ns / 1 ppm steps), and 24-pin 4×4 mm QFN package with integrated loss-of-lock and loss-of-signal monitoring.

Technical Context

The SI5338L-B05814-GM implements a two-stage PLL architecture: a high-stability reference stage (input range 5–710 MHz) feeding a programmable VCO, followed by four independent MultiSynth™ fractional-N dividers per output. Each output path includes configurable output drivers, selectable termination, and per-channel supply voltage control (VDDO0–VDDO3).

It supports both free-running synthesis and external feedback (zero-delay mode), with real-time frequency increment/decrement via dedicated pins or I²C, and <20 ps step phase adjustment. The device operates across –40 to +85 °C with core supply options of 1.8 V, 2.5 V, or 3.3 V and delivers 45 mA typical core current at 100 MHz on all outputs.

Key Specifications

Parameter	Value and Actual Design Meaning
Phase Jitter (RMS)	0.7 ps typical (12 kHz–20 MHz); meets PCIe Gen 3 SRNS and Gen 4 common clock jitter requirements.
Output Frequency Range	0.16–710 MHz per channel; supports LVPECL/LVDS (≤710 MHz), HCSL (≤250 MHz), CMOS (≤200 MHz), SSTL/HSTL (≤350 MHz).
Input Reference Support	Crystal (8–30 MHz), CMOS (5–200 MHz), SSTL/HSTL (5–350 MHz), differential (5–710 MHz).
Supply Voltages	Core: 1.8/2.5/3.3 V ±10%; Output buffers: independently configurable 1.5/1.8/2.5/3.3 V per driver.
Package & Pins	24-pin QFN, 4 × 4 mm body, 0.5 mm pitch; 4 differential clock outputs (CLK0A/B–CLK3A/B), 6 input clocks (IN1–IN6), I²C (SCL/SDA), INTR, OEB/PINC/FINC.
Temperature Range	–40 °C to +85 °C ambient; qualified for industrial and telecom line card deployment.
PCIe Compliance	Gen 1/2/3/4 Common Clock; Gen 3 Separate Reference No Spread (SRNS); validated per Intel Clock Jitter Tool v1.6.4.

Pinout & Package

SI5338L-B05814-GM is housed in a thermally enhanced 24-lead QFN package (4 mm × 4 mm, 0.5 mm pitch) with exposed thermal pad. Pin 1 is top-left corner (IN1), pin 24 is bottom-right (GND). Package conforms to JEDEC MO-220, RoHS-compliant, MSL3.

Pin/Terminal	Circuit Role	Design Meaning
IN1, IN2, IN5, IN6	Differential input pairs	Accept AC-coupled LVPECL/LVDS/CML references up to 710 MHz; require external 100 Ω termination.
IN3, IN4	Single-ended inputs	Support CMOS/SSTL/HSTL references (5–350 MHz); VIH = 0.7×VDD, VIL = 0.3×VDD.
CLK0A–CLK3B	Differential clock outputs	Four independent output pairs; each configurable for LVPECL/LVDS/HCSL/CML with per-driver VDDO supply.
VDDO0–VDDO3	Output buffer supplies	Independent 1.5/1.8/2.5/3.3 V supplies per output pair; enable mixed-voltage system interfacing.
SCL, SDA	I²C interface	SMBus-compatible 100/400 kHz operation; used for configuration, status readback, and dynamic reprogramming.
INTR	Interrupt output	Open-drain active-low signal indicating loss-of-lock, loss-of-signal, or register write completion.
OEB, PINC, FINC	Control inputs	Hardware-controlled output enable, phase increment, and frequency increment; enable glitchless real-time tuning.

Key Features

Feature	Design Value
MultiSynth™ synthesis	Four independent fractional-N synthesizers enabling true zero-ppm accuracy on all outputs simultaneously.
Per-output voltage control	Each of four output drivers powered by separate VDDOx rails (1.5/1.8/2.5/3.3 V), eliminating level-shifting ICs in multi-voltage systems.
Glitchless frequency tuning	Hardware pin-controlled frequency increment/decrement in 1 ppm steps without output interruption or phase discontinuity.
Programmable phase offset	±45 ns fine phase adjustment per output with <20 ps resolution, enabling precise skew management in parallel data paths.
Spread spectrum support	Configurable SSC on any output: 0.5–5.0% spread, 33–63 kHz modulation rate, 5–350 MHz frequency range.
Status monitoring	Dedicated INTR pin reports loss-of-lock and loss-of-signal events with sub-10 ms detection latency for system fault recovery.

Applications

PCIe Gen 4 Root Complex	Ethernet Switch Timing
Use Scenario: Providing synchronized 100 MHz reference clocks to multiple PCIe Gen 4 endpoints and upstream ports in a server motherboard. IC Role / Device Role / Timing Role: Quad-output clock generator delivering four independent, low-jitter PCIe-compliant clocks with matched skew and spread-spectrum capability. Use Value: Eliminates four discrete oscillators while meeting PCIe Gen 4 common clock TJ < 33.6 ps pk-pk and RMS jitter < 0.45 ps.	Use Scenario: Generating 125 MHz, 156.25 MHz, and 312.5 MHz clocks for 1/10 GbE PHYs, MACs, and packet buffers in a Layer-3 switch ASIC. IC Role / Device Role / Timing Role: Any-frequency synthesizer producing exact Ethernet standard frequencies with independent format and voltage per port. Use Value: Enables single-chip timing for mixed-rate interfaces (1G/10G/25G) with <0.7 ps RMS jitter, reducing board area and BOM count.
FPGA-Based Video Processing	Telecom Line Card Sync
Use Scenario: Supplying pixel clocks (74.25 MHz, 148.5 MHz), DDR memory clocks (400–800 MHz), and transceiver reference clocks (3.125 GHz via divider) to a broadcast video processing FPGA. IC Role / Device Role / Timing Role: Configurable quad clock source supporting LVDS, HCSL, and CMOS outputs with per-output voltage and phase alignment. Use Value: Achieves sub-100 ps output-to-output skew and <30 ps period jitter, critical for SMPTE UHD-SDI timing compliance.	Use Scenario: Delivering stratum-3 compliant 2.048 MHz, 19.44 MHz, and 155.52 MHz clocks to T1/E1 framers, SONET/SDH PHYs, and packet timing engines in a carrier-grade line card. IC Role / Device Role / Timing Role: High-stability clock generator with crystal input support and OC-12–compliant jitter (<1 ps RMS). Use Value: Meets Telcordia GR-1244-CORE for wander and jitter, enabling single-device timing for legacy and packet-sync hybrid architectures.

PCIe Gen 4 Root Complex

Ethernet Switch Timing

Use Scenario: Providing synchronized 100 MHz reference clocks to multiple PCIe Gen 4 endpoints and upstream ports in a server motherboard.

IC Role / Device Role / Timing Role: Quad-output clock generator delivering four independent, low-jitter PCIe-compliant clocks with matched skew and spread-spectrum capability.

Use Value: Eliminates four discrete oscillators while meeting PCIe Gen 4 common clock TJ < 33.6 ps pk-pk and RMS jitter < 0.45 ps.

Use Scenario: Generating 125 MHz, 156.25 MHz, and 312.5 MHz clocks for 1/10 GbE PHYs, MACs, and packet buffers in a Layer-3 switch ASIC.

IC Role / Device Role / Timing Role: Any-frequency synthesizer producing exact Ethernet standard frequencies with independent format and voltage per port.

Use Value: Enables single-chip timing for mixed-rate interfaces (1G/10G/25G) with <0.7 ps RMS jitter, reducing board area and BOM count.

FPGA-Based Video Processing

Telecom Line Card Sync

Use Scenario: Supplying pixel clocks (74.25 MHz, 148.5 MHz), DDR memory clocks (400–800 MHz), and transceiver reference clocks (3.125 GHz via divider) to a broadcast video processing FPGA.

IC Role / Device Role / Timing Role: Configurable quad clock source supporting LVDS, HCSL, and CMOS outputs with per-output voltage and phase alignment.

Use Value: Achieves sub-100 ps output-to-output skew and <30 ps period jitter, critical for SMPTE UHD-SDI timing compliance.

Use Scenario: Delivering stratum-3 compliant 2.048 MHz, 19.44 MHz, and 155.52 MHz clocks to T1/E1 framers, SONET/SDH PHYs, and packet timing engines in a carrier-grade line card.

IC Role / Device Role / Timing Role: High-stability clock generator with crystal input support and OC-12–compliant jitter (<1 ps RMS).

Use Value: Meets Telcordia GR-1244-CORE for wander and jitter, enabling single-device timing for legacy and packet-sync hybrid architectures.

Equivalent & Alternatives

The following parts are listed as comparable options for similar quad-output clock generator applications.

Alternative Part	Technical Difference	Application Difference	Selection Advice
Si5332A-D05814-GM	Higher integration: 8 outputs, dual-loop architecture, lower jitter (0.35 ps RMS), supports JESD204B deterministic latency.	Targeted at JESD204B ADC/DAC synchronization and 5G wireless infrastructure requiring sub-100 fs jitter.	Select when >4 outputs, tighter jitter, or deterministic delay control are required; higher cost and larger 32-QFN package.
ICS843002AGI-01LFT	Fixed-frequency quad LVDS generator (no I²C programming); 1.2 ps RMS jitter; 3.3 V only; no spread spectrum or phase adjustment.	Suitable for cost-sensitive, static-clock applications like legacy storage controllers where frequency flexibility is unnecessary.	Select only for fixed-frequency, non-reprogrammable use cases; lacks Si5338L-B05814-GM's any-frequency synthesis and hardware tuning features.

Compared with Si5332A-D05814-GM and ICS843002AGI-01LFT, the SI5338L-B05814-GM uniquely balances field-programmability, PCIe Gen 4 compliance, and per-output voltage/phase control in a compact 24-QFN footprint-making it optimal for FPGA-based systems requiring post-silicon clock tuning and mixed-voltage interface support.

Availability

SI5338L-B05814-GM is available at Aetrix Electronics and suitable for PCIe Gen 4 root complexes, Ethernet switch timing, and FPGA-based video processing requiring stable component supply, long-term lifecycle support, and traceable sourcing.

Supply support for SI5338L-B05814-GM includes scheduled delivery planning, volume procurement assistance, BOM continuity management, traceable sourcing, and lifecycle availability coordination for OEM customers, industrial embedded developers, connected-device designers, and electronics production programs.

Manufacturer

Skyworks Solutions is a global leader in analog and mixed-signal semiconductors, specializing in RF, timing, and connectivity solutions for infrastructure, automotive, and mobile markets.

The SI5338L-B05814-GM belongs to Skyworks' Si5338 family of programmable clock generators, designed specifically for high-speed serial interface timing-including PCIe, Ethernet, Fibre Channel, and broadcast video-where low jitter, multi-format outputs, and field reconfigurability are essential.

FAQ

What is the primary function of the SI5338L-B05814-GM in a PCIe Gen 4 system?

The SI5338L-B05814-GM serves as a quad-output common clock generator, delivering four synchronized, low-jitter 100 MHz reference clocks to PCIe Gen 4 endpoints and root ports. It meets PCIe Gen 4 common clock total jitter <33.6 ps pk-pk and RMS jitter <0.45 ps, and supports spread-spectrum modulation to reduce EMI. Its hardware frequency increment pins allow runtime tuning without disrupting link training.

Does the SI5338L-B05814-GM support crystal input, and what frequency range is validated?

Yes, the SI5338L-B05814-GM supports fundamental-mode crystals from 8 MHz to 30 MHz. Datasheet Tables 8–11 validate operation across four bands: 8–11 MHz, 11–19 MHz, 19–26 MHz, and 26–30 MHz, with on-chip load capacitance support of 11–13 pF and recommended external loading of 17–19 pF. Crystal drive level is limited to 100 µW maximum.

How does the SI5338L-B05814-GM achieve 0 ppm frequency accuracy across all outputs?

The SI5338L-B05814-GM achieves true zero-ppm accuracy using Skyworks' patented MultiSynth™ fractional-N synthesis architecture. Each output derives from an independent divider chain fed by a shared high-stability VCO, eliminating integer boundary spurs and enabling exact frequency synthesis (e.g., 125.000000 MHz) without rounding error-verified across all four outputs simultaneously in integer or fractional mode.

Can the SI5338L-B05814-GM generate different output formats on each channel, and what are the supported standards?

Yes, each of the four output pairs (CLK0–CLK3) can be independently configured for LVPECL, LVDS, HCSL, CML, CMOS, SSTL, or HSTL. Supported standards include PCIe Gen 1–4 (HCSL), Gigabit Ethernet (LVDS), Fibre Channel (LVPECL), and DDR memory interfaces (SSTL/HSTL), with frequency ranges from 0.16 MHz to 710 MHz depending on format.

What debug and configuration tools are officially supported for the SI5338L-B05814-GM?

Skyworks provides ClockBuilder Pro software for GUI-based configuration, register mapping, and .csv file generation. The PCIe Clock Jitter Tool validates jitter compliance against Intel specifications. Hardware evaluation is supported via the Si5338-EVB evaluation board, which includes USB-to-I²C interface, SMA clock inputs/outputs, and jumper-selectable power domains for VDD and VDDOx rails.

SI5338L-B05814-GM Specifications

Product attributes: Attribute value

Manufacturer:: Skyworks Solutions Inc.

Series:: MultiSynth™

Package/Case:: 24-VFQFN Exposed Pad

Packaging:: Tray

Product Status:: Active

Programmable:: Not Verified

PLL:: -

Main Purpose:: -

Input:: -

Output:: -

Number of Circuits:: -

Ratio - Input:Output:: -

Differential - Input:Output:: -

Frequency - Max:: -

Voltage - Supply:: -

Operating Temperature:: -

Mounting Type:: Surface Mount

Grade:: -

Qualification:: -

Supplier Device Package:: 24-QFN (4x4)

SI5338L-B05814-GM FAQ

1.How can I place an order for SI5338L-B05814-GM through Aetrix?

Please submit a Request for Quotation (RFQ) for SI5338L-B05814-GM on Aetrix. Our sales agent will provide a competitive quotation and guide you through the order confirmation once you accept the terms.

2.Are the price and stock information for SI5338L-B05814-GM reliable?

The price and inventory of SI5338L-B05814-GM are updated periodically and may fluctuate due to market conditions. Stock and pricing data are typically refreshed every 24 hours. Quotation validity for SI5338L-B05814-GM is usually 5 days.

3.What payment methods are accepted for SI5338L-B05814-GM?

We accept Wire Transfer, PayPal, Credit Card, Western Union, MoneyGram, and Escrow for SI5338L-B05814-GM transactions.

Note: Certain payment methods may incur a processing fee.

4.How is shipping managed for SI5338L-B05814-GM?

SI5338L-B05814-GM orders can be shipped via leading logistics carriers, including DHL, UPS, FedEx, TNT, or Registered Mail.

Once your SI5338L-B05814-GM order is processed, you will receive an email with the shipment details and tracking number.

Note: Tracking information may take up to 24 hours to appear. Express delivery typically takes 3–5 business days.

5.How can I obtain technical support or documentation for SI5338L-B05814-GM?

For technical support, including SI5338L-B05814-GM datasheets, pinout diagrams, or application guidance, please contact our engineering support team. They can provide detailed documentation and assistance for your SI5338L-B05814-GM requirements.

6.How does Aetrix verify that SI5338L-B05814-GM is sourced from the original manufacturer or authorized distributors?

All SI5338L-B05814-GM products on Aetrix are procured from qualified distributors and authorized channels. Our dedicated quality assurance team conducts strict verification, including traceability checks and, if necessary, third-party testing. This ensures that SI5338L-B05814-GM meets industry standards.

7.What is the process for return or replacement of SI5338L-B05814-GM?

All SI5338L-B05814-GM units undergo pre-shipment inspection (PSI). If there is an issue with SI5338L-B05814-GM, returns or replacements are accepted under the following conditions:

1.Quantity discrepancies, incorrect items, or visible external defects (such as breakage or corrosion), acknowledged by Aetrix.

2.The issue is reported within 90 days of delivery.

3.The SI5338L-B05814-GM part is unused and in its original packaging.

Return procedure for SI5338L-B05814-GM:

1.Submit a request within 90 days.

2.Obtain a Return Material Authorization (RMA) from Aetrix.

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