Skyworks Solutions Inc. SI5338L-B05947-GM
- Part No.:
- SI5338L-B05947-GM
- Manufacturer:
- Skyworks Solutions Inc.
- Category:
- Application Specific Clock/Timing
- Package:
- 24-VFQFN Exposed Pad
- Datasheet:
-
SI5338L-B05947-GM.pdf
- Description:
- I2C CONTROL, 4-OUTPUT, ANY FREQU
- Quantity:
- Payment:

- Shipping:

Inventory:3,625
Please send an inquiry. Send us your inquiry, and we will respond immediately.
Product details
Overview
SI5338L-B05947-GM from Skyworks Solutions is an I²C-programmable quad clock generator with four independently configurable differential or single-ended outputs, 0.7 ps RMS typical phase jitter, PCIe Gen 1–4 Common Clock and Gen 3 SRNS compliance, and operation across –40 to +85 °C. It replaces up to four crystal oscillators in Ethernet switch/router, processor/FPGA clocking, and broadcast video timing systems.
For engineers reviewing the SI5338L-B05947-GM datasheet, SI5338L-B05947-GM pinout, SI5338L-B05947-GM application, or SI5338L-B05947-GM equivalent, key selection criteria include its MultiSynth™-based any-frequency synthesis (0.16–710 MHz), independent output voltage per driver (1.5/1.8/2.5/3.3 V), low-power 45 mA core supply, spread-spectrum capability (0.5–5.0% deviation), and 24-QFN 4×4 mm package.
Technical Context
The SI5338L-B05947-GM implements a two-stage PLL architecture: a high-performance synthesis stage (VCO + MultiSynth dividers) followed by a flexible output stage with independent format and voltage control per driver. Its patented MultiSynth™ technology enables fractional-N frequency synthesis with true zero-ppm accuracy on all four outputs.
It supports six input types - external crystal (8–30 MHz), CMOS (5–200 MHz), SSTL/HSTL (5–350 MHz), and differential (5–710 MHz) - and delivers configurable outputs in LVPECL, LVDS, HCSL, CML, CMOS, SSTL, or HSTL formats, each with programmable phase offset (<20 ps steps), frequency increment/decrement (1 ppm steps), and spread-spectrum modulation (33–63 kHz rate).
Key Specifications
| Parameter | Value and Actual Design Meaning |
|---|---|
| Phase Jitter (RMS) | 0.7 ps typical (12 kHz–20 MHz); meets PCIe Gen 3 SRNS and GbE jitter requirements |
| Output Frequency Range | 0.16–710 MHz per channel; supports integer/fractional synthesis with <1 ppb resolution |
| Input Reference Support | Crystal (8–30 MHz), CMOS (5–200 MHz), differential (5–710 MHz), SSTL/HSTL (5–350 MHz) |
| Supply Voltages | Core: 1.8/2.5/3.3 V; Output buffers: independently configurable 1.5/1.8/2.5/3.3 V |
| Package | 24-pin QFN, 4 × 4 mm, 0.5 mm pitch; RoHS-compliant, moisture-sensitive level 3 |
| Operating Temperature | –40 to +85 °C ambient; qualified for industrial and telecom line card environments |
| Power Consumption | 45 mA typical core current at 100 MHz on all outputs and 25 MHz reference |
Pinout & Package
SI5338L-B05947-GM is housed in a 24-lead, 4 × 4 mm QFN package with exposed thermal pad. Pin assignments are fixed per the Si5338 family and validated for this variant.
| Pin/Terminal | Circuit Role | Design Meaning |
|---|---|---|
| IN1, IN2, IN5, IN6 | Differential clock inputs | Accept 5–710 MHz AC-coupled differential references; require external 100 Ω termination |
| IN3, IN4 | Single-ended clock inputs | Support 5–200 MHz CMOS, SSTL, or HSTL; VIH = 0.7×VDD, VIL = 0.3×VDD |
| CLK0A/CLK0B to CLK3A/CLK3B | Differential output pairs | Four independent output drivers; each configurable as LVPECL/LVDS/HCSL/CML with selectable VDDOx |
| VDDO0–VDDO3 | Output buffer supplies | Independent 1.4–3.63 V supplies per output bank; enable mixed-voltage system interfacing |
| VDD | Core supply | 1.8/2.5/3.3 V ± tolerance; PSRR optimized for clean internal PLL operation |
| SCL, SDA | I²C interface | SMBus-compatible serial programming; supports ClockBuilder Pro configuration |
| INTR | Interrupt output | Open-drain status pin indicating loss-of-lock or loss-of-signal events |
| GND, RSVD_GND | Ground terminals | Multiple dedicated ground pins and thermal pad connection for low-noise clock distribution |
Key Features
| Feature | Design Value |
|---|---|
| Any-frequency synthesis per output | Four independent MultiSynth™ engines deliver 0.16–710 MHz with zero ppm error and <1 ppb resolution |
| PCIe Gen 1–4 compliance | Validated for Common Clock (Gen 1/2/3/4) and Gen 3 SRNS; 0.11–0.45 ps RMS jitter per spec |
| Independent output voltage control | Each of four output banks powered by separate VDDOx (1.5/1.8/2.5/3.3 V) for multi-protocol interoperability |
| Programmable phase adjustment | ±45 ns range in <20 ps steps per output; enables precise skew management in high-speed SerDes lanes |
| Glitchless frequency tuning | 1 ppm step size via PINC/FDEC pins; no output interruption during real-time frequency updates |
| Spread-spectrum modulation | Configurable 0.5–5.0% down-spread at 33–63 kHz on any output; reduces EMI in dense PCB layouts |
Applications
| Processor and FPGA Clocking | PCIe Gen 3/4 Systems |
|---|---|
Use Scenario: Providing multiple synchronized clocks to heterogeneous SoCs, FPGAs, and memory controllers in AI accelerators or edge compute modules. IC Role / Device Role / Timing Role: Quad-output clock generator delivering independent 100 MHz, 156.25 MHz, 312.5 MHz, and 500 MHz clocks with sub-20 ps inter-output skew. Use Value: Eliminates need for four discrete oscillators; enables dynamic frequency scaling and phase alignment across logic, I/O, and SerDes domains. |
Use Scenario: Generating compliant reference clocks for PCIe root complex and endpoint devices in servers and storage controllers. IC Role / Device Role / Timing Role: PCIe Common Clock source meeting Gen 3 SRNS (0.11–0.32 ps RMS) and Gen 4 (0.15–0.45 ps RMS) jitter limits. Use Value: Ensures link training success and long-term bit-error-rate stability without requiring external jitter cleaners. |
| Ethernet Switch/Routing | Broadcast Video Timing |
Use Scenario: Driving 1 GbE and 10 GbE PHYs, packet processors, and traffic managers in carrier-grade switches. IC Role / Device Role / Timing Role: Low-jitter (0.7 ps RMS) clock source for IEEE 802.3 standards-compliant interfaces with deterministic latency. Use Value: Maintains synchronization across multi-port, multi-rate switching fabrics while supporting IEEE 1588 PTP timestamping. |
Use Scenario: Synchronizing SDI, HDMI, and audio sample clocks in professional broadcast encoders and IP media gateways. IC Role / Device Role / Timing Role: Any-frequency generator producing exact SMPTE ST 2059-2–compliant frequencies (e.g., 27 MHz, 74.25 MHz, 148.5 MHz). Use Value: Enables frame-accurate genlock across video, audio, and metadata streams without external dividers or muxes. |
Equivalent & Alternatives
The following parts are listed as comparable options for similar quad clock generator applications.
| Alternative Part | Technical Difference | Application Difference | Selection Advice |
|---|---|---|---|
| Si5332A-D05947-GM | Higher integration: integrated crystal, lower jitter (0.35 ps RMS), supports up to 10 outputs | Targeted at space-constrained, ultra-low-jitter designs where board area and phase noise are critical | Select when replacing crystal + clock IC combo; requires different layout and ClockBuilder Pro configuration |
| ICS853S01AGI-01LFT | Fixed-frequency, non-programmable; 4 LVDS outputs; 1.2 ps RMS jitter; 3.3 V only | Used in cost-sensitive, static-clocking applications like legacy telecom line cards | Select only if frequency flexibility is unnecessary and BOM simplification outweighs programmability benefits |
Compared with Si5332A-D05947-GM, SI5338L-B05947-GM offers broader input reference support and field-programmability without integrated crystal; compared with ICS853S01AGI-01LFT, it provides full I²C configurability and multi-voltage outputs but requires firmware initialization.
Availability
SI5338L-B05947-GM is available at Aetrix Electronics and suitable for Ethernet switch/router, PCIe Gen 3/4 server platforms, and broadcast video timing systems requiring stable component supply, long-term lifecycle assurance, and traceable sourcing.
Supply support for SI5338L-B05947-GM includes scheduled delivery planning, volume procurement assistance, BOM continuity management, traceable sourcing, and lifecycle availability coordination for OEM customers, industrial embedded developers, connected-device designers, and electronics production programs.
Manufacturer
Skyworks Solutions is a global semiconductor company specializing in analog and mixed-signal connectivity solutions, with leadership in RF, timing, and power management ICs for infrastructure, automotive, and mobile markets.
The Si5338 product line was designed for high-performance, software-configurable clock generation in datacenter, networking, and broadcast equipment-emphasizing low jitter, multi-format flexibility, and PCIe compliance.
FAQ
What is the primary function of the SI5338L-B05947-GM?
The SI5338L-B05947-GM is an I²C-programmable quad clock generator that synthesizes four independent, low-jitter output clocks from a single reference. It serves as a drop-in replacement for multiple crystal oscillators in systems requiring precise, configurable timing-such as PCIe root complexes, Ethernet switches, and FPGA-based video processing platforms-while maintaining 0.7 ps RMS phase jitter and PCIe Gen 4 compliance.
Does the SI5338L-B05947-GM support PCIe Gen 4 timing requirements?
Yes, the SI5338L-B05947-GM meets PCIe Gen 4 Common Clock jitter specifications with 0.15–0.45 ps RMS (12 kHz–20 MHz) when configured per Skyworks' recommended settings-including PLL bandwidth of 2–4 MHz and CDR = 10 MHz. This compliance is verified using the Skyworks PCIe Clock Jitter Tool and aligns with PCI-Express Base Specification 4.0 rev. 0.5.
Can the SI5338L-B05947-GM generate different output voltages simultaneously?
Yes, the SI5338L-B05947-GM supports independent output buffer supplies (VDDO0–VDDO3), enabling simultaneous LVDS (2.5 V), HCSL (1.8 V), CMOS (3.3 V), and SSTL (1.5 V) outputs on its four driver banks. Each VDDO pin accepts 1.4–3.63 V, allowing direct interfacing with mixed-voltage ASICs, FPGAs, and PHYs without level-shifting components.
How is the SI5338L-B05947-GM programmed and configured?
The SI5338L-B05947-GM is programmed via its I²C/SMBus-compatible interface using Skyworks' ClockBuilder Pro software, which generates custom configuration files (.cbpro) and register maps. Configuration can be stored in on-chip OTP NVM for autonomous startup, or loaded dynamically at boot. Pin-controlled frequency/phase adjustments (PINC/FDEC) also enable real-time tuning without host intervention.
What package type and thermal characteristics does the SI5338L-B05947-GM have?
The SI5338L-B05947-GM uses a 24-lead QFN package measuring 4 × 4 mm with 0.5 mm pitch and an exposed thermal pad. Its thermal resistance is θJA = 37 °C/W (still air) and θJC = 10 °C/W, enabling reliable operation at full load across –40 to +85 °C ambient. The package is RoHS-compliant and rated MSL-3 per JEDEC J-STD-020.
SI5338L-B05947-GM Specifications
- Product attributes
- Attribute value
- Manufacturer:
- Skyworks Solutions Inc.
- Series:
- MultiSynth™
- Package/Case:
- 24-VFQFN Exposed Pad
- Packaging:
- Tray
- Product Status:
- Active
- Programmable:
- Not Verified
- PLL:
- -
- Main Purpose:
- -
- Input:
- -
- Output:
- -
- Number of Circuits:
- -
- Ratio - Input:Output:
- -
- Differential - Input:Output:
- -
- Frequency - Max:
- -
- Voltage - Supply:
- -
- Operating Temperature:
- -
- Mounting Type:
- Surface Mount
- Grade:
- -
- Qualification:
- -
- Supplier Device Package:
- 24-QFN (4x4)
SI5338L-B05947-GM FAQ
1.How can I place an order for SI5338L-B05947-GM through Aetrix?
Please submit a Request for Quotation (RFQ) for SI5338L-B05947-GM on Aetrix. Our sales agent will provide a competitive quotation and guide you through the order confirmation once you accept the terms.
2.Are the price and stock information for SI5338L-B05947-GM reliable?
The price and inventory of SI5338L-B05947-GM are updated periodically and may fluctuate due to market conditions. Stock and pricing data are typically refreshed every 24 hours. Quotation validity for SI5338L-B05947-GM is usually 5 days.
3.What payment methods are accepted for SI5338L-B05947-GM?
We accept Wire Transfer, PayPal, Credit Card, Western Union, MoneyGram, and Escrow for SI5338L-B05947-GM transactions.
Note: Certain payment methods may incur a processing fee.
4.How is shipping managed for SI5338L-B05947-GM?
SI5338L-B05947-GM orders can be shipped via leading logistics carriers, including DHL, UPS, FedEx, TNT, or Registered Mail.
Once your SI5338L-B05947-GM order is processed, you will receive an email with the shipment details and tracking number.
Note: Tracking information may take up to 24 hours to appear. Express delivery typically takes 3–5 business days.
5.How can I obtain technical support or documentation for SI5338L-B05947-GM?
For technical support, including SI5338L-B05947-GM datasheets, pinout diagrams, or application guidance, please contact our engineering support team. They can provide detailed documentation and assistance for your SI5338L-B05947-GM requirements.
6.How does Aetrix verify that SI5338L-B05947-GM is sourced from the original manufacturer or authorized distributors?
All SI5338L-B05947-GM products on Aetrix are procured from qualified distributors and authorized channels. Our dedicated quality assurance team conducts strict verification, including traceability checks and, if necessary, third-party testing. This ensures that SI5338L-B05947-GM meets industry standards.
7.What is the process for return or replacement of SI5338L-B05947-GM?
All SI5338L-B05947-GM units undergo pre-shipment inspection (PSI). If there is an issue with SI5338L-B05947-GM, returns or replacements are accepted under the following conditions:
1.Quantity discrepancies, incorrect items, or visible external defects (such as breakage or corrosion), acknowledged by Aetrix.
2.The issue is reported within 90 days of delivery.
3.The SI5338L-B05947-GM part is unused and in its original packaging.
Return procedure for SI5338L-B05947-GM:
1.Submit a request within 90 days.
2.Obtain a Return Material Authorization (RMA) from Aetrix.
SI5338L-B05947-GM Tags

-
LMK00334RTVRQ1
Texas Instruments
.jpg)
-
DSC557-0344FI0T
Microchip Technology

-
9FGV0241AKILFT
Renesas

-
9DBL0452CKILFT
Renesas
.jpg)
-
DSC557-0344FL1T
Microchip Technology
-
RC19008AGND#KB0
Renesas
-
RC19008AGND#BB0
Renesas

-
9DB403DGILFT
Renesas

-
9DB233AGILFT
Renesas

-
9DB803DGILFT
Renesas

-
9FGL0851DKILFT
Renesas
-
AB-557-03-HCHC-F-L-C-T
Abracon LLC
Tech Hub
Counterfeit components can hide behind convincing markings and passing basic function tests. This engineering reference covers source traceability, external inspection, X-ray, XRF, electrical testing, …
A practical engineering and sourcing framework covering lifecycle verification, lifetime-buy calculations, replacement qualification, supplier checks and counterfeit-risk controls.
TTL and CMOS logic families differ in thresholds, loading, output drive, power and timing. This engineering guide compares 74HC and 74HCT, calculates noise margins and checks 3.3 V/5 V compatibility.
A practical engineering guide to 3.3V and 5V logic compatibility, input thresholds, resistor dividers, translator ICs, MOSFET level shifting, I2C pull-ups, timing limits and power-sequencing risks.
The 74HC595 uses push-pull logic outputs, while the TPIC6B595 uses 50 V open-drain DMOS sinks for higher-power loads. This guide compares timing, current limits, 3.3 V interfacing, load wiring, thermal…
The 74HC595 converts serial data into eight stable parallel outputs. This guide covers pin functions, shift and storage timing, OE and MR behavior, drive-current limits, cascading, voltage compatibilit…
A technical comparison of level-sensitive latches and edge-triggered flip-flops, covering timing windows, setup and hold limits, master–slave operation, time borrowing, race-through, HDL inference and…
A D latch stores one bit while Enable controls when data can pass. This reference covers gate-level operation, truth tables, transparency, setup and hold timing, LE versus OE, common ICs and practical …
An SR latch stores one bit through cross-coupled feedback. This engineering reference covers NOR and NAND implementations, truth tables, forbidden-state recovery, gated operation, switch debouncing, fa…
Latch circuits retain one bit through feedback. This technical reference covers SR and D latches, truth tables, transparency, timing limits, latch-versus-flip-flop behavior, applications and common log…

