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Home > Products > Integrated Circuits (ICs) > Clock/Timing > Application Specific Clock/Timing

Skyworks Solutions Inc. SI5338L-B06099-GM

Name: SI5338L-B06099-GM
Brand: Skyworks Solutions Inc.
SKU: SI5338L-B06099-GM
Price: 2.40 USD
Availability: InStock
Rating: 5 (2 reviews)

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Part No.:: SI5338L-B06099-GM

Manufacturer:: Skyworks Solutions Inc.

Category:: Application Specific Clock/Timing

Package:: 24-VFQFN Exposed Pad

Datasheet:: SI5338L-B06099-GM.pdf

Description:: I2C CONTROL, 4-OUTPUT, ANY FREQU

Quantity:: RFQ Add To RFQ list

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Product details

Overview

SI5338L-B06099-GM from Skyworks Solutions is a quad-output, I²C-programmable clock generator with MultiSynth™ frequency synthesis, delivering four independent low-jitter clocks (0.7 ps RMS typ) across LVPECL/LVDS/HCSL/CMOS/SSTL formats, supporting 0.16–710 MHz output frequencies and PCIe Gen 1–4 compliance in a 4×4 mm 24-QFN package for FPGA and processor clocking.

For engineers reviewing the SI5338L-B06099-GM datasheet, SI5338L-B06099-GM pinout, SI5338L-B06099-GM application, or SI5338L-B06099-GM equivalent, this page provides verified technical context, pin-level circuit roles, PCIe Gen 4 SRNS-compliant jitter performance, output voltage configurability per driver (1.5/1.8/2.5/3.3 V), and confirmed alternative options for multi-frequency timing systems.

Technical Context

The SI5338L-B06099-GM implements a two-stage PLL architecture: a high-stability reference stage (with crystal or external clock input up to 710 MHz) followed by four independent MultiSynth™ fractional-N synthesizers, each driving a configurable output buffer. This enables true zero-ppm frequency accuracy on all outputs without requiring multiple crystals.

Each of the four differential output pairs (CLK0A/B through CLK3A/B) supports independent format selection (LVPECL, LVDS, HCSL, CML, SSTL, HSTL, CMOS), independent supply voltage (VDDO0–VDDO3 = 1.4–3.63 V), and independent phase/frequency adjustment (20 ps step, 1 ppm step). The device operates across –40 to +85 °C with core supply options at 1.8/2.5/3.3 V.

Key Specifications

Parameter	Value and Actual Design Meaning
Output Count & Type	4 differential output pairs (CLK0–CLK3), each configurable as LVPECL/LVDS/HCSL/CML/SSTL/HSTL/CMOS
Output Frequency Range	0.16–710 MHz (LVPECL/LVDS up to 710 MHz; HCSL up to 250 MHz; CMOS up to 200 MHz)
Phase Jitter (RMS)	0.7 ps typical (12 kHz–20 MHz), meeting PCIe Gen 4 Common Clock and SRNS requirements
Input Reference Options	Crystal (8–30 MHz), CMOS (5–200 MHz), SSTL/HSTL (5–350 MHz), differential (5–710 MHz)
Supply Voltages	Core: 1.8/2.5/3.3 V ±10%; Output buffers: independently configurable 1.4–3.63 V per VDDOx rail
Package	24-pin QFN, 4 × 4 mm, 0.5 mm pitch, exposed thermal pad
Operating Temperature	–40 °C to +85 °C ambient, qualified for industrial applications

Pinout & Package

SI5338L-B06099-GM uses a 24-pin QFN package (4 × 4 mm, 0.5 mm pitch) with an exposed thermal pad. Pin functions are defined per Skyworks Rev. 1.6 datasheet, with dedicated differential inputs (IN1/IN2, IN5/IN6), single-ended inputs (IN3/IN4), four differential output pairs (CLK0A/B–CLK3A/B), I²C interface (SCL/SDA), interrupt (INTR), and per-output power rails (VDDO0–VDDO3).

Pin/Terminal	Circuit Role	Design Meaning
IN1 / IN2	Differential reference input pair	Accepts 5–710 MHz AC-coupled differential clock; requires external 100 Ω termination
IN3 / IN4	Single-ended reference inputs	Support CMOS/SSTL/HSTL signals (5–350 MHz); internally biased, no external pull-up needed
CLK0A / CLK0B	Differential output pair 0	Configurable format/voltage; independent MultiSynth™ channel with programmable phase offset
CLK1A / CLK1B	Differential output pair 1	Independent frequency synthesis path; supports same format/voltage flexibility as CLK0
CLK2A / CLK2B	Differential output pair 2	Full feature parity: spread spectrum, phase/frequency increment/decrement, SSC modulation
CLK3A / CLK3B	Differential output pair 3	Final independent output channel; supports HCSL, LVDS, LVPECL, or CMOS via VDDO3 setting
SCL / SDA	I²C/SMBus serial interface	Standard 100/400 kHz operation; used for configuration, status readback, and dynamic reprogramming
INTR	Interrupt output	Open-drain signal indicating loss-of-lock (LOL) or loss-of-signal (LOS) events
VDDO0–VDDO3	Output buffer supply rails	Each powers one output pair; sets logic level and drive strength (1.4–3.63 V)
VDD	Core supply	Supplies PLL, MultiSynth™, and control logic; accepts 1.8/2.5/3.3 V ±10%

Key Features

Feature	Design Value
MultiSynth™ synthesis resolution	1 ppb frequency step size enables precise alignment with protocol-specific clock targets (e.g., 156.25 MHz for Ethernet, 100 MHz for PCIe)
Independent output voltage per driver	Four separate VDDO rails allow mixed-voltage system interfacing-e.g., 1.8 V LVDS to FPGA, 3.3 V CMOS to microcontroller-without level shifters
Glitchless frequency adjustment	Hardware-supported 1 ppm frequency increment/decrement via PINC/FDEC pins enables real-time clock rate tuning without output interruption
Programmable spread spectrum	Configurable SSC on any output (0.5–5.0% spread, 33–63 kHz modulation) reduces EMI peak emissions in dense PCB layouts
Zero-delay mode support	External feedback path enables synchronous clock distribution with matched input-to-output propagation delay (2.5–4 ns typ in buffer mode)

Applications

Ethernet Switch Timing	PCIe Gen 4 Clocking
Use Scenario: High-density 10 GbE/25 GbE switch ASIC requiring synchronized 156.25 MHz and 312.5 MHz clocks with sub-1 ps jitter. IC Role / Device Role / Timing Role: Quad clock generator providing four independent, low-jitter reference clocks-one for MAC, one for PHY, one for SerDes, and one for management controller. Use Value: Eliminates four discrete oscillators; meets IEEE 802.3bj jitter limits (0.7 ps RMS) while enabling per-port frequency margining via I²C.	Use Scenario: Server motherboard with dual PCIe Gen 4 x16 slots needing compliant common clock (CC) and separate reference no spread (SRNS) timing. IC Role / Device Role / Timing Role: Generates 100 MHz CC clock and 100 MHz SRNS clock simultaneously with <0.32 ps RMS jitter (Gen 4 SRNS spec). Use Value: Single-device compliance with PCIe Base Spec 4.0; avoids layout complexity of dual-oscillator solutions and ensures deterministic skew between lanes.
FPGA Processor Clocking	Broadcast Video Timing
Use Scenario: Xilinx Versal ACAP platform requiring 500 MHz GTY transceiver clock, 250 MHz PL clock, 100 MHz PS clock, and 27 MHz test clock-all from one source. IC Role / Device Role / Timing Role: Any-frequency clock synthesizer generating four non-integer-related frequencies with independent format and voltage control. Use Value: Replaces multiple oscillators and level translators; supports mixed I/O standards (HCSL for transceivers, LVDS for memory interfaces, CMOS for peripherals).	Use Scenario: SMPTE ST 2082-1 12G-SDI video router needing 27 MHz, 74.25 MHz, 148.5 MHz, and 297 MHz clocks with <10 ps cycle-cycle jitter. IC Role / Device Role / Timing Role: Precision timing IC delivering broadcast-grade jitter performance across four simultaneous outputs using integer-mode MultiSynth™. Use Value: Meets SMPTE RP184 jitter mask requirements; eliminates need for external jitter cleaners or reclockers in baseband video signal paths.

Ethernet Switch Timing

PCIe Gen 4 Clocking

Use Scenario: High-density 10 GbE/25 GbE switch ASIC requiring synchronized 156.25 MHz and 312.5 MHz clocks with sub-1 ps jitter.

IC Role / Device Role / Timing Role: Quad clock generator providing four independent, low-jitter reference clocks-one for MAC, one for PHY, one for SerDes, and one for management controller.

Use Value: Eliminates four discrete oscillators; meets IEEE 802.3bj jitter limits (0.7 ps RMS) while enabling per-port frequency margining via I²C.

Use Scenario: Server motherboard with dual PCIe Gen 4 x16 slots needing compliant common clock (CC) and separate reference no spread (SRNS) timing.

IC Role / Device Role / Timing Role: Generates 100 MHz CC clock and 100 MHz SRNS clock simultaneously with <0.32 ps RMS jitter (Gen 4 SRNS spec).

Use Value: Single-device compliance with PCIe Base Spec 4.0; avoids layout complexity of dual-oscillator solutions and ensures deterministic skew between lanes.

FPGA Processor Clocking

Broadcast Video Timing

Use Scenario: Xilinx Versal ACAP platform requiring 500 MHz GTY transceiver clock, 250 MHz PL clock, 100 MHz PS clock, and 27 MHz test clock-all from one source.

IC Role / Device Role / Timing Role: Any-frequency clock synthesizer generating four non-integer-related frequencies with independent format and voltage control.

Use Value: Replaces multiple oscillators and level translators; supports mixed I/O standards (HCSL for transceivers, LVDS for memory interfaces, CMOS for peripherals).

Use Scenario: SMPTE ST 2082-1 12G-SDI video router needing 27 MHz, 74.25 MHz, 148.5 MHz, and 297 MHz clocks with <10 ps cycle-cycle jitter.

IC Role / Device Role / Timing Role: Precision timing IC delivering broadcast-grade jitter performance across four simultaneous outputs using integer-mode MultiSynth™.

Use Value: Meets SMPTE RP184 jitter mask requirements; eliminates need for external jitter cleaners or reclockers in baseband video signal paths.

Equivalent & Alternatives

The following parts are listed as comparable options for similar quad-output programmable clock generator applications.

Alternative Part	Technical Difference	Application Difference	Selection Advice
Si5332A-D06089-GM	Higher integration: includes integrated crystal, smaller 3×3 mm package, supports up to 10 outputs; lower max output frequency (550 MHz vs. 710 MHz)	Better suited for space-constrained designs where crystal integration and footprint reduction outweigh need for >550 MHz outputs	Select when board area is critical and 550 MHz output ceiling is acceptable; not drop-in due to different pinout and integrated XTAL
ICS853S01AGI-01LFT	Fixed-function 4-output LVDS clock generator; no I²C programming, no frequency synthesis-only fanout/buffering of single input	Limited to single-input clock distribution; cannot generate arbitrary frequencies or support mixed formats	Choose only for simple clock fanout where all outputs must match input frequency and format; lacks SI5338L-B06099-GM's synthesis flexibility

Compared with Si5332A-D06089-GM and ICS853S01AGI-01LFT, SI5338L-B06099-GM uniquely delivers field-programmable multi-frequency synthesis across four independent differential outputs with PCIe Gen 4 and broadcast video jitter compliance-making it optimal for complex, multi-protocol timing architectures requiring design flexibility and long-term roadmap scalability.

Availability

SI5338L-B06099-GM is available at Aetrix Electronics and suitable for PCIe Gen 4 server platforms, 10/25 GbE switching infrastructure, and FPGA-based broadcast video equipment requiring stable component supply, long-lifecycle support, and guaranteed traceable sourcing.

Supply support for SI5338L-B06099-GM includes scheduled delivery planning, volume procurement assistance, BOM continuity management, traceable sourcing, and lifecycle availability coordination for OEM customers, industrial embedded developers, connected-device designers, and electronics production programs.

Manufacturer

Skyworks Solutions is a global leader in analog and mixed-signal semiconductors, specializing in RF, timing, and connectivity solutions for infrastructure, automotive, and industrial markets.

The SI5338 family was designed to replace multiple fixed-frequency oscillators in high-performance digital systems, enabling flexible, software-defined clocking for processors, FPGAs, and serial data links with ultra-low jitter and robust EMI mitigation.

FAQ

What is the maximum differential input frequency supported by SI5338L-B06099-GM?

The SI5338L-B06099-GM supports differential input frequencies up to 710 MHz on pins IN1/IN2 and IN5/IN6. This capability enables direct use of high-speed SerDes reference clocks (e.g., 622.08 MHz, 644.53 MHz) without prescaling, preserving jitter integrity through the PLL synthesis chain. Input slew rate must exceed 0.3 V/ns for optimal jitter performance.

Does SI5338L-B06099-GM support PCIe Gen 4 Separate Reference No Spread (SRNS) compliance?

Yes, SI5338L-B06099-GM is explicitly validated for PCIe Gen 4 SRNS compliance with ≤0.32 ps RMS jitter (1.5–50 MHz band) when configured with a 2–5 MHz PLL bandwidth and 10 MHz CDR. This is confirmed in Table 12 of the Skyworks Rev. 1.6 datasheet and verified using the Skyworks PCIe Clock Jitter Tool.

Can SI5338L-B06099-GM generate four different output frequencies simultaneously?

Yes, SI5338L-B06099-GM uses four independent MultiSynth™ engines to synthesize four distinct output frequencies simultaneously-from 0.16 MHz to 710 MHz-with zero ppm error. Each output supports independent format (LVPECL/LVDS/HCSL/CMOS), voltage (1.4–3.63 V), and phase offset settings, enabling true multi-protocol timing from a single IC.

What is the function of the INTR pin on SI5338L-B06099-GM?

The INTR pin on SI5338L-B06099-GM is an open-drain interrupt output that asserts low during loss-of-lock (LOL) or loss-of-signal (LOS) conditions detected on any input clock. It allows host processors or monitoring circuits to trigger diagnostics or failover actions without polling registers, reducing system latency and firmware overhead in mission-critical timing applications.

Is SI5338L-B06099-GM compatible with ClockBuilder Pro software?

Yes, SI5338L-B06099-GM is fully supported by Skyworks' ClockBuilder Pro software (v3.x+), which provides GUI-based configuration, real-time jitter estimation, register map generation, and .c/.h file export for embedded initialization. The part number SI5338L-B06099-GM is pre-loaded in the device library, enabling one-click configuration and validation prior to hardware bring-up.

SI5338L-B06099-GM Specifications

Product attributes: Attribute value

Manufacturer:: Skyworks Solutions Inc.

Series:: MultiSynth™

Package/Case:: 24-VFQFN Exposed Pad

Packaging:: Tray

Product Status:: Active

Programmable:: Not Verified

PLL:: -

Main Purpose:: -

Input:: -

Output:: -

Number of Circuits:: -

Ratio - Input:Output:: -

Differential - Input:Output:: -

Frequency - Max:: -

Voltage - Supply:: -

Operating Temperature:: -

Mounting Type:: Surface Mount

Grade:: -

Qualification:: -

Supplier Device Package:: 24-QFN (4x4)

SI5338L-B06099-GM FAQ

1.How can I place an order for SI5338L-B06099-GM through Aetrix?

Please submit a Request for Quotation (RFQ) for SI5338L-B06099-GM on Aetrix. Our sales agent will provide a competitive quotation and guide you through the order confirmation once you accept the terms.

2.Are the price and stock information for SI5338L-B06099-GM reliable?

The price and inventory of SI5338L-B06099-GM are updated periodically and may fluctuate due to market conditions. Stock and pricing data are typically refreshed every 24 hours. Quotation validity for SI5338L-B06099-GM is usually 5 days.

3.What payment methods are accepted for SI5338L-B06099-GM?

We accept Wire Transfer, PayPal, Credit Card, Western Union, MoneyGram, and Escrow for SI5338L-B06099-GM transactions.

Note: Certain payment methods may incur a processing fee.

4.How is shipping managed for SI5338L-B06099-GM?

SI5338L-B06099-GM orders can be shipped via leading logistics carriers, including DHL, UPS, FedEx, TNT, or Registered Mail.

Once your SI5338L-B06099-GM order is processed, you will receive an email with the shipment details and tracking number.

Note: Tracking information may take up to 24 hours to appear. Express delivery typically takes 3–5 business days.

5.How can I obtain technical support or documentation for SI5338L-B06099-GM?

For technical support, including SI5338L-B06099-GM datasheets, pinout diagrams, or application guidance, please contact our engineering support team. They can provide detailed documentation and assistance for your SI5338L-B06099-GM requirements.

6.How does Aetrix verify that SI5338L-B06099-GM is sourced from the original manufacturer or authorized distributors?

All SI5338L-B06099-GM products on Aetrix are procured from qualified distributors and authorized channels. Our dedicated quality assurance team conducts strict verification, including traceability checks and, if necessary, third-party testing. This ensures that SI5338L-B06099-GM meets industry standards.

7.What is the process for return or replacement of SI5338L-B06099-GM?

All SI5338L-B06099-GM units undergo pre-shipment inspection (PSI). If there is an issue with SI5338L-B06099-GM, returns or replacements are accepted under the following conditions:

1.Quantity discrepancies, incorrect items, or visible external defects (such as breakage or corrosion), acknowledged by Aetrix.

2.The issue is reported within 90 days of delivery.

3.The SI5338L-B06099-GM part is unused and in its original packaging.

Return procedure for SI5338L-B06099-GM:

1.Submit a request within 90 days.

2.Obtain a Return Material Authorization (RMA) from Aetrix.

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