Skyworks Solutions Inc. SI5338L-B06099-GMR

Overview

SI5338L-B06099-GMR from Skyworks Solutions is an I²C-programmable quad clock generator with four independently configurable differential or single-ended outputs, 0.7 ps RMS typical phase jitter, PCIe Gen 1–4 Common Clock and Gen 3 SRNS compliance, and operation across –40 to +85 °C. It replaces up to four crystal oscillators in high-speed serial interface timing applications such as PCIe root complexes and FPGA-based networking systems.

For engineers reviewing the SI5338L-B06099-GMR datasheet, SI5338L-B06099-GMR pinout, SI5338L-B06099-GMR application, or SI5338L-B06099-GMR equivalent, key selection criteria include its MultiSynth™-based any-frequency synthesis (0.16–710 MHz per output), independent output voltage control (1.5/1.8/2.5/3.3 V), spread-spectrum capability (0.5–5.0% down-spread), and 24-QFN package compatibility with space-constrained PCB layouts.

Technical Context

The SI5338L-B06099-GMR implements a two-stage PLL architecture: a high-stability integer-N PLL (Stage 1) locks to one of six input references (crystal, CMOS, SSTL/HSTL, or differential), followed by four independent MultiSynth™ fractional-N synthesizers (Stage 2) generating precise output frequencies. Each output driver supports LVPECL/LVDS/HCSL/CMOS/SSTL/HSTL formats with programmable slew rate and termination.

It features loss-of-lock and loss-of-signal monitoring, independent 20-ps-step phase adjustment per output, glitchless ±1 ppm frequency increment/decrement via pin or I²C, and external feedback mode for zero-delay operation. The device uses on-chip OTP memory for factory-programmed configurations and supports ClockBuilder Pro for register-level customization.

Key Specifications

Pinout & Package

SI5338L-B06099-GMR is housed in a 24-lead, 4 × 4 mm QFN package with exposed thermal pad. Pin assignments are fixed per the Si5338 family and validated for this variant.

Key Features

Applications

Equivalent & Alternatives

The following parts are listed as comparable options for similar quad-output programmable clock generator applications.

Compared with SI5338L-B06099-GMR, Si5338A-B06089-GM offers identical architecture but different factory settings - requiring full register verification - while ICS853S01AGI-01LFT sacrifices programmability and jitter performance for simplicity and lower cost.

Availability

SI5338L-B06099-GMR is available at Aetrix Electronics and suitable for PCIe Gen 4 host platforms, 10 GbE switch fabrics, and FPGA-based broadcast video systems requiring stable component supply, long-term lifecycle assurance, and guaranteed traceable sourcing.

Supply support for SI5338L-B06099-GMR includes scheduled delivery planning, volume procurement assistance, BOM continuity management, traceable sourcing, and lifecycle availability coordination for OEM customers, industrial embedded developers, connected-device designers, and electronics production programs.

Manufacturer

Skyworks Solutions is a global leader in analog and mixed-signal semiconductors, specializing in RF, timing, and connectivity solutions for infrastructure, automotive, and mobile markets.

The Si5338 product line delivers high-precision, software-programmable clock generation for high-speed serial interfaces - designed specifically to replace multiple discrete oscillators and simplify timing architecture in PCIe, Ethernet, and telecom systems.

FAQ

What is the default factory configuration of the SI5338L-B06099-GMR?

The SI5338L-B06099-GMR ships with a pre-programmed configuration stored in on-chip OTP memory, including specific output frequencies, formats, and voltage settings defined by Skyworks part number B06099. This configuration is loaded automatically at power-up and does not require external I²C initialization. Users can reprogram SI5338L-B06099-GMR via I²C using ClockBuilder Pro, but the original B06099 settings remain recoverable.

Does the SI5338L-B06099-GMR support PCIe Gen 4 Separate Reference No Spread (SRNS) mode?

Yes, the SI5338L-B06099-GMR supports PCIe Gen 4 SRNS mode with 0.15–0.45 ps RMS jitter (typ./max) when configured with a PLL bandwidth of 2–5 MHz and CDR = 10 MHz. This is validated per PCI-SIG Base Specification 4.0 rev. 0.5 and confirmed using the Skyworks PCIe Clock Jitter Tool. The device must be programmed with appropriate loop filter coefficients and output format (HCSL recommended) to meet SRNS requirements.

Can the SI5338L-B06099-GMR generate three outputs above 350 MHz simultaneously?

No. The SI5338L-B06099-GMR supports only two unique frequencies above 350 MHz simultaneously - specifically Fvco/4 and Fvco/6 - due to VCO frequency constraints in the MultiSynth™ architecture. Attempting to configure three >350 MHz outputs will result in invalid synthesis or failure to lock. Valid high-frequency combinations must be verified using ClockBuilder Pro's constraint checker before deployment.

What is the maximum allowable input slew rate for differential clock inputs on the SI5338L-B06099-GMR?

For optimal jitter performance, the SI5338L-B06099-GMR requires a minimum differential input slew rate of >0.3 V/ns on pins IN1/IN2 and IN5/IN6. Slew rates below this threshold increase deterministic jitter and may degrade PCIe or OC-12 compliance. Measured at 20–80% crossing, this corresponds to <1.0 ns rise/fall time for a 2.4 VPP swing. External AC coupling and proper termination are mandatory to maintain signal integrity.

How does the SI5338L-B06099-GMR handle loss-of-signal detection on single-ended inputs?

The SI5338L-B06099-GMR detects loss-of-signal (LOS) on single-ended inputs (IN3/IN4) within 2.6–5 µs and releases the alarm within 0.01–1 µs after signal restoration. However, LOS functionality is disabled in PLL bypass (clock buffer) mode below 5 MHz input frequency. For reliable LOS operation, the input must meet specified voltage thresholds (VIH ≥ 0.7×VDD, VIL ≤ 0.3×VDD) and slew rate (>1 V/ns) per Table 7 of the datasheet.