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Home > Products > Integrated Circuits (ICs) > Clock/Timing > Application Specific Clock/Timing

Skyworks Solutions Inc. SI5338L-B06100-GM

Name: SI5338L-B06100-GM
Brand: Skyworks Solutions Inc.
SKU: SI5338L-B06100-GM
Price: 2.40 USD
Availability: InStock
Rating: 5 (2 reviews)

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Part No.:: SI5338L-B06100-GM

Manufacturer:: Skyworks Solutions Inc.

Category:: Application Specific Clock/Timing

Package:: 24-VFQFN Exposed Pad

Datasheet:: SI5338L-B06100-GM.pdf

Description:: I2C CONTROL, 4-OUTPUT, ANY FREQU

Quantity:: RFQ Add To RFQ list

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Product details

Overview

SI5338L-B06100-GM from Skyworks Solutions is an I²C-programmable quad clock generator IC with four independently configurable differential or single-ended outputs, 0.7 ps RMS typical phase jitter, PCIe Gen 1–4 Common Clock and Gen 3 SRNS compliance, and operation from 1.8/2.5/3.3 V core supply in a 4 × 4 mm 24-QFN package. It replaces up to four crystal oscillators in high-speed serial interface timing applications.

For engineers reviewing the SI5338L-B06100-GM datasheet, SI5338L-B06100-GM pinout, SI5338L-B06100-GM application, or SI5338L-B06100-GM equivalent, key selection considerations include its MultiSynth™-based any-frequency synthesis (0.16–710 MHz per output), independent output voltage control (1.5–3.3 V), ±20 ps phase step resolution, and spread-spectrum capability (0.5–5.0% deviation, 33–63 kHz modulation).

Technical Context

The SI5338L-B06100-GM integrates a two-stage PLL architecture: a high-performance integer-N PLL (1.6 MHz loop bandwidth) for low-noise reference conditioning, followed by four independent MultiSynth™ fractional-N synthesis blocks enabling zero-ppm frequency accuracy on each output. Input flexibility includes external crystal (8–30 MHz), CMOS (5–200 MHz), SSTL/HSTL (5–350 MHz), or differential (5–710 MHz) references.

Each of the four output drivers supports LVPECL/LVDS/HCSL/CMOS/SSTL/HSTL formats with independent supply voltage (VDDO0–VDDO3), programmable initial phase offset (±45 ns), glitchless frequency increment/decrement (1 ppm steps), and configurable spread spectrum. Loss-of-lock and loss-of-signal alarms provide real-time status monitoring via the INTR pin.

Key Specifications

Parameter	Value and Actual Design Meaning
Phase Jitter (RMS)	0.7 ps typical - meets PCIe Gen 4 common clock jitter requirement (≤0.45 ps RMS) when configured per spec.
Output Frequency Range	0.16–710 MHz - covers Ethernet (125/156.25 MHz), PCIe (100 MHz), Fibre Channel (1.0625 GHz ÷2 = 531.25 MHz), and broadcast video (27/74.25/148.5 MHz).
Input Reference Support	Crystal (8–30 MHz), CMOS (5–200 MHz), SSTL/HSTL (5–350 MHz), differential (5–710 MHz) - enables direct replacement of multiple discrete clocks without external buffers.
Output Format Flexibility	LVPECL/LVDS/HCSL/CMOS/SSTL/HSTL per channel - allows mixed-signal board-level clock distribution to FPGAs, processors, and SerDes PHYs.
Supply Voltage	Core: 1.8/2.5/3.3 V ±10%; Output buffers: 1.4–3.63 V - supports heterogeneous voltage domains across SoC, FPGA, and memory interfaces.
Package	24-pin QFN, 4 × 4 mm, 0.5 mm pitch - compact footprint compatible with high-density PCB layouts and automated assembly.
Operating Temperature	–40 to +85 °C - qualified for industrial and telecom line card environments without derating.

Pinout & Package

SI5338L-B06100-GM uses a 24-lead QFN package (4 × 4 mm, 0.5 mm pitch) with exposed thermal pad. Pin assignments are fixed per Skyworks Si5338 family specification.

Pin/Terminal	Circuit Role	Design Meaning
IN1, IN2, IN5, IN6	Differential input pairs	Accept AC-coupled LVDS/LVPECL/CML references up to 710 MHz; internal 100 Ω termination enabled.
IN3, IN4	Single-ended CMOS/SSTL/HSTL inputs	Support DC-coupled clocks from 5–350 MHz; VIH/VIL thresholds scale with VDD.
CLK0A/CLK0B – CLK3A/CLK3B	Differential output pairs	Four independent output channels; each pair configurable as LVPECL/LVDS/HCSL/CML with dedicated VDDOx supply.
VDDO0–VDDO3	Output buffer supplies	Independent 1.4–3.63 V rails per output bank - enables mixed-voltage clocking (e.g., 1.8 V FPGA + 3.3 V legacy ASIC).
VDD	Core supply	1.8/2.5/3.3 V ±10% - powers PLL, MultiSynth, and control logic; PSRR optimized for noisy system rails.
SCL, SDA	I²C/SMBus interface	Standard 100/400 kHz operation; supports ClockBuilder Pro programming and runtime reconfiguration.
INTR	Interrupt output	Open-drain status pin asserting loss-of-lock or loss-of-signal; active-low, 3 mA sink capability.
RSVD_GND	Reserved ground	Internal test pin; must be connected to GND per layout guidelines to ensure thermal and EMI performance.

Key Features

Feature	Design Value
MultiSynth™ any-frequency synthesis	Four independent outputs with true zero-ppm accuracy across 0.16–710 MHz - eliminates need for multiple crystals or fixed-ratio PLLs.
PCIe Gen 1–4 Common Clock & Gen 3 SRNS compliance	Validated jitter performance (≤0.32 ps RMS for SRNS, ≤0.45 ps RMS for Gen 4 CC) - enables drop-in use in server, storage, and switch designs.
Independent output voltage per driver	VDDO0–VDDO3 support 1.5/1.8/2.5/3.3 V - simplifies multi-voltage clock tree design without level shifters.
Glitchless frequency increment/decrement	1 ppm step size with <667 ns update time - enables dynamic frequency scaling in adaptive computing or power-aware systems.
Programmable spread spectrum	0.5–5.0% spread, 33–63 kHz modulation rate on any output - reduces EMI peak emissions for FCC/CE certification.
External feedback mode	Supports zero-delay configuration - maintains deterministic phase alignment between input and output clocks for synchronous systems.

Applications

Ethernet Switch/Routing	PCIe Gen 1–4 Timing
Use Scenario: High-port-count 1/10 GbE switches requiring synchronized 125 MHz and 156.25 MHz clocks for MAC/PHY layers and packet buffering. IC Role / Device Role / Timing Role: Quad clock generator providing four precisely aligned, low-jitter clocks - one for CPU/FPGA fabric, one for SerDes, one for memory controller, and one for management subsystem. Use Value: Replaces four discrete oscillators while maintaining <10 ps output-to-output skew and meeting IEEE 802.3 clause 49 jitter limits.	Use Scenario: Server motherboard with multiple PCIe slots (Gen 3/4), requiring compliant 100 MHz reference clocks with SRNS or common clock topology. IC Role / Device Role / Timing Role: PCIe-compliant clock source delivering four identical or frequency-shifted 100 MHz outputs with <0.32 ps RMS jitter (SRNS) or <0.45 ps RMS (Gen 4 CC). Use Value: Eliminates need for separate PCIe clock buffers and satisfies Intel Platform Design Guide jitter requirements without external filtering.
Broadcast Video/Audio Timing	Processor & FPGA Clocking
Use Scenario: SMPTE ST 2082/2110 IP video routers needing 27 MHz, 74.25 MHz, and 148.5 MHz pixel clocks with sub-100 ps period jitter. IC Role / Device Role / Timing Role: Any-frequency synthesizer generating exact SMPTE-standard frequencies from a single 25 MHz crystal reference. Use Value: Achieves <0.7 ps RMS phase jitter at 148.5 MHz - exceeds SMPTE RP184-2017 stability requirements for 4K/8K baseband transport.	Use Scenario: Heterogeneous compute platform with ARM SoC (1.8 V), Xilinx FPGA (2.5 V), DDR4 memory (1.2 V), and peripheral controllers (3.3 V). IC Role / Device Role / Timing Role: Configurable clock hub supplying domain-specific frequencies (e.g., 500 MHz CPU, 250 MHz FPGA fabric, 1333 MHz DDR4) with independent voltage rails. Use Value: Reduces BOM count by consolidating six clock sources into one IC while supporting mixed-voltage I/O standards without external regulators.

Ethernet Switch/Routing

PCIe Gen 1–4 Timing

Use Scenario: High-port-count 1/10 GbE switches requiring synchronized 125 MHz and 156.25 MHz clocks for MAC/PHY layers and packet buffering.

IC Role / Device Role / Timing Role: Quad clock generator providing four precisely aligned, low-jitter clocks - one for CPU/FPGA fabric, one for SerDes, one for memory controller, and one for management subsystem.

Use Value: Replaces four discrete oscillators while maintaining <10 ps output-to-output skew and meeting IEEE 802.3 clause 49 jitter limits.

Use Scenario: Server motherboard with multiple PCIe slots (Gen 3/4), requiring compliant 100 MHz reference clocks with SRNS or common clock topology.

IC Role / Device Role / Timing Role: PCIe-compliant clock source delivering four identical or frequency-shifted 100 MHz outputs with <0.32 ps RMS jitter (SRNS) or <0.45 ps RMS (Gen 4 CC).

Use Value: Eliminates need for separate PCIe clock buffers and satisfies Intel Platform Design Guide jitter requirements without external filtering.

Broadcast Video/Audio Timing

Processor & FPGA Clocking

Use Scenario: SMPTE ST 2082/2110 IP video routers needing 27 MHz, 74.25 MHz, and 148.5 MHz pixel clocks with sub-100 ps period jitter.

IC Role / Device Role / Timing Role: Any-frequency synthesizer generating exact SMPTE-standard frequencies from a single 25 MHz crystal reference.

Use Value: Achieves <0.7 ps RMS phase jitter at 148.5 MHz - exceeds SMPTE RP184-2017 stability requirements for 4K/8K baseband transport.

Use Scenario: Heterogeneous compute platform with ARM SoC (1.8 V), Xilinx FPGA (2.5 V), DDR4 memory (1.2 V), and peripheral controllers (3.3 V).

IC Role / Device Role / Timing Role: Configurable clock hub supplying domain-specific frequencies (e.g., 500 MHz CPU, 250 MHz FPGA fabric, 1333 MHz DDR4) with independent voltage rails.

Use Value: Reduces BOM count by consolidating six clock sources into one IC while supporting mixed-voltage I/O standards without external regulators.

Equivalent & Alternatives

The following parts are listed as comparable options for similar quad clock generator applications.

Alternative Part	Technical Difference	Application Difference	Selection Advice
Si5332A-D06100-GM	Higher integration: integrated crystal, lower jitter (0.35 ps RMS), supports up to 10 outputs; requires different programming flow.	Targeted at space-constrained, ultra-low-jitter applications (e.g., 5G radio units); not pin-compatible.	Select when crystal integration and sub-0.4 ps jitter are mandatory; accept higher cost and ClockBuilder Desktop dependency.
ICS853S01I	Fixed-frequency, non-programmable quad LVDS clock buffer; no synthesis capability; 1.2 ps RMS jitter; 32-QFN package.	Used only where all required frequencies are fixed and known at design stage; no runtime reconfiguration.	Select for cost-sensitive, high-volume applications with static clock trees; avoid when frequency agility or PCIe SRNS compliance is needed.

Compared with Si5332A-D06100-GM, SI5338L-B06100-GM offers field-programmability and broader input flexibility but higher jitter; compared with ICS853S01I, it provides full any-frequency synthesis and PCIe compliance at the cost of complexity and price.

Availability

SI5338L-B06100-GM is available at Aetrix Electronics and suitable for Ethernet switch/router, PCIe Gen 1–4 timing, and broadcast video/audio timing applications requiring stable component supply, long-term lifecycle support, and traceable sourcing.

Supply support for SI5338L-B06100-GM includes scheduled delivery planning, volume procurement assistance, BOM continuity management, traceable sourcing, and lifecycle availability coordination for OEM customers, industrial embedded developers, connected-device designers, and electronics production programs.

Manufacturer

Skyworks Solutions is a global semiconductor company specializing in analog and mixed-signal connectivity solutions, with leadership in RF, timing, and precision analog ICs for infrastructure, automotive, and mobile markets.

The Si5338 product line delivers programmable, low-jitter clock generation for high-speed serial interfaces including PCIe, Ethernet, Fibre Channel, and broadcast video - designed to replace multiple discrete oscillators with a single configurable IC.

FAQ

What is the primary function of the SI5338L-B06100-GM in a system design?

The SI5338L-B06100-GM serves as a programmable quad clock generator that synthesizes four independent, low-jitter output clocks from a single reference input. Its core function is to replace multiple fixed-frequency crystal oscillators or clock buffers while supporting PCIe Gen 1–4, Ethernet, and broadcast video timing standards. The SI5338L-B06100-GM enables flexible, software-defined clock trees in FPGA, processor, and switch designs.

Does the SI5338L-B06100-GM support PCIe Gen 4 Common Clock compliance?

Yes, the SI5338L-B06100-GM is validated for PCIe Gen 4 Common Clock compliance with ≤0.45 ps RMS jitter (10 kHz–50 MHz) when configured per Skyworks application note AN562 using HCSL 100 MHz outputs and appropriate loop bandwidth settings. This compliance is measured using the Skyworks PCIe Clock Jitter Tool and aligns with PCI-SIG Base Specification 4.0 rev. 0.5.

Can the SI5338L-B06100-GM generate different output voltages on each channel?

Yes, the SI5338L-B06100-GM supports independent output supply rails (VDDO0–VDDO3) ranging from 1.4 V to 3.63 V. Each output driver can be configured for 1.5 V, 1.8 V, 2.5 V, or 3.3 V logic levels - enabling simultaneous clocking of mixed-voltage devices such as 1.8 V FPGAs and 3.3 V legacy peripherals without external level shifters.

What programming interface does the SI5338L-B06100-GM use, and is external hardware required?

The SI5338L-B06100-GM uses an I²C/SMBus-compatible serial interface (SCL/SDA pins) for configuration. Programming is performed using Skyworks' ClockBuilder Pro software, which runs on Windows PCs and connects via USB-to-I²C adapter (e.g., Si5338-EVB or third-party FTDI-based programmers). No dedicated hardware programmer is required beyond standard I²C host capability.

How does the SI5338L-B06100-GM handle loss-of-signal or loss-of-lock conditions?

The SI5338L-B06100-GM monitors input reference integrity and PLL lock status continuously. Upon detection of loss-of-signal (LOS) or loss-of-lock (LOL), it asserts the open-drain INTR pin low within 2.6–5 µs (LOS) or 5–10 ms (LOL). These events are also latched in internal status registers accessible via I²C, allowing host firmware to trigger failover or diagnostic routines without external supervision circuitry.

SI5338L-B06100-GM Specifications

Product attributes: Attribute value

Manufacturer:: Skyworks Solutions Inc.

Series:: MultiSynth™

Package/Case:: 24-VFQFN Exposed Pad

Packaging:: Tray

Product Status:: Active

Programmable:: Not Verified

PLL:: -

Main Purpose:: -

Input:: -

Output:: -

Number of Circuits:: -

Ratio - Input:Output:: -

Differential - Input:Output:: -

Frequency - Max:: -

Voltage - Supply:: -

Operating Temperature:: -

Mounting Type:: Surface Mount

Grade:: -

Qualification:: -

Supplier Device Package:: 24-QFN (4x4)

SI5338L-B06100-GM FAQ

1.How can I place an order for SI5338L-B06100-GM through Aetrix?

Please submit a Request for Quotation (RFQ) for SI5338L-B06100-GM on Aetrix. Our sales agent will provide a competitive quotation and guide you through the order confirmation once you accept the terms.

2.Are the price and stock information for SI5338L-B06100-GM reliable?

The price and inventory of SI5338L-B06100-GM are updated periodically and may fluctuate due to market conditions. Stock and pricing data are typically refreshed every 24 hours. Quotation validity for SI5338L-B06100-GM is usually 5 days.

3.What payment methods are accepted for SI5338L-B06100-GM?

We accept Wire Transfer, PayPal, Credit Card, Western Union, MoneyGram, and Escrow for SI5338L-B06100-GM transactions.

Note: Certain payment methods may incur a processing fee.

4.How is shipping managed for SI5338L-B06100-GM?

SI5338L-B06100-GM orders can be shipped via leading logistics carriers, including DHL, UPS, FedEx, TNT, or Registered Mail.

Once your SI5338L-B06100-GM order is processed, you will receive an email with the shipment details and tracking number.

Note: Tracking information may take up to 24 hours to appear. Express delivery typically takes 3–5 business days.

5.How can I obtain technical support or documentation for SI5338L-B06100-GM?

For technical support, including SI5338L-B06100-GM datasheets, pinout diagrams, or application guidance, please contact our engineering support team. They can provide detailed documentation and assistance for your SI5338L-B06100-GM requirements.

6.How does Aetrix verify that SI5338L-B06100-GM is sourced from the original manufacturer or authorized distributors?

All SI5338L-B06100-GM products on Aetrix are procured from qualified distributors and authorized channels. Our dedicated quality assurance team conducts strict verification, including traceability checks and, if necessary, third-party testing. This ensures that SI5338L-B06100-GM meets industry standards.

7.What is the process for return or replacement of SI5338L-B06100-GM?

All SI5338L-B06100-GM units undergo pre-shipment inspection (PSI). If there is an issue with SI5338L-B06100-GM, returns or replacements are accepted under the following conditions:

1.Quantity discrepancies, incorrect items, or visible external defects (such as breakage or corrosion), acknowledged by Aetrix.

2.The issue is reported within 90 days of delivery.

3.The SI5338L-B06100-GM part is unused and in its original packaging.

Return procedure for SI5338L-B06100-GM:

1.Submit a request within 90 days.

2.Obtain a Return Material Authorization (RMA) from Aetrix.

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