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Home > Products > Integrated Circuits (ICs) > Clock/Timing > Application Specific Clock/Timing

Skyworks Solutions Inc. SI5338L-B06100-GMR

Name: SI5338L-B06100-GMR
Brand: Skyworks Solutions Inc.
SKU: SI5338L-B06100-GMR
Price: 2.40 USD
Availability: InStock
Rating: 5 (2 reviews)

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Part No.:: SI5338L-B06100-GMR

Manufacturer:: Skyworks Solutions Inc.

Category:: Application Specific Clock/Timing

Package:: 24-VFQFN Exposed Pad

Datasheet:: SI5338L-B06100-GMR.pdf

Description:: I2C CONTROL, 4-OUTPUT, ANY FREQU

Quantity:: RFQ Add To RFQ list

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Product details

Overview

SI5338L-B06100-GMR from Skyworks Solutions is an I²C-programmable quad clock generator IC with four independently configurable differential or single-ended outputs, 0.7 ps RMS typical phase jitter, PCIe Gen 1–4 Common Clock and Gen 3 SRNS compliance, and operation from 1.8/2.5/3.3 V core supply in a 4 × 4 mm 24-QFN package. It replaces up to four crystal oscillators in high-speed serial interface timing applications.

For engineers reviewing the SI5338L-B06100-GMR datasheet, SI5338L-B06100-GMR pinout, SI5338L-B06100-GMR application, or SI5338L-B06100-GMR equivalent, key selection criteria include PCIe Gen 4 jitter compliance (0.15–0.45 ps RMS), independent output voltage per driver (1.5/1.8/2.5/3.3 V), MultiSynth™ fractional synthesis resolution (1 ppb), spread-spectrum control (0.5–5.0% deviation), and loss-of-lock/loss-of-signal alarm support.

Technical Context

The SI5338L-B06100-GMR implements a two-stage PLL architecture: a high-stability integer-N PLL for reference conditioning followed by four independent MultiSynth™ fractional-N synthesizers-one per output channel-enabling true any-frequency generation with zero ppm accuracy. Each synthesizer supports programmable phase offset (<20 ps step), frequency increment/decrement (1 ppm steps), and spread-spectrum modulation (33–63 kHz rate).

Input flexibility includes external crystal (8–30 MHz), CMOS (5–200 MHz), SSTL/HSTL (5–350 MHz), or differential (5–710 MHz) references. Output drivers support LVPECL/LVDS/HCSL/CMOS/SSTL/HSTL formats across 0.16–710 MHz, with independent VDDO per bank (1.4–3.63 V) and internal 22 Ω series termination on differential outputs.

Key Specifications

Parameter	Value and Actual Design Meaning
Phase Jitter (RMS)	0.7 ps typical (12 kHz–20 MHz); meets PCIe Gen 4 common clock spec (≤0.45 ps RMS)
Output Count & Type	4 independent outputs; configurable as differential (LVPECL/LVDS/HCSL/CML) or single-ended (CMOS/SSTL/HSTL)
Frequency Range	0.16–710 MHz per output; supports Fvco/4 and Fvco/6 for >350 MHz outputs (two unique frequencies max)
Synthesis Resolution	1 ppb; enables exact frequency match without rounding error in integer or fractional mode
Supply Voltages	Core: 1.8/2.5/3.3 V (±10%); Output buffers: 1.4–3.63 V independently per VDDOx pin
Operating Temp	–40 °C to +85 °C; qualified for industrial embedded and telecom line card environments
Package	24-pin QFN, 4 × 4 mm, 0.5 mm pitch; exposed thermal pad for thermal management

Pinout & Package

SI5338L-B06100-GMR uses a 24-lead QFN package (4 × 4 mm, 0.5 mm pitch) with exposed thermal pad. Pin functions are defined per Skyworks Rev. 1.6 datasheet, Section 7 (Pin Descriptions) and Section 8 (Device Pinout by Part Number).

Pin/Terminal	Circuit Role	Design Meaning
IN1, IN2, IN5, IN6	Differential input pairs	Accept 5–710 MHz AC-coupled differential clocks; require external 100 Ω termination
IN3, IN4	Single-ended input pins	Support 5–200 MHz CMOS, 5–350 MHz SSTL/HSTL; VIH = 0.7×VDD, VIL = 0.3×VDD
CLK0A–CLK3B	Differential output pairs	Four independent output banks; each pair supports LVPECL/LVDS/HCSL/CML with per-bank VDDO
VDDO0–VDDO3	Output buffer supply pins	Independent 1.4–3.63 V supplies per output bank; enable mixed-voltage system interfacing
VDD	Core supply	1.8/2.5/3.3 V ±10%; powers PLL, MultiSynth, and control logic; PSRR optimized
SCL, SDA	I²C interface	SMBus-compatible 100/400 kHz interface; supports ClockBuilder Pro programming and runtime reconfiguration
INTR	Interrupt output	Open-drain status indicator for loss-of-lock (LOL) and loss-of-signal (LOS) alarms

Key Features

Feature	Design Value
MultiSynth™ synthesis	Four independent fractional-N synthesizers enabling simultaneous any-frequency outputs with 0 ppm precision
PCIe Gen 4 compliance	0.15–0.45 ps RMS jitter in common clock mode; validated per PCI Express Base Spec 4.0 rev. 0.5
Programmable spread spectrum	Configurable on any output: 0.5–5.0% deviation, 33–63 kHz modulation rate, down-spread default
Glitchless frequency tuning	Pin-controlled or I²C-based frequency increment/decrement in 1 ppm steps without output interruption
Per-output voltage control	Independent VDDOx pins allow LVDS (2.5 V), HCSL (1.8 V), and CMOS (3.3 V) outputs on same device
Alarm monitoring	Dedicated INTR pin reports loss-of-lock and loss-of-signal events with configurable debounce

Applications

PCIe Gen 4 Switch Timing	Ethernet Switch Clocking
Use Scenario: Providing synchronized 100 MHz reference clocks to multiple PCIe Gen 4 switch ASICs in a data center fabric. IC Role / Device Role / Timing Role: Quad-output clock generator delivering four low-jitter, phase-aligned clocks with independent SSC control per port. Use Value: Meets PCIe Gen 4 common clock TJ spec (≤33.6 ps pk-pk) and eliminates need for four discrete oscillators, reducing BOM count and layout area.	Use Scenario: Generating 125 MHz, 156.25 MHz, and 312.5 MHz clocks for 1 GbE/10 GbE PHYs and packet processors in enterprise switches. IC Role / Device Role / Timing Role: Any-frequency synthesizer replacing crystal oscillators and fanout buffers while supporting mixed signal formats (LVDS, HCSL, CMOS). Use Value: Enables single-device clock tree with <20 ps inter-output skew and programmable phase alignment for SerDes lane deskew.
Broadcast Video Sync	FPGA Processor Clocking
Use Scenario: Delivering SMPTE ST 2059-2–compliant 27 MHz, 74.25 MHz, and 148.5 MHz video reference clocks to encoder/decoder ASICs and frame synchronizers. IC Role / Device Role / Timing Role: Precision clock generator with sub-20 ps phase step resolution for genlock and frame-accurate timing alignment. Use Value: Achieves <1 ps RMS jitter at 148.5 MHz (LVDS), meeting broadcast-grade stability requirements without external jitter cleaners.	Use Scenario: Supplying 100 MHz system clock, 200 MHz DDR4 memory clock, 300 MHz transceiver reference, and 500 MHz debug clock to Xilinx Versal or Intel Agilex FPGA platforms. IC Role / Device Role / Timing Role: Configurable quad clock source supporting mixed-voltage I/O standards and independent frequency/phase tuning per domain. Use Value: Eliminates discrete clock buffers and synthesizers; enables dynamic reconfiguration of FPGA clock domains via I²C during runtime.

PCIe Gen 4 Switch Timing

Ethernet Switch Clocking

Use Scenario: Providing synchronized 100 MHz reference clocks to multiple PCIe Gen 4 switch ASICs in a data center fabric.

IC Role / Device Role / Timing Role: Quad-output clock generator delivering four low-jitter, phase-aligned clocks with independent SSC control per port.

Use Value: Meets PCIe Gen 4 common clock TJ spec (≤33.6 ps pk-pk) and eliminates need for four discrete oscillators, reducing BOM count and layout area.

Use Scenario: Generating 125 MHz, 156.25 MHz, and 312.5 MHz clocks for 1 GbE/10 GbE PHYs and packet processors in enterprise switches.

IC Role / Device Role / Timing Role: Any-frequency synthesizer replacing crystal oscillators and fanout buffers while supporting mixed signal formats (LVDS, HCSL, CMOS).

Use Value: Enables single-device clock tree with <20 ps inter-output skew and programmable phase alignment for SerDes lane deskew.

Broadcast Video Sync

FPGA Processor Clocking

Use Scenario: Delivering SMPTE ST 2059-2–compliant 27 MHz, 74.25 MHz, and 148.5 MHz video reference clocks to encoder/decoder ASICs and frame synchronizers.

IC Role / Device Role / Timing Role: Precision clock generator with sub-20 ps phase step resolution for genlock and frame-accurate timing alignment.

Use Value: Achieves <1 ps RMS jitter at 148.5 MHz (LVDS), meeting broadcast-grade stability requirements without external jitter cleaners.

Use Scenario: Supplying 100 MHz system clock, 200 MHz DDR4 memory clock, 300 MHz transceiver reference, and 500 MHz debug clock to Xilinx Versal or Intel Agilex FPGA platforms.

IC Role / Device Role / Timing Role: Configurable quad clock source supporting mixed-voltage I/O standards and independent frequency/phase tuning per domain.

Use Value: Eliminates discrete clock buffers and synthesizers; enables dynamic reconfiguration of FPGA clock domains via I²C during runtime.

Equivalent & Alternatives

The following parts are listed as comparable options for similar quad-output programmable clock generator applications.

Alternative Part	Technical Difference	Application Difference	Selection Advice
Si5332A-D06100-GM	Higher integration: 8 outputs, integrated EEPROM, lower jitter (0.35 ps RMS), supports JESD204B deterministic latency	Targeted at JESD204B ADC/DAC timing and multi-ASIC synchronization where deterministic delay matters	Choose Si5332A-D06100-GM when >4 outputs, deterministic latency, or factory pre-programming are required
ICS8430I-01T	Fixed-frequency, non-programmable; 4 LVDS outputs; 0.9 ps RMS jitter; no I²C interface or spread spectrum	Limited to static clock trees where frequency agility and runtime tuning are unnecessary	Choose ICS8430I-01T only for cost-sensitive, fixed-frequency applications with no requirement for reconfiguration or SSC

Compared with Si5332A-D06100-GM and ICS8430I-01T, the SI5338L-B06100-GMR uniquely balances field-programmability, PCIe Gen 4 compliance, and per-output voltage flexibility in a compact QFN-making it optimal for industrial and telecom systems requiring post-silicon clock tuning without added complexity or cost.

Availability

SI5338L-B06100-GMR is available at Aetrix Electronics and suitable for PCIe Gen 4 switch timing, Ethernet switch clocking, and broadcast video sync applications requiring stable component supply, long-term lifecycle support, and traceable sourcing.

Supply support for SI5338L-B06100-GMR includes scheduled delivery planning, volume procurement assistance, BOM continuity management, traceable sourcing, and lifecycle availability coordination for OEM customers, industrial embedded developers, connected-device designers, and electronics production programs.

Manufacturer

Skyworks Solutions is a global semiconductor company specializing in analog and mixed-signal connectivity solutions, with leadership in RF, timing, and power management ICs for infrastructure, automotive, and mobile markets.

The SI5338 family is designed for high-performance, multi-protocol clock generation in data center, telecom, and broadcast systems-delivering low-jitter, software-configurable timing with minimal board space and power consumption.

FAQ

What is the maximum output frequency supported by SI5338L-B06100-GMR?

The SI5338L-B06100-GMR supports up to 710 MHz on LVPECL/LVDS/CML outputs, 250 MHz on HCSL, and 350 MHz on SSTL/HSTL. However, only two unique frequencies above 350 MHz can be simultaneously generated (Fvco/4 and Fvco/6), as specified in the functional description section of the Skyworks datasheet Rev. 1.6. All outputs maintain ≤0.7 ps RMS jitter at these rates when using differential signaling and proper layout.

Does SI5338L-B06100-GMR support PCIe Gen 4 Separate Reference No Spread (SRNS) mode?

Yes, the SI5338L-B06100-GMR is compliant with PCIe Gen 4 SRNS requirements, achieving 0.11–0.32 ps RMS jitter under specified test conditions (PLL bandwidth 2–4 MHz, CDR = 10 MHz). This is verified in Table 12 of the Skyworks datasheet Rev. 1.6 and confirmed using the Skyworks PCIe Clock Jitter Tool. The device supports both common clock and SRNS topologies via register configuration.

Can SI5338L-B06100-GMR generate different output voltages on each channel?

Yes, SI5338L-B06100-GMR provides independent VDDO0–VDDO3 pins, allowing each of its four output banks to operate at 1.5 V, 1.8 V, 2.5 V, or 3.3 V. This enables direct interfacing with mixed-voltage devices-for example, LVDS outputs at 2.5 V, HCSL at 1.8 V, and CMOS at 3.3 V-all from a single SI5338L-B06100-GMR device without level shifters.

How is SI5338L-B06100-GMR programmed, and is external non-volatile memory required?

The SI5338L-B06100-GMR is programmed via its I²C/SMBus interface using Skyworks' ClockBuilder Pro software. It contains on-chip one-time-programmable (OTP) NVM that stores configuration; no external EEPROM is required. Factory programming or field updates are supported, and the device boots with preloaded settings within 2 ms after power-on reset.

What input reference sources does SI5338L-B06100-GMR accept?

The SI5338L-B06100-GMR accepts four types of input references: (1) 8–30 MHz fundamental-mode crystals on dedicated XTAL pins, (2) 5–200 MHz CMOS clocks on IN3/IN4, (3) 5–350 MHz SSTL/HSTL signals on IN3/IN4, and (4) 5–710 MHz differential inputs on IN1/IN2 or IN5/IN6. Input slew rate requirements (≥1.0 V/ns for CMOS, ≥0.3 V/ns for differential) must be met for optimal jitter performance.

SI5338L-B06100-GMR Specifications

Product attributes: Attribute value

Manufacturer:: Skyworks Solutions Inc.

Series:: MultiSynth™

Package/Case:: 24-VFQFN Exposed Pad

Packaging:: Tape & Reel (TR)

Product Status:: Active

Programmable:: Not Verified

PLL:: -

Main Purpose:: -

Input:: -

Output:: -

Number of Circuits:: -

Ratio - Input:Output:: -

Differential - Input:Output:: -

Frequency - Max:: -

Voltage - Supply:: -

Operating Temperature:: -

Mounting Type:: Surface Mount

Grade:: -

Qualification:: -

Supplier Device Package:: 24-QFN (4x4)

SI5338L-B06100-GMR FAQ

1.How can I place an order for SI5338L-B06100-GMR through Aetrix?

Please submit a Request for Quotation (RFQ) for SI5338L-B06100-GMR on Aetrix. Our sales agent will provide a competitive quotation and guide you through the order confirmation once you accept the terms.

2.Are the price and stock information for SI5338L-B06100-GMR reliable?

The price and inventory of SI5338L-B06100-GMR are updated periodically and may fluctuate due to market conditions. Stock and pricing data are typically refreshed every 24 hours. Quotation validity for SI5338L-B06100-GMR is usually 5 days.

3.What payment methods are accepted for SI5338L-B06100-GMR?

We accept Wire Transfer, PayPal, Credit Card, Western Union, MoneyGram, and Escrow for SI5338L-B06100-GMR transactions.

Note: Certain payment methods may incur a processing fee.

4.How is shipping managed for SI5338L-B06100-GMR?

SI5338L-B06100-GMR orders can be shipped via leading logistics carriers, including DHL, UPS, FedEx, TNT, or Registered Mail.

Once your SI5338L-B06100-GMR order is processed, you will receive an email with the shipment details and tracking number.

Note: Tracking information may take up to 24 hours to appear. Express delivery typically takes 3–5 business days.

5.How can I obtain technical support or documentation for SI5338L-B06100-GMR?

For technical support, including SI5338L-B06100-GMR datasheets, pinout diagrams, or application guidance, please contact our engineering support team. They can provide detailed documentation and assistance for your SI5338L-B06100-GMR requirements.

6.How does Aetrix verify that SI5338L-B06100-GMR is sourced from the original manufacturer or authorized distributors?

All SI5338L-B06100-GMR products on Aetrix are procured from qualified distributors and authorized channels. Our dedicated quality assurance team conducts strict verification, including traceability checks and, if necessary, third-party testing. This ensures that SI5338L-B06100-GMR meets industry standards.

7.What is the process for return or replacement of SI5338L-B06100-GMR?

All SI5338L-B06100-GMR units undergo pre-shipment inspection (PSI). If there is an issue with SI5338L-B06100-GMR, returns or replacements are accepted under the following conditions:

1.Quantity discrepancies, incorrect items, or visible external defects (such as breakage or corrosion), acknowledged by Aetrix.

2.The issue is reported within 90 days of delivery.

3.The SI5338L-B06100-GMR part is unused and in its original packaging.

Return procedure for SI5338L-B06100-GMR:

1.Submit a request within 90 days.

2.Obtain a Return Material Authorization (RMA) from Aetrix.

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