Skyworks Solutions Inc. SI5338M-B04369-GM

Overview

SI5338M-B04369-GM from Skyworks Solutions is an I²C-programmable quad clock generator with four independently configurable differential or single-ended outputs, 0.7 ps RMS typical phase jitter, PCIe Gen 1–4 Common Clock and Gen 3 SRNS compliance, and support for input references from 5 MHz to 710 MHz. It replaces up to four crystal oscillators in high-speed serial interface timing applications such as PCIe switch cards and 10 GbE line cards.

For engineers reviewing the SI5338M-B04369-GM datasheet, SI5338M-B04369-GM pinout, SI5338M-B04369-GM application, or SI5338M-B04369-GM equivalent, key selection considerations include its MultiSynth™ fractional-N synthesis architecture, per-output voltage control (1.5/1.8/2.5/3.3 V), independent phase/frequency adjustment (±45 ns / 1 ppm steps), and 24-pin 4×4 mm QFN package with integrated loss-of-lock and loss-of-signal monitoring.

Technical Context

The SI5338M-B04369-GM implements a two-stage PLL architecture: a high-stability integer-N Phase-Locked Loop (PLL) stage locks to one of six input sources (crystal, CMOS, SSTL/HSTL, or differential), followed by four independent MultiSynth™ fractional-N synthesis blocks-each driving one output pair (CLKxA/CLKxB). This enables true zero-ppm frequency accuracy across all four outputs simultaneously.

Each output driver supports LVPECL/LVDS/HCSL/CMOS/SSTL/HSTL formats with programmable output voltage (1.5 V to 3.3 V), spread-spectrum modulation (0.5–5.0% down-spread, 33–63 kHz), and glitchless frequency increment/decrement via dedicated pins or I²C. The device operates from a single 1.8/2.5/3.3 V core supply and delivers 45 mA typical core current at full load.

Key Specifications

Pinout & Package

SI5338M-B04369-GM uses a 24-pin, 4 × 4 mm QFN package with exposed thermal pad. Pin 1 is top-left (IN1), and pin 24 is bottom-right (GND). The package supports reflow soldering per JEDEC J-STD-020 and provides 37 °C/W junction-to-ambient thermal resistance in still air.

Key Features

Applications

Equivalent & Alternatives

The following parts are listed as comparable options for similar quad clock generator applications.

Compared with Si5332A-D06881-GM and ICS853S01AG-01, the SI5338M-B04369-GM uniquely balances field-programmability, multi-format output flexibility, and PCIe Gen 4 compliance in a compact QFN-making it optimal for systems requiring post-design clock tuning and mixed-voltage interface support.

Availability

SI5338M-B04369-GM is available at Aetrix Electronics and suitable for PCIe switch timing, 10 GbE line cards, broadcast video sync, and FPGA-based test equipment requiring stable component supply, long-term lifecycle assurance, and traceable sourcing.

Supply support for SI5338M-B04369-GM includes scheduled delivery planning, volume procurement assistance, BOM continuity management, traceable sourcing, and lifecycle availability coordination for OEM customers, industrial embedded developers, connected-device designers, and electronics production programs.

Manufacturer

Skyworks Solutions is a global leader in analog and mixed-signal semiconductors, specializing in RF, mobile, infrastructure, and timing solutions with over 30 years of RF and clocking innovation.

The Si5338 family was designed for high-performance, multi-protocol serial interface timing-including PCIe, Ethernet, Fibre Channel, and broadcast video-where low jitter, flexible synthesis, and small footprint are critical.

FAQ

What is the maximum output frequency supported by the SI5338M-B04369-GM?

The SI5338M-B04369-GM supports up to 710 MHz on LVPECL/LVDS/CML outputs, 350 MHz on SSTL/HSTL, 250 MHz on HCSL, and 200 MHz on CMOS. However, only two unique frequencies above 350 MHz can be generated simultaneously (Fvco/4 and Fvco/6), as defined by the internal VCO architecture. All frequencies are synthesized with zero-ppm precision using MultiSynth™ technology.

Does the SI5338M-B04369-GM support PCIe Gen 4 timing requirements?

Yes, the SI5338M-B04369-GM meets PCIe Gen 4 Common Clock specifications with 0.15–0.45 ps RMS jitter (10 kHz–50 MHz) and is explicitly listed as PCIe Gen 1/2/3/4 Common Clock and Gen 3 SRNS compliant in its official documentation. Its jitter performance is validated using the Skyworks PCIe Clock Jitter Tool and Intel Clock Jitter Tool v1.6.4.

Can the SI5338M-B04369-GM generate different output formats simultaneously?

Yes, the SI5338M-B04369-GM supports mixed output formats: for example, CLK0A/B as LVDS, CLK1A/B as HCSL, CLK2A/B as CMOS, and CLK3A/B as SSTL-all concurrently. Each output pair is independently configurable for format, frequency, voltage (via VDDOx), and termination, enabling direct interfacing with heterogeneous SoCs, FPGAs, and PHYs.

How is the SI5338M-B04369-GM programmed and configured?

The SI5338M-B04369-GM is programmed via an I²C/SMBus-compatible 2-wire interface (SCL/SDA) operating up to 400 kHz. Configuration is simplified using Skyworks' ClockBuilder Pro software, which generates register maps, validates settings, and exports configuration files. Pin-controlled frequency/phase adjustments are also supported for real-time tuning without host processor intervention.

What input reference options does the SI5338M-B04369-GM support?

The SI5338M-B04369-GM accepts six input reference types: external crystal (8–30 MHz), CMOS (5–200 MHz), SSTL/HSTL (5–350 MHz), and differential (5–710 MHz) on four dedicated input pairs (IN1/IN2, IN5/IN6) and two single-ended pins (IN3/IN4). Input detection includes loss-of-signal monitoring with 2.6–5 µs response time.