Skyworks Solutions Inc. SI5338M-B04369-GMR

Overview

SI5338M-B04369-GMR from Skyworks Solutions is an I²C-programmable quad clock generator with four independently configurable differential or single-ended outputs, 0.7 ps RMS typical phase jitter, PCIe Gen 1–4 Common Clock and Gen 3 SRNS compliance, and operation across –40 to +85 °C. It replaces up to four crystal oscillators in high-speed serial interface timing applications such as PCIe root complexes and FPGA-based compute platforms.

For engineers reviewing the SI5338M-B04369-GMR datasheet, SI5338M-B04369-GMR pinout, SI5338M-B04369-GMR application, or SI5338M-B04369-GMR equivalent, key selection criteria include its MultiSynth™-based any-frequency synthesis (0.16–710 MHz per output), independent output voltage support (1.5/1.8/2.5/3.3 V), spread-spectrum capability (0.5–5.0% down-spread), and 24-pin 4×4 mm QFN package with I²C/SMBus control.

Technical Context

The SI5338M-B04369-GMR implements a two-stage PLL architecture: a high-stability integer-N PLL (Stage 1) locks to one of six input references (crystal, CMOS, SSTL/HSTL, or differential), followed by four independent MultiSynth™ fractional-N synthesis blocks (Stage 2) generating each output. Each MultiSynth supports programmable initial phase offset (±45 ns), glitchless frequency increment/decrement (1 ppm steps), and <20 ps phase step resolution.

Input flexibility includes external crystal (8–30 MHz), CMOS (5–200 MHz), SSTL/HSTL (5–350 MHz), or differential (5–710 MHz); outputs support LVPECL/LVDS/HCSL/CMOS/SSTL/HSTL formats with per-driver supply voltage selection. The device integrates OTP NVM for factory programming and supports zero-delay mode via external feedback.

Key Specifications

Pinout & Package

SI5338M-B04369-GMR is housed in a 24-pin, 4 × 4 mm QFN package with exposed thermal pad. Pin assignments follow the standard Si5338 top-view layout: pins 1–24 include six input clocks (IN1–IN6), four differential output pairs (CLK0A/B through CLK3A/B), four VDDOx supplies (VDDO0–VDDO3), core VDD, SCL/SDA/I²C interface, INTR alarm output, and reserved ground (RSVD_GND).

Key Features

Applications

Equivalent & Alternatives

The following parts are listed as comparable options for similar quad clock generator applications.

Compared with Si5332A-D06881-GM and ICS853S02IAGLF, SI5338M-B04369-GMR delivers optimal balance of programmability, PCIe compliance, and industrial temperature support in a compact 4×4 mm footprint-making it ideal for field-upgradable timing in mid-range networking and compute platforms where flexibility and qualification matter more than absolute lowest jitter.

Availability

SI5338M-B04369-GMR is available at Aetrix Electronics and suitable for PCIe Gen 4 switch timing, FPGA clock distribution, and telecom line card synchronization requiring stable component supply, long-term lifecycle assurance, and traceable sourcing.

Supply support for SI5338M-B04369-GMR includes scheduled delivery planning, volume procurement assistance, BOM continuity management, traceable sourcing, and lifecycle availability coordination for OEM customers, industrial embedded developers, connected-device designers, and electronics production programs.

Manufacturer

Skyworks Solutions is a global semiconductor company specializing in analog and mixed-signal connectivity solutions for wireless, broadband, automotive, and industrial markets.

The Si5338 product line was designed for high-performance, software-configurable clock generation in systems demanding multi-frequency synthesis, low jitter, and flexible I/O voltage support-targeting PCIe, Ethernet, broadcast, and telecom infrastructure.

FAQ

What is the maximum output frequency supported by SI5338M-B04369-GMR?

The SI5338M-B04369-GMR supports up to 710 MHz on LVPECL/LVDS/CML outputs, 350 MHz on SSTL/HSTL, 250 MHz on HCSL, and 200 MHz on CMOS. However, only two unique frequencies above 350 MHz can be simultaneously generated (Fvco/4 and Fvco/6), as defined by the internal VCO architecture. All frequencies are synthesized with 0 ppm precision using MultiSynth™ technology.

Does SI5338M-B04369-GMR support PCIe Gen 4 Common Clock compliance?

Yes, SI5338M-B04369-GMR meets PCIe Gen 4 Common Clock jitter requirements with ≤0.45 ps RMS (1.5 MHz–50 MHz band) when configured per Skyworks' validated settings. This is confirmed in Table 12 of the datasheet and verified using the Skyworks PCIe Clock Jitter Tool. The device also satisfies Gen 3 SRNS and Gen 1/2 specifications out-of-the-box.

Can SI5338M-B04369-GMR operate with a 1.8 V core supply and 3.3 V output buffers?

Yes, SI5338M-B04369-GMR supports independent supply rails: the core VDD may be 1.8 V (1.71–1.98 V), while each VDDOx output buffer can be set to 1.5 V, 1.8 V, 2.5 V, or 3.3 V. This allows direct interfacing with mixed-voltage systems-for example, driving 3.3 V CMOS logic and 1.8 V FPGA I/O banks simultaneously without external level shifters.

How is SI5338M-B04369-GMR programmed and configured?

SI5338M-B04369-GMR is programmed via its I²C/SMBus-compatible serial interface (SCL/SDA pins) using Skyworks' ClockBuilder Pro software. Configuration includes frequency, format, voltage, spread spectrum, phase offset, and alarm thresholds. Factory-programmed OTP NVM retains settings across power cycles; no external EEPROM is required.

What is the thermal performance of SI5338M-B04369-GMR in continuous operation?

SI5338M-B04369-GMR has a junction-to-ambient thermal resistance (θJA) of 37 °C/W under still-air conditions. At typical 45 mA core current and full output load, power dissipation remains below 150 mW, keeping junction temperature well within the 150 °C absolute maximum-even at +85 °C ambient. The exposed thermal pad must be soldered to a PCB copper plane for optimal heat transfer.