Skyworks Solutions Inc. SI5338M-B04370-GM

Overview

SI5338M-B04370-GM from Skyworks Solutions is a quad-output, I²C-programmable clock generator with MultiSynth™ frequency synthesis. It delivers four independent differential or single-ended clocks (up to 710 MHz LVPECL/LVDS, 350 MHz SSTL/HSTL), 0.7 ps RMS typical phase jitter, PCIe Gen 1–4 Common Clock and Gen 3 SRNS compliance, and operates from 1.8/2.5/3.3 V core supply in a 4 × 4 mm 24-QFN package. It replaces multiple crystal oscillators in high-speed serial interface timing.

For engineers reviewing the SI5338M-B04370-GM datasheet, SI5338M-B04370-GM pinout, SI5338M-B04370-GM application, or SI5338M-B04370-GM equivalent, key selection criteria include PCIe Gen 4 jitter compliance (0.15–0.45 ps RMS), independent output voltage per driver (1.5/1.8/2.5/3.3 V), programmable phase/frequency step resolution (<20 ps / 1 ppm), and support for external crystal (8–30 MHz) or wideband differential inputs (5–710 MHz).

Technical Context

The SI5338M-B04370-GM implements a two-stage PLL architecture: a high-stability reference PLL (loop bandwidth 1.6 MHz) followed by four independent MultiSynth™ fractional-N synthesizers. Each output stage supports integer or fractional mode operation, enabling true zero-ppm accuracy across all four outputs while maintaining sub-1 ps RMS jitter performance.

It features configurable input stage selection (crystal, CMOS, SSTL/HSTL, or differential), independent output format assignment (LVPECL/LVDS/HCSL/CMOS/SSTL/HSTL), and real-time glitchless frequency adjustment via dedicated PINC/FDEC pins or I²C. Loss-of-lock and loss-of-signal alarms provide system-level fault monitoring.

Key Specifications

Pinout & Package

SI5338M-B04370-GM uses a 24-pin QFN package (4 mm × 4 mm, 0.5 mm pitch) with exposed thermal pad. Pin assignments are fixed per Si5338 family: IN1/IN2 (diff clk 1), IN3/IN4 (SE clk), IN5/IN6 (diff clk 2), CLK0A/CLK0B through CLK3A/CLK3B (four differential outputs), VDDO0–VDDO3 (independent output supply pins), VDD (core supply), SCL/SDA (I²C), INTR (interrupt), and RSVD_GND.

Key Features

Applications

Equivalent & Alternatives

The following parts are listed as comparable options for similar quad-output programmable clock generator applications.

Compared with Si5332A-D06880-GM and ICS854S01IAGLF, the SI5338M-B04370-GM offers optimal balance of programmability, PCIe Gen 4 compliance, and mixed-signal output flexibility - making it ideal for FPGA-based platforms and multi-standard serial interface timing where field-upgradable clocking is required.

Availability

SI5338M-B04370-GM is available at Aetrix Electronics and suitable for PCIe Gen 4 switch timing, Ethernet switching/routing, and broadcast video equipment requiring stable component supply, long-term lifecycle support, and traceable sourcing.

Supply support for SI5338M-B04370-GM includes scheduled delivery planning, volume procurement assistance, BOM continuity management, traceable sourcing, and lifecycle availability coordination for OEM customers, industrial embedded developers, connected-device designers, and electronics production programs.

Manufacturer

Skyworks Solutions is a global leader in analog and mixed-signal semiconductors, specializing in RF, timing, and connectivity solutions for infrastructure, automotive, and mobile markets.

The SI5338M-B04370-GM belongs to Skyworks' Si5338 family of any-frequency clock generators, designed specifically for high-speed serial interface timing in datacenter, telecom, and broadcast systems requiring PCIe, Ethernet, and SMPTE-compliant jitter performance.

FAQ

What is the maximum output frequency supported by the SI5338M-B04370-GM in LVPECL format?

The SI5338M-B04370-GM supports LVPECL output frequencies up to 710 MHz. This capability is confirmed in Table 6 of the official datasheet, which specifies "LVPECL, LVDS, CML: 0.16–350 MHz; 367–473.33 MHz; 550–710 MHz" with appropriate VDDO and load conditions. Operation above 350 MHz requires use of Fvco/4 or Fvco/6 synthesis paths, and only two unique frequencies >350 MHz may be active simultaneously.

Does the SI5338M-B04370-GM support PCIe Gen 4 Common Clock jitter requirements?

Yes, the SI5338M-B04370-GM meets PCIe Gen 4 Common Clock jitter specifications. Table 12 confirms RMS jitter of 0.15–0.45 ps (10 kHz–50 MHz band) for 100 MHz HCSL outputs under specified test conditions. The device is explicitly listed in the Features section as "PCIe Gen 1/2/3/4 Common Clock and Gen 3 SRNS compliant", and its PLL loop bandwidth (1.6 MHz) and MultiSynth™ architecture are optimized for this standard.

Can the SI5338M-B04370-GM generate four different output voltages simultaneously?

Yes, the SI5338M-B04370-GM supports independent output supply voltages per driver: VDDO0 powers CLK0A/B, VDDO1 powers CLK1A/B, VDDO2 powers CLK2A/B, and VDDO3 powers CLK3A/B. Each can be set to 1.5 V, 1.8 V, 2.5 V, or 3.3 V, enabling simultaneous clocking of mixed-voltage devices such as 1.8 V FPGAs, 2.5 V SerDes, and 3.3 V legacy peripherals - all from a single SI5338M-B04370-GM.

How is the SI5338M-B04370-GM programmed, and is external nonvolatile memory required?

The SI5338M-B04370-GM is programmed via its I²C/SMBus-compatible interface using Skyworks' ClockBuilder Pro software. It contains on-chip one-time-programmable (OTP) NVM that stores configuration settings, eliminating the need for external memory. Factory-programmed devices power up with valid clocks within 2 ms (tRDY), and field updates can be performed dynamically without reset via I²C writes to RAM registers.

What input reference options does the SI5338M-B04370-GM support?

The SI5338M-B04370-GM supports four input reference types: (1) external crystal (8–30 MHz), (2) single-ended CMOS clock (5–200 MHz on IN3/IN4), (3) SSTL/HSTL clock (5–350 MHz), and (4) differential clock (5–710 MHz on IN1/IN2 or IN5/IN6). All inputs are automatically detected and conditioned by the internal input stage, with configurable termination and slew-rate optimization for best jitter performance.