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Home > Products > Integrated Circuits (ICs) > Clock/Timing > Application Specific Clock/Timing

Skyworks Solutions Inc. SI5338M-B04370-GMR

Name: SI5338M-B04370-GMR
Brand: Skyworks Solutions Inc.
SKU: SI5338M-B04370-GMR
Price: 2.40 USD
Availability: InStock
Rating: 5 (2 reviews)

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Part No.:: SI5338M-B04370-GMR

Manufacturer:: Skyworks Solutions Inc.

Category:: Application Specific Clock/Timing

Package:: 24-VFQFN Exposed Pad

Datasheet:: SI5338M-B04370-GMR.pdf

Description:: I2C CONTROL, 4-OUTPUT, ANY FREQU

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Product details

Overview

SI5338M-B04370-GMR from Skyworks Solutions is an I²C-programmable quad clock generator with four independently configurable differential or single-ended outputs, 0.7 ps RMS typical phase jitter, PCIe Gen 1–4 Common Clock and Gen 3 SRNS compliance, and operation from 1.8/2.5/3.3 V core supply in a 4 × 4 mm 24-QFN package. It replaces up to four crystal oscillators in Ethernet switch/router, FPGA clocking, and broadcast video timing systems.

For engineers reviewing the SI5338M-B04370-GMR datasheet, SI5338M-B04370-GMR pinout, SI5338M-B04370-GMR application, or SI5338M-B04370-GMR equivalent, key selection criteria include its MultiSynth™-based any-frequency synthesis (0.16–710 MHz per output), independent output voltage per driver (1.5/1.8/2.5/3.3 V), spread-spectrum capability (0.5–5.0% down-spread), and I²C/SMBus programmability with ClockBuilder Pro support.

Technical Context

The SI5338M-B04370-GMR implements a two-stage PLL architecture: a high-stability reference stage (with crystal or external clock input) followed by four independent MultiSynth™ fractional-N synthesis blocks, each feeding a configurable output driver. This enables true zero-ppm frequency accuracy across all outputs without requiring integer-related frequencies.

Each output supports LVPECL/LVDS/HCSL/CMOS/SSTL/HSTL formats with independent supply voltage (VDDOx), programmable phase offset (±45 ns, <20 ps step), and glitchless frequency increment/decrement (1 ppm steps). Input flexibility includes differential (5–710 MHz), CMOS (5–200 MHz), SSTL/HSTL (5–350 MHz), and 8–30 MHz crystal references.

Key Specifications

Parameter	Value and Actual Design Meaning
Phase Jitter (RMS)	0.7 ps typical (12 kHz–20 MHz); meets PCIe Gen 3 SRNS and Gen 4 common clock jitter requirements
Output Frequency Range	0.16–710 MHz per channel; supports LVPECL/LVDS up to 710 MHz, HCSL up to 250 MHz, CMOS up to 200 MHz
Input Reference Support	Crystal (8–30 MHz), CMOS (5–200 MHz), SSTL/HSTL (5–350 MHz), differential (5–710 MHz)
Supply Voltages	Core: 1.8/2.5/3.3 V ±10%; Output buffers: independently configurable 1.5/1.8/2.5/3.3 V
Package	24-pin QFN, 4 × 4 mm, 0.5 mm pitch; RoHS-compliant, halogen-free, MSL3
Operating Temperature	–40 °C to +85 °C ambient; validated for industrial and telecom line card environments
Power Consumption	45 mA typical core current at 100 MHz on all outputs and 25 MHz reference clock

Pinout & Package

SI5338M-B04370-GMR is housed in a 24-lead, 4 × 4 mm QFN package with exposed thermal pad. Pin assignments are fixed per the Si5338 family: IN1/IN2 (differential ref 1), IN3/IN4 (single-ended ref), IN5/IN6 (differential ref 2), CLK0A/CLK0B through CLK3A/CLK3B (four differential output pairs), VDDO0–VDDO3 (independent output supply pins), VDD (core supply), SCL/SDA (I²C interface), INTR (interrupt output), and RSVD_GND (reserved ground).

Pin/Terminal	Circuit Role	Design Meaning
CLK0A / CLK0B	Differential Output Pair 0	LVPECL/LVDS/HCSL/CML-capable; independently configured frequency, format, and VDDO0 voltage
CLK1A / CLK1B	Differential Output Pair 1	Same configurability as CLK0; supports integer/fractional synthesis with <20 ps phase step resolution
CLK2A / CLK2B	Differential Output Pair 2	Configurable for PCIe Gen 4 common clock (100 MHz HCSL) or broadcast video timing (148.5 MHz LVDS)
CLK3A / CLK3B	Differential Output Pair 3	Supports spread-spectrum modulation (33–63 kHz rate, 0.5–5.0% spread) for EMI reduction
IN1 / IN2	Differential Reference Input 1	Accepts 5–710 MHz AC-coupled differential clock; internal 100 Ω termination enabled
IN3 / IN4	Single-Ended Reference Input	CMOS-compatible; 5–200 MHz range; VIH = 0.7×VDD, VIL = 0.3×VDD
SCL / SDA	I²C/SMBus Interface	Standard 2-wire serial interface for configuration; supports ClockBuilder Pro programming
INTR	Interrupt Output	Open-drain status signal indicating loss-of-lock or loss-of-signal events
VDDO0–VDDO3	Output Buffer Supplies	Independent 1.5/1.8/2.5/3.3 V supplies per output pair; decoupling required per pin
VDD	Core Supply	Single 1.8/2.5/3.3 V supply for PLL and logic; PSRR optimized for noise immunity

Key Features

Feature	Design Value
MultiSynth™ Any-Frequency Synthesis	Four independent outputs with 0 ppm precision across 0.16–710 MHz; eliminates need for multiple XO/VCXO components
PCIe Gen 1–4 Compliance	Validated for Common Clock (Gen 1/2/3/4) and Gen 3 Separate Reference No Spread (SRNS) modes per specification
Independent Output Voltage Control	VDDO0–VDDO3 pins enable mixed-voltage system interfacing (e.g., 1.8 V FPGA core + 3.3 V legacy PHY)
Glitchless Frequency Adjustment	1 ppm step size via PINC/FDEC pins or I²C; no output interruption during dynamic frequency changes
Programmable Phase Offset	±45 ns range with <20 ps resolution per output; enables precise skew management in multi-lane SerDes
Spread Spectrum Clocking (SSC)	Configurable on any output: 5–350 MHz frequency range, 0.5–5.0% spread depth, 33–63 kHz modulation rate

Applications

Ethernet Switch/Router Timing	PCIe Gen 3/4 Clocking
Use Scenario: High-density 10 GbE/25 GbE switch fabric requiring synchronized clocks across multiple PHYs and packet processors. IC Role / Device Role / Timing Role: Quad-output clock generator providing independent 156.25 MHz (XAUI), 125 MHz (GbE), 100 MHz (PCIe), and 25 MHz (management) clocks with sub-1 ps jitter. Use Value: Eliminates four discrete oscillators while maintaining PCIe Gen 3 SRNS compliance and <0.7 ps RMS jitter for deterministic latency.	Use Scenario: Server motherboard with dual x16 PCIe Gen 4 slots, CPU interconnect, and NVMe storage controller. IC Role / Device Role / Timing Role: Single-chip source of 100 MHz common clock (HCSL) for root complex and endpoints, plus auxiliary clocks for USB 3.2 and SATA. Use Value: Meets PCIe Gen 4 common clock jitter spec (0.15–0.45 ps RMS) with one device, reducing BOM count and layout complexity.
Broadcast Video/Audio Timing	FPGA & Processor Clocking
Use Scenario: SMPTE ST 2110 IP media gateway requiring genlock-capable 27 MHz, 74.25 MHz, and 148.5 MHz video clocks with frame-accurate phase alignment. IC Role / Device Role / Timing Role: Programmable quad generator delivering three video clocks plus a 10 MHz reference for ADC/DAC synchronization. Use Value: Achieves <20 ps phase step resolution and ±45 ns programmable offset to align video/audio sample clocks across distributed nodes.	Use Scenario: Industrial FPGA-based motion controller needing separate clocks for ARM Cortex-A9 (200 MHz), DDR3 memory (400 MHz), SERDES transceivers (312.5 MHz), and analog front-end (10 MHz). IC Role / Device Role / Timing Role: Configurable clock source supporting mixed-signal domain partitioning with independent voltage and format per output. Use Value: Enables single-supply core (3.3 V) with 1.8 V VDDO for DDR3, 2.5 V for SERDES, and 3.3 V for MCU-reducing power rail count.

Ethernet Switch/Router Timing

PCIe Gen 3/4 Clocking

Use Scenario: High-density 10 GbE/25 GbE switch fabric requiring synchronized clocks across multiple PHYs and packet processors.

IC Role / Device Role / Timing Role: Quad-output clock generator providing independent 156.25 MHz (XAUI), 125 MHz (GbE), 100 MHz (PCIe), and 25 MHz (management) clocks with sub-1 ps jitter.

Use Value: Eliminates four discrete oscillators while maintaining PCIe Gen 3 SRNS compliance and <0.7 ps RMS jitter for deterministic latency.

Use Scenario: Server motherboard with dual x16 PCIe Gen 4 slots, CPU interconnect, and NVMe storage controller.

IC Role / Device Role / Timing Role: Single-chip source of 100 MHz common clock (HCSL) for root complex and endpoints, plus auxiliary clocks for USB 3.2 and SATA.

Use Value: Meets PCIe Gen 4 common clock jitter spec (0.15–0.45 ps RMS) with one device, reducing BOM count and layout complexity.

Broadcast Video/Audio Timing

FPGA & Processor Clocking

Use Scenario: SMPTE ST 2110 IP media gateway requiring genlock-capable 27 MHz, 74.25 MHz, and 148.5 MHz video clocks with frame-accurate phase alignment.

IC Role / Device Role / Timing Role: Programmable quad generator delivering three video clocks plus a 10 MHz reference for ADC/DAC synchronization.

Use Value: Achieves <20 ps phase step resolution and ±45 ns programmable offset to align video/audio sample clocks across distributed nodes.

Use Scenario: Industrial FPGA-based motion controller needing separate clocks for ARM Cortex-A9 (200 MHz), DDR3 memory (400 MHz), SERDES transceivers (312.5 MHz), and analog front-end (10 MHz).

IC Role / Device Role / Timing Role: Configurable clock source supporting mixed-signal domain partitioning with independent voltage and format per output.

Use Value: Enables single-supply core (3.3 V) with 1.8 V VDDO for DDR3, 2.5 V for SERDES, and 3.3 V for MCU-reducing power rail count.

Equivalent & Alternatives

The following parts are listed as comparable options for similar quad clock generator applications.

Alternative Part	Technical Difference	Application Difference	Selection Advice
Si5332A-D06880-GM	Higher integration: 8 outputs, lower jitter (0.35 ps RMS), integrated crystal option; larger 5 × 5 mm 32-QFN package	Targets high-port-count switches and AI accelerators requiring >4 clocks; not drop-in compatible due to pin count and footprint	Select when >4 outputs or sub-0.5 ps jitter is required; verify PCB redesign for 32-QFN and updated ClockBuilder Pro configuration
ICS853S01AGI-01LFT	Fixed-function 4-output LVDS generator; no I²C programming; 1.2 ps RMS jitter; 3.3 V only; 32-pin TQFP	Cost-sensitive, static-clock applications (e.g., legacy telecom line cards); lacks frequency agility or spread spectrum	Choose for simple, unchanging clock trees where programmability adds no value; requires full layout change due to TQFP vs QFN

Compared with Si5332A-D06880-GM and ICS853S01AGI-01LFT, SI5338M-B04370-GMR uniquely balances field-programmability, PCIe Gen 4 readiness, and compact 24-QFN packaging-making it optimal for space-constrained, multi-standard designs where clock requirements may evolve post-deployment.

Availability

SI5338M-B04370-GMR is available at Aetrix Electronics and suitable for Ethernet switch/router timing, PCIe Gen 4 clocking, and broadcast video/audio timing applications requiring stable component supply, long-term lifecycle support, and guaranteed traceable sourcing.

Supply support for SI5338M-B04370-GMR includes scheduled delivery planning, volume procurement assistance, BOM continuity management, traceable sourcing, and lifecycle availability coordination for OEM customers, industrial embedded developers, connected-device designers, and electronics production programs.

Manufacturer

Skyworks Solutions is a global semiconductor company specializing in analog and mixed-signal connectivity solutions for wireless, broadband, automotive, and industrial markets.

The Si5338 product line delivers programmable, low-jitter clock generation for high-speed serial interfaces-including PCIe, Ethernet, and broadcast video-enabling flexible, future-proof timing architectures in space-constrained systems.

FAQ

What is the maximum output frequency supported by SI5338M-B04370-GMR in LVPECL mode?

The SI5338M-B04370-GMR supports up to 710 MHz in LVPECL mode per output, as confirmed in Table 6 of the official Skyworks datasheet Rev. 1.6. This applies when using differential outputs with appropriate termination and layout practices to maintain signal integrity and jitter performance. The device achieves this using its MultiSynth™ fractional-N synthesis engine with VCO frequencies up to ~4.2 GHz.

Does SI5338M-B04370-GMR support PCIe Gen 4 Common Clock compliance?

Yes, SI5338M-B04370-GMR is explicitly validated for PCIe Gen 4 Common Clock compliance, with measured RMS jitter of 0.15–0.45 ps (10 kHz–50 MHz) per Table 12 in the Skyworks datasheet Rev. 1.6. It meets the PCI-SIG Base Specification 4.0 rev. 0.5 requirements when configured in 100 MHz HCSL mode with appropriate PLL bandwidth (2–4 or 2–5 MHz) and CDR settings.

Can SI5338M-B04370-GMR generate four different output frequencies simultaneously?

Yes, SI5338M-B04370-GMR can synthesize four completely independent output frequencies simultaneously-each with its own MultiSynth™ block, format, voltage, and phase offset. The datasheet confirms "any frequency on each of the device's four output drivers" with 0 ppm precision, enabled by patented MultiSynth™ technology and independent R/M/N dividers per channel.

What is the function of the INTR pin on SI5338M-B04370-GMR?

The INTR pin on SI5338M-B04370-GMR is an open-drain interrupt output that asserts low to indicate loss-of-lock (LOL) or loss-of-signal (LOS) conditions detected by the PLL or input monitoring circuitry. Its behavior is defined in Section 3.6 ("Status Indicators") and Table 7 of the Skyworks datasheet Rev. 1.6, and it supports system-level fault detection without requiring continuous I²C polling.

Is ClockBuilder Pro software required to configure SI5338M-B04370-GMR?

No, ClockBuilder Pro is optional but strongly recommended for SI5338M-B04370-GMR configuration-it simplifies register setup, validates timing constraints, and generates I²C initialization code. However, the device can be programmed directly via its I²C/SMBus interface using custom firmware, as detailed in Sections 5 and 6 of the Skyworks datasheet Rev. 1.6. All registers are fully documented and accessible.

SI5338M-B04370-GMR Specifications

Product attributes: Attribute value

Manufacturer:: Skyworks Solutions Inc.

Series:: MultiSynth™

Package/Case:: 24-VFQFN Exposed Pad

Packaging:: Tape & Reel (TR)

Product Status:: Active

Programmable:: Not Verified

PLL:: -

Main Purpose:: -

Input:: -

Output:: -

Number of Circuits:: -

Ratio - Input:Output:: -

Differential - Input:Output:: -

Frequency - Max:: -

Voltage - Supply:: -

Operating Temperature:: -

Mounting Type:: Surface Mount

Grade:: -

Qualification:: -

Supplier Device Package:: 24-QFN (4x4)

SI5338M-B04370-GMR FAQ

1.How can I place an order for SI5338M-B04370-GMR through Aetrix?

Please submit a Request for Quotation (RFQ) for SI5338M-B04370-GMR on Aetrix. Our sales agent will provide a competitive quotation and guide you through the order confirmation once you accept the terms.

2.Are the price and stock information for SI5338M-B04370-GMR reliable?

The price and inventory of SI5338M-B04370-GMR are updated periodically and may fluctuate due to market conditions. Stock and pricing data are typically refreshed every 24 hours. Quotation validity for SI5338M-B04370-GMR is usually 5 days.

3.What payment methods are accepted for SI5338M-B04370-GMR?

We accept Wire Transfer, PayPal, Credit Card, Western Union, MoneyGram, and Escrow for SI5338M-B04370-GMR transactions.

Note: Certain payment methods may incur a processing fee.

4.How is shipping managed for SI5338M-B04370-GMR?

SI5338M-B04370-GMR orders can be shipped via leading logistics carriers, including DHL, UPS, FedEx, TNT, or Registered Mail.

Once your SI5338M-B04370-GMR order is processed, you will receive an email with the shipment details and tracking number.

Note: Tracking information may take up to 24 hours to appear. Express delivery typically takes 3–5 business days.

5.How can I obtain technical support or documentation for SI5338M-B04370-GMR?

For technical support, including SI5338M-B04370-GMR datasheets, pinout diagrams, or application guidance, please contact our engineering support team. They can provide detailed documentation and assistance for your SI5338M-B04370-GMR requirements.

6.How does Aetrix verify that SI5338M-B04370-GMR is sourced from the original manufacturer or authorized distributors?

All SI5338M-B04370-GMR products on Aetrix are procured from qualified distributors and authorized channels. Our dedicated quality assurance team conducts strict verification, including traceability checks and, if necessary, third-party testing. This ensures that SI5338M-B04370-GMR meets industry standards.

7.What is the process for return or replacement of SI5338M-B04370-GMR?

All SI5338M-B04370-GMR units undergo pre-shipment inspection (PSI). If there is an issue with SI5338M-B04370-GMR, returns or replacements are accepted under the following conditions:

1.Quantity discrepancies, incorrect items, or visible external defects (such as breakage or corrosion), acknowledged by Aetrix.

2.The issue is reported within 90 days of delivery.

3.The SI5338M-B04370-GMR part is unused and in its original packaging.

Return procedure for SI5338M-B04370-GMR:

1.Submit a request within 90 days.

2.Obtain a Return Material Authorization (RMA) from Aetrix.

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