Skyworks Solutions Inc. SI5338M-B04372-GM

Overview

SI5338M-B04372-GM from Skyworks Solutions is a quad-output, I²C-programmable clock generator with MultiSynth™ frequency synthesis. It delivers four independent, any-frequency outputs (0.16–710 MHz), supports LVPECL/LVDS/HCSL/CMOS/SSTL/HSTL formats, achieves 0.7 ps RMS phase jitter, and operates from 1.8/2.5/3.3 V core supply in PCIe Gen 1–4 timing applications.

For engineers reviewing the SI5338M-B04372-GM datasheet, SI5338M-B04372-GM pinout, SI5338M-B04372-GM application, or SI5338M-B04372-GM equivalent, key selection criteria include PCIe Gen 4 SRNS compliance, independent per-output voltage control (1.5–3.3 V), programmable phase/frequency adjustment (±45 ns / 1 ppm steps), and 24-pin 4×4 mm QFN package compatibility.

Technical Context

The SI5338M-B04372-GM integrates a dual-stage PLL architecture: a high-performance integer-N PLL for low-noise reference multiplication and four independent MultiSynth™ fractional-N synthesis blocks per output. Each output stage features configurable drive strength, format, and supply voltage, enabling simultaneous generation of non-integer-related frequencies across mixed signal standards.

It accepts six input references - differential (5–710 MHz), single-ended CMOS (5–200 MHz), SSTL/HSTL (5–350 MHz), or 8–30 MHz crystal - and supports external feedback for zero-delay operation. Loss-of-lock and loss-of-signal alarms provide real-time monitoring for system reliability in telecom and data center timing systems.

Key Specifications

Pinout & Package

SI5338M-B04372-GM is housed in a 24-pin, 4 × 4 mm QFN package with exposed thermal pad (pin 24). Pin assignments follow Skyworks' standardized Si5338 layout: IN1/IN2 (differential ref 1), IN3/IN4 (single-ended ref), IN5/IN6 (differential ref 2), CLK0A/CLK0B through CLK3A/CLK3B (four differential output pairs), VDDO0–VDDO3 (independent output supply pins), VDD (core supply), SCL/SDA/INTR (I²C control), and GND/RSVD_GND.

Key Features

Applications

Equivalent & Alternatives

The following parts are listed as comparable options for similar quad-output clock generator applications.

Compared with Si5338A-B04372-GM, SI5338M-B04372-GM offers factory-programmed PCIe Gen 4 timing; compared with ICS85411AGI-01LFT, it provides full programmability, lower jitter, and multi-standard output flexibility at higher design effort cost.

Availability

SI5338M-B04372-GM is available at Aetrix Electronics and suitable for PCIe Gen 4 server motherboards, 10 GbE switching platforms, broadcast video infrastructure, and FPGA-based acceleration cards requiring stable component supply and guaranteed timing performance.

Supply support for SI5338M-B04372-GM includes scheduled delivery planning, volume procurement assistance, BOM continuity management, traceable sourcing, and lifecycle availability coordination for OEM customers, industrial embedded developers, connected-device designers, and electronics production programs.

Manufacturer

Skyworks Solutions is a global leader in analog semiconductors, specializing in RF, timing, and precision analog solutions for communications, automotive, and industrial markets.

The Si5338 product line was designed to replace multiple discrete oscillators and clock buffers with a single, software-configurable timing IC for high-speed digital systems demanding ultra-low jitter and flexible frequency synthesis.

FAQ

What is the default factory configuration of the SI5338M-B04372-GM?

The SI5338M-B04372-GM ships with a pre-programmed configuration optimized for PCIe Gen 4 common clock and SRNS operation: four 100 MHz HCSL outputs, 1.8 V VDDO, and 3.3 V VDD core. This enables immediate plug-and-play use without initial ClockBuilder Pro setup, unlike the base Si5338A variant. The configuration is stored in one-time-programmable (OTP) memory and can be reprogrammed via I²C if needed.

Does the SI5338M-B04372-GM support spread spectrum clocking (SSC) on all outputs?

Yes, the SI5338M-B04372-GM supports independent spread spectrum clocking on any output, with user-selectable spread (0.5–5.0%), modulation rate (33–63 kHz), and direction (down-spread or center-spread). This feature is implemented per-output in hardware and does not require external components. For PCIe Gen 4 compliance, SSC must be disabled on the primary reference output, but can remain active on auxiliary clocks for EMI reduction elsewhere in the system.

How does the SI5338M-B04372-GM achieve 0.7 ps RMS phase jitter?

The SI5338M-B04372-GM achieves 0.7 ps RMS phase jitter through its patented MultiSynth™ architecture, low-noise VCO design, and optimized PLL loop bandwidth (1.6 MHz typical). Jitter performance is validated using differential LVDS/HCSL outputs with low-noise 25 MHz crystal reference and measured per JEDEC 65. Single-ended outputs may increase jitter; configurations requiring <3 ps RMS with CMOS should be validated with Skyworks' PCIe Clock Jitter Tool.

Can the SI5338M-B04372-GM generate four different frequencies simultaneously?

Yes, the SI5338M-B04372-GM synthesizes four fully independent frequencies simultaneously - for example, 100 MHz (PCIe), 125 MHz (GbE), 156.25 MHz (10GbE), and 270 MHz (video) - each with independent format, voltage, phase, and spread spectrum settings. The device uses four separate MultiSynth™ engines, allowing non-integer-related outputs without shared dividers or frequency constraints beyond the 5–710 MHz range per channel.

What is the purpose of the INTR pin on the SI5338M-B04372-GM?

The INTR pin on the SI5338M-B04372-GM is an open-drain interrupt output that asserts low upon detection of loss-of-lock (LOL) or loss-of-signal (LOS) conditions. It enables real-time system monitoring and fault response - for example, triggering firmware-initiated clock source failover or logging timing anomalies. The interrupt status is also readable via I²C register 0x000F, allowing software polling as an alternative to hardware interrupt handling.