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Home > Products > Integrated Circuits (ICs) > Clock/Timing > Application Specific Clock/Timing

Skyworks Solutions Inc. SI5338M-B04373-GM

Name: SI5338M-B04373-GM
Brand: Skyworks Solutions Inc.
SKU: SI5338M-B04373-GM
Price: 2.40 USD
Availability: InStock
Rating: 5 (2 reviews)

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Part No.:: SI5338M-B04373-GM

Manufacturer:: Skyworks Solutions Inc.

Category:: Application Specific Clock/Timing

Package:: 24-VFQFN Exposed Pad

Datasheet:: SI5338M-B04373-GM.pdf

Description:: I2C CONTROL, 4-OUTPUT, ANY FREQU

Quantity:: RFQ Add To RFQ list

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Product details

Overview

SI5338M-B04373-GM from Skyworks Solutions is an I²C-programmable quad clock generator with four independent differential output drivers, 0.7 ps RMS typical phase jitter, PCIe Gen 1–4 Common Clock and Gen 3 SRNS compliance, and support for LVPECL/LVDS/HCSL/CMOS/SSTL/HSTL output formats across 0.16–710 MHz. It replaces up to four crystal oscillators in high-speed serial interface timing applications.

For engineers reviewing the SI5338M-B04373-GM datasheet, SI5338M-B04373-GM pinout, SI5338M-B04373-GM application, or SI5338M-B04373-GM equivalent, key selection criteria include PCIe Gen 4 jitter compliance (0.15–0.45 ps RMS), independent per-output voltage control (1.5/1.8/2.5/3.3 V), MultiSynth™ fractional synthesis resolution (1 ppb), and 24-QFN package compatibility with space-constrained FPGA/ASIC clock trees.

Technical Context

The SI5338M-B04373-GM implements a two-stage PLL architecture: a high-stability input stage with programmable R-divider followed by four independent MultiSynth™ synthesis blocks (M0–M3), each feeding a configurable output driver. Each MultiSynth supports integer or fractional-N division with <20 ps phase step accuracy and 1 ppm frequency increment/decrement capability.

It accepts six input sources - dual differential (IN1/IN2, IN5/IN6), dual single-ended (IN3/IN4), and external crystal (IN1/IN2) - with flexible reference handling including external feedback for zero-delay mode. Output drivers are independently configurable for format, voltage, slew rate, and spread-spectrum modulation (0.5–5.0% spread, 33–63 kHz rate).

Key Specifications

Parameter	Value and Actual Design Meaning
Phase Jitter (RMS)	0.7 ps typ (12 kHz–20 MHz); meets PCIe Gen 4 common clock jitter spec (≤0.45 ps RMS)
Output Count & Type	4 differential outputs (CLK0A/B–CLK3A/B); supports LVPECL/LVDS/HCSL/CML/SSTL/HSTL
Frequency Range	0.16–710 MHz per output; up to two >350 MHz frequencies simultaneously (Fvco/4, Fvco/6)
Supply Voltages	Core: 1.8/2.5/3.3 V; Output buffers: independently selectable 1.5/1.8/2.5/3.3 V per driver
Synthesis Resolution	1 ppb frequency step size; enables true zero-ppm accuracy on all outputs
Package	24-pin QFN, 4 × 4 mm, 0.5 mm pitch; RoHS-compliant, moisture-sensitive level 3
Operating Temp	–40 °C to +85 °C ambient; validated for industrial and telecom line card environments

Pinout & Package

SI5338M-B04373-GM uses a 24-lead QFN package (4 mm × 4 mm, 0.5 mm pitch) with exposed thermal pad. Pin 1 is top-left corner (IN1), pin 24 is bottom-right (GND). The package supports reflow soldering per JEDEC J-STD-020 (peak 260 °C).

Pin/Terminal	Circuit Role	Design Meaning
IN1, IN2, IN5, IN6	Differential input pairs	Accept 5–710 MHz AC-coupled differential clocks; require external 100 Ω termination
IN3, IN4	Single-ended CMOS inputs	Support 5–200 MHz DC-coupled clocks; VIH = 0.7×VDD, VIL = 0.3×VDD
CLK0A–CLK3B	Differential output pairs	Four independent outputs; each pair (e.g., CLK0A/CLK0B) delivers complementary signals
VDDO0–VDDO3	Output buffer supplies	Independent 1.4–3.63 V supplies per output bank; enable mixed-voltage clock distribution
VDD	Core supply	1.8/2.5/3.3 V core; PSRR optimized for low-noise operation
SCL, SDA	I²C interface	SMBus-compatible 100/400 kHz interface; supports ClockBuilder Pro programming
INTR	Interrupt output	Open-drain status indicator for loss-of-lock and loss-of-signal alarms

Key Features

Feature	Design Value
MultiSynth™ synthesis	Four independent fractional-N synthesizers enabling any-frequency generation with 1 ppb resolution and zero ppm error
PCIe Gen 4 compliance	Validated 0.15–0.45 ps RMS jitter in common clock mode; meets PCI-SIG Base Spec 4.0 rev 0.5 requirements
Per-output voltage control	Each of four output banks powered by separate VDDOx pins (1.5/1.8/2.5/3.3 V), eliminating level-shifter ICs
Glitchless frequency tuning	Hardware-supported ±1 ppm frequency increment/decrement via PINC/FDEC pins without output interruption
Programmable phase offset	±45 ns initial phase adjustment per output with <20 ps step resolution for skew compensation
Spread spectrum control	Configurable SSC on any output: 0.5–5.0% spread depth, 33–63 kHz modulation rate, down-spread default

Applications

PCIe Gen 4 Switch Timing	Ethernet Switch/Routing
Use Scenario: Providing synchronized 100 MHz HCSL clocks to multiple PCIe Gen 4 switch ASICs in a 1U data center switch chassis. IC Role / Device Role / Timing Role: Quad-output clock generator delivering four independent, jitter-clean clocks meeting PCIe Gen 4 SRNS and common clock specs. Use Value: Eliminates four discrete oscillators while maintaining sub-0.45 ps RMS jitter and enabling per-port frequency margining via I²C.	Use Scenario: Generating 125 MHz LVDS and 156.25 MHz CMOS clocks for 1 GbE/10 GbE PHYs and packet processors in carrier-grade Ethernet routers. IC Role / Device Role / Timing Role: Any-frequency clock synthesizer supporting mixed-signal format outputs from a single 25 MHz crystal reference. Use Value: Reduces BOM count by replacing dedicated oscillators and level translators; supports IEEE 802.3 jitter masks via programmable SSC.
Broadcast Video Timing	FPGA/ASIC Clock Tree
Use Scenario: Delivering SMPTE ST 2082 (27 Gbps) reference clocks (27 MHz, 74.25 MHz, 148.5 MHz) to video encoder/decoder SoCs in 4K/8K broadcast equipment. IC Role / Device Role / Timing Role: Precision clock generator with <10 ps cycle-cycle jitter and programmable phase alignment across outputs. Use Value: Ensures frame-accurate synchronization across multi-channel video pipelines; eliminates timing skews between encode/decode paths.	Use Scenario: Supplying 300 MHz LVDS, 200 MHz HCSL, and 100 MHz CMOS clocks to heterogeneous FPGA fabric, transceivers, and memory controllers on a high-performance compute accelerator board. IC Role / Device Role / Timing Role: Configurable quad clock source with independent voltage and format per output bank. Use Value: Enables single-chip clocking of mixed-voltage domains (e.g., 1.8 V transceivers, 1.2 V logic, 3.3 V peripherals) without external regulators or buffers.

PCIe Gen 4 Switch Timing

Ethernet Switch/Routing

Use Scenario: Providing synchronized 100 MHz HCSL clocks to multiple PCIe Gen 4 switch ASICs in a 1U data center switch chassis.

IC Role / Device Role / Timing Role: Quad-output clock generator delivering four independent, jitter-clean clocks meeting PCIe Gen 4 SRNS and common clock specs.

Use Value: Eliminates four discrete oscillators while maintaining sub-0.45 ps RMS jitter and enabling per-port frequency margining via I²C.

Use Scenario: Generating 125 MHz LVDS and 156.25 MHz CMOS clocks for 1 GbE/10 GbE PHYs and packet processors in carrier-grade Ethernet routers.

IC Role / Device Role / Timing Role: Any-frequency clock synthesizer supporting mixed-signal format outputs from a single 25 MHz crystal reference.

Use Value: Reduces BOM count by replacing dedicated oscillators and level translators; supports IEEE 802.3 jitter masks via programmable SSC.

Broadcast Video Timing

FPGA/ASIC Clock Tree

Use Scenario: Delivering SMPTE ST 2082 (27 Gbps) reference clocks (27 MHz, 74.25 MHz, 148.5 MHz) to video encoder/decoder SoCs in 4K/8K broadcast equipment.

IC Role / Device Role / Timing Role: Precision clock generator with <10 ps cycle-cycle jitter and programmable phase alignment across outputs.

Use Value: Ensures frame-accurate synchronization across multi-channel video pipelines; eliminates timing skews between encode/decode paths.

Use Scenario: Supplying 300 MHz LVDS, 200 MHz HCSL, and 100 MHz CMOS clocks to heterogeneous FPGA fabric, transceivers, and memory controllers on a high-performance compute accelerator board.

IC Role / Device Role / Timing Role: Configurable quad clock source with independent voltage and format per output bank.

Use Value: Enables single-chip clocking of mixed-voltage domains (e.g., 1.8 V transceivers, 1.2 V logic, 3.3 V peripherals) without external regulators or buffers.

Equivalent & Alternatives

The following parts are listed as comparable options for similar quad clock generator applications.

Alternative Part	Technical Difference	Application Difference	Selection Advice
Si5332A-D06989-GM	Higher integration: 8 outputs, integrated LDOs, lower jitter (0.35 ps RMS), supports JESD204B deterministic latency	Targeted at JESD204B SerDes and multi-gigabit ADC/DAC systems requiring sub-100 fs jitter	Select when >4 outputs, ultra-low jitter, or deterministic latency are required; higher cost and larger 32-QFN package
ICS8430I-01LG	Fixed-frequency quad LVDS generator (no I²C programming); 1.2 ps RMS jitter; 3.3 V only; no spread spectrum	Suitable for legacy designs with static clock trees where reprogramming is unnecessary	Select for cost-sensitive, non-reconfigurable applications with fixed 100/125/156.25 MHz outputs and no need for dynamic tuning

Compared with Si5332A-D06989-GM and ICS8430I-01LG, SI5338M-B04373-GM offers optimal balance of programmability, PCIe Gen 4 compliance, and 4-output density in a compact 4×4 mm QFN-making it ideal for space-constrained, field-upgradable timing architectures requiring zero-ppm synthesis and mixed-voltage support.

Availability

SI5338M-B04373-GM is available at Aetrix Electronics and suitable for PCIe Gen 4 switch timing, Ethernet routing, broadcast video synchronization, and FPGA clock tree applications requiring stable component supply, long-term lifecycle support, and traceable sourcing.

Supply support for SI5338M-B04373-GM includes scheduled delivery planning, volume procurement assistance, BOM continuity management, traceable sourcing, and lifecycle availability coordination for OEM customers, industrial embedded developers, connected-device designers, and electronics production programs.

Manufacturer

Skyworks Solutions is a global leader in analog and mixed-signal semiconductors, specializing in RF, timing, and connectivity solutions for infrastructure, automotive, and mobile markets.

The Si5338 product line was designed for high-performance, software-configurable clock generation in datacenter, telecom, and broadcast systems-enabling consolidation of multiple oscillators into a single, field-programmable device with PCIe and Ethernet compliance.

FAQ

What is the maximum output frequency supported by SI5338M-B04373-GM?

The SI5338M-B04373-GM supports up to 710 MHz on LVPECL/LVDS/CML outputs, 350 MHz on SSTL/HSTL, 250 MHz on HCSL, and 200 MHz on CMOS. However, only two unique frequencies above 350 MHz can be generated simultaneously (Fvco/4 and Fvco/6), as defined by the internal VCO architecture. All frequencies are synthesized with MultiSynth™ technology and maintain ≤0.7 ps RMS jitter.

Does SI5338M-B04373-GM support PCIe Gen 4 Separate Reference No Spread (SRNS) mode?

Yes, SI5338M-B04373-GM is compliant with PCIe Gen 4 SRNS mode, achieving 0.11–0.32 ps RMS jitter (typical 0.11 ps) when configured with a PLL bandwidth of 2–4 MHz and CDR set to 10 MHz. This compliance is verified per PCI-SIG Base Specification 4.0 rev 0.5 and documented in Skyworks' AN562 application note.

Can SI5338M-B04373-GM generate different output voltages on each of its four output banks?

Yes, SI5338M-B04373-GM provides independent VDDO0–VDDO3 pins, allowing each of the four output banks to be powered at 1.5 V, 1.8 V, 2.5 V, or 3.3 V. This enables direct interfacing with mixed-voltage devices (e.g., 1.8 V FPGA transceivers and 3.3 V legacy peripherals) without external level shifters or regulators-reducing board area and power loss.

How is SI5338M-B04373-GM programmed, and is ClockBuilder Pro required?

SI5338M-B04373-GM is programmed via its I²C/SMBus interface (SCL/SDA pins) using register writes. While ClockBuilder Pro is the recommended GUI tool for configuration, full register-level programming is possible using custom firmware. The device includes one-time programmable (OTP) NVM for storing boot configurations, enabling autonomous startup without host intervention.

What input reference options does SI5338M-B04373-GM support?

SI5338M-B04373-GM supports six input references: two differential pairs (IN1/IN2, IN5/IN6) for 5–710 MHz; two single-ended CMOS inputs (IN3/IN4) for 5–200 MHz; and an external crystal (8–30 MHz) across IN1/IN2. Input flexibility allows use with OCXOs, TCXOs, recovered SerDes clocks, or low-cost crystals-enabling both high-precision and cost-optimized timing architectures.

SI5338M-B04373-GM Specifications

Product attributes: Attribute value

Manufacturer:: Skyworks Solutions Inc.

Series:: MultiSynth™

Package/Case:: 24-VFQFN Exposed Pad

Packaging:: Tray

Product Status:: Active

Programmable:: Not Verified

PLL:: -

Main Purpose:: -

Input:: -

Output:: -

Number of Circuits:: -

Ratio - Input:Output:: -

Differential - Input:Output:: -

Frequency - Max:: -

Voltage - Supply:: -

Operating Temperature:: -

Mounting Type:: Surface Mount

Grade:: -

Qualification:: -

Supplier Device Package:: 24-QFN (4x4)

SI5338M-B04373-GM FAQ

1.How can I place an order for SI5338M-B04373-GM through Aetrix?

Please submit a Request for Quotation (RFQ) for SI5338M-B04373-GM on Aetrix. Our sales agent will provide a competitive quotation and guide you through the order confirmation once you accept the terms.

2.Are the price and stock information for SI5338M-B04373-GM reliable?

The price and inventory of SI5338M-B04373-GM are updated periodically and may fluctuate due to market conditions. Stock and pricing data are typically refreshed every 24 hours. Quotation validity for SI5338M-B04373-GM is usually 5 days.

3.What payment methods are accepted for SI5338M-B04373-GM?

We accept Wire Transfer, PayPal, Credit Card, Western Union, MoneyGram, and Escrow for SI5338M-B04373-GM transactions.

Note: Certain payment methods may incur a processing fee.

4.How is shipping managed for SI5338M-B04373-GM?

SI5338M-B04373-GM orders can be shipped via leading logistics carriers, including DHL, UPS, FedEx, TNT, or Registered Mail.

Once your SI5338M-B04373-GM order is processed, you will receive an email with the shipment details and tracking number.

Note: Tracking information may take up to 24 hours to appear. Express delivery typically takes 3–5 business days.

5.How can I obtain technical support or documentation for SI5338M-B04373-GM?

For technical support, including SI5338M-B04373-GM datasheets, pinout diagrams, or application guidance, please contact our engineering support team. They can provide detailed documentation and assistance for your SI5338M-B04373-GM requirements.

6.How does Aetrix verify that SI5338M-B04373-GM is sourced from the original manufacturer or authorized distributors?

All SI5338M-B04373-GM products on Aetrix are procured from qualified distributors and authorized channels. Our dedicated quality assurance team conducts strict verification, including traceability checks and, if necessary, third-party testing. This ensures that SI5338M-B04373-GM meets industry standards.

7.What is the process for return or replacement of SI5338M-B04373-GM?

All SI5338M-B04373-GM units undergo pre-shipment inspection (PSI). If there is an issue with SI5338M-B04373-GM, returns or replacements are accepted under the following conditions:

1.Quantity discrepancies, incorrect items, or visible external defects (such as breakage or corrosion), acknowledged by Aetrix.

2.The issue is reported within 90 days of delivery.

3.The SI5338M-B04373-GM part is unused and in its original packaging.

Return procedure for SI5338M-B04373-GM:

1.Submit a request within 90 days.

2.Obtain a Return Material Authorization (RMA) from Aetrix.

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