Skyworks Solutions Inc. SI5338M-B04373-GMR

Overview

SI5338M-B04373-GMR from Skyworks Solutions is an I²C-programmable quad clock generator with four independently configurable differential or single-ended outputs, 0.7 ps RMS typical phase jitter, PCIe Gen 1–4 Common Clock and Gen 3 SRNS compliance, and operation from 1.8/2.5/3.3 V core supply in a 4 × 4 mm 24-QFN package. It replaces up to four crystal oscillators in high-speed serial interface timing applications.

For engineers reviewing the SI5338M-B04373-GMR datasheet, SI5338M-B04373-GMR pinout, SI5338M-B04373-GMR application, or SI5338M-B04373-GMR equivalent, key selection criteria include PCIe Gen 4 jitter compliance (0.15–0.45 ps RMS), independent output voltage per driver (1.5/1.8/2.5/3.3 V), MultiSynth™ fractional synthesis resolution (1 ppb), spread-spectrum control (0.5–5.0% down-spread), and loss-of-lock/loss-of-signal alarm support.

Technical Context

The SI5338M-B04373-GMR implements a two-stage PLL architecture: a high-stability integer-N PLL for reference conditioning followed by four independent MultiSynth™ fractional-N synthesizers-one per output channel-enabling any-frequency generation from 0.16 MHz to 710 MHz. Each output supports programmable format (LVPECL/LVDS/HCSL/CMOS/SSTL/HSTL) and voltage (1.5–3.3 V).

It accepts six input references-including 8–30 MHz crystals, 5–200 MHz CMOS, 5–350 MHz SSTL/HSTL, and 5–710 MHz differential-and provides independent phase adjustment (<20 ps steps), frequency increment/decrement (1 ppm steps), and spread-spectrum modulation (33–63 kHz rate, 0.5–5.0% deviation) on any output.

Key Specifications

Pinout & Package

SI5338M-B04373-GMR uses a 24-lead QFN package (4 × 4 mm, 0.5 mm pitch) with exposed thermal pad. Pin assignments are fixed across Si5338 family variants per Skyworks Rev. 1.6 datasheet Figure 1 (Top View).

Key Features

Applications

Equivalent & Alternatives

The following parts are listed as comparable options for similar quad clock generator applications.

Compared with Si5338A-B04373-GM and ICS854S01IAGLF, SI5338M-B04373-GMR delivers factory-validated PCIe Gen 4 SRNS compliance, full I²C configurability, and independent output voltage control-enabling rapid deployment in high-speed serial timing without custom firmware or layout redesign.

Availability

SI5338M-B04373-GMR is available at Aetrix Electronics and suitable for PCIe Gen 4 switch timing, Ethernet switching/routing, broadcast video synchronization, and FPGA processor clocking requiring stable component supply across industrial temperature ranges and long production lifecycles.

Supply support for SI5338M-B04373-GMR includes scheduled delivery planning, volume procurement assistance, BOM continuity management, traceable sourcing, and lifecycle availability coordination for OEM customers, industrial embedded developers, connected-device designers, and electronics production programs.

Manufacturer

Skyworks Solutions is a global semiconductor company specializing in analog and mixed-signal connectivity solutions for wireless, broadband, automotive, and industrial markets.

The Si5338 product line delivers programmable, low-jitter clock generation for high-speed serial interfaces-including PCIe, Ethernet, Fibre Channel, and broadcast video-where deterministic timing, multi-output flexibility, and field reconfigurability are critical.

FAQ

What is the guaranteed phase jitter performance of the SI5338M-B04373-GMR under PCIe Gen 4 conditions?

The SI5338M-B04373-GMR delivers 0.15–0.45 ps RMS phase jitter (12 kHz–20 MHz) in PCIe Gen 4 Common Clock mode with PLL bandwidth set to 2–4 MHz and CDR at 10 MHz. This is measured per PCI-SIG Base Specification 4.0 rev. 0.5 using 100 MHz HCSL outputs and validated with the Skyworks PCIe Clock Jitter Tool. SI5338M-B04373-GMR meets Gen 4 SRNS requirements without external filtering.

Does the SI5338M-B04373-GMR support independent voltage supply per output bank?

Yes, the SI5338M-B04373-GMR provides four dedicated VDDOx pins (VDDO0–VDDO3), each configurable for 1.5 V, 1.8 V, 2.5 V, or 3.3 V operation. This allows simultaneous LVDS (2.5 V), HCSL (1.8 V), CMOS (3.3 V), and SSTL (1.5 V) outputs on a single device. SI5338M-B04373-GMR requires individual 0.1 µF + 10 µF decoupling per VDDO rail per Skyworks layout guidelines.

Can the SI5338M-B04373-GMR generate frequencies above 350 MHz on multiple outputs simultaneously?

Yes, but with constraint: only two unique frequencies above 350 MHz may be generated simultaneously-specifically Fvco/4 and Fvco/6-per Skyworks datasheet Table 6 note 6. For example, SI5338M-B04373-GMR can output 473.33 MHz and 710 MHz concurrently, but not three distinct >350 MHz frequencies. All outputs remain fully programmable within their respective format limits (e.g., LVPECL up to 710 MHz).

How does the SI5338M-B04373-GMR handle loss-of-signal detection and reporting?

The SI5338M-B04373-GMR monitors all six input pins (IN1–IN6) for loss-of-signal (LOS) with 2.6–5 µs detection time and 0.01–1 µs release time. Detection status is reported via the open-drain INTR pin and readable through I²C register 0x000D. SI5338M-B04373-GMR also provides loss-of-lock (LOL) detection with 5–10 ms response, enabling fail-safe clock monitoring in telecom and industrial systems.

Is ClockBuilder Pro software required to configure the SI5338M-B04373-GMR?

No-ClockBuilder Pro is optional but strongly recommended. SI5338M-B04373-GMR supports full I²C/SMBus configuration (100/400 kHz) using raw register writes per datasheet Section 6. However, ClockBuilder Pro automates complex MultiSynth™ calculations, validates PCIe/Ethernet compliance, generates .c files for embedded initialization, and exports configuration bitstreams-reducing SI5338M-B04373-GMR bring-up time from hours to minutes.