Send an Inquiry

To receive a quote for your project, please fill in the following information, and we’ll get back to you promptly.

Submit Inventory List

Please fill in the following information, and we’ll get back to you promptly.

Home > Products > Integrated Circuits (ICs) > Clock/Timing > Application Specific Clock/Timing

Skyworks Solutions Inc. SI5338M-B04405-GM

Name: SI5338M-B04405-GM
Brand: Skyworks Solutions Inc.
SKU: SI5338M-B04405-GM
Price: 2.40 USD
Availability: InStock
Rating: 5 (2 reviews)

Compare

Part No.:: SI5338M-B04405-GM

Manufacturer:: Skyworks Solutions Inc.

Category:: Application Specific Clock/Timing

Package:: 24-VFQFN Exposed Pad

Datasheet:: SI5338M-B04405-GM.pdf

Description:: I2C CONTROL, 4-OUTPUT, ANY FREQU

Quantity:: RFQ Add To RFQ list

Payment:

Shipping:

Inventory:1,704

Please send an inquiry. Send us your inquiry, and we will respond immediately.

Product details

Overview

SI5338M-B04405-GM from Skyworks Solutions is an I²C-programmable quad clock generator with four independently configurable differential or single-ended outputs, 0.7 ps RMS typical phase jitter, PCIe Gen 1–4 Common Clock and Gen 3 SRNS compliance, and operation across –40 to +85 °C. It replaces up to four crystal oscillators in Ethernet switch/router, PCIe, and FPGA clocking systems.

For engineers reviewing the SI5338M-B04405-GM datasheet, SI5338M-B04405-GM pinout, SI5338M-B04405-GM application, or SI5338M-B04405-GM equivalent, key selection criteria include its MultiSynth™-based any-frequency synthesis (0.16–710 MHz), independent output voltage per driver (1.5/1.8/2.5/3.3 V), low-power 4×4 mm QFN package, and I²C/SMBus programmability with ClockBuilder Pro support.

Technical Context

The SI5338M-B04405-GM integrates a high-stability PLL-based synthesis stage followed by four independent MultiSynth™ fractional-N dividers, enabling true zero-ppm frequency accuracy on all outputs. Its architecture supports both free-running clock generation and synchronous frequency translation modes.

It features dual-stage synthesis: Stage 1 (PLL) locks to one of six input references (crystal, CMOS, SSTL/HSTL, or differential), while Stage 2 (MultiSynth™) generates each output with independent M/N/P division, phase offset (<20 ps step), and spread-spectrum control (0.5–5.0% spread, 33–63 kHz modulation).

Key Specifications

Parameter	Value and Actual Design Meaning
Phase Jitter (RMS)	0.7 ps - meets PCIe Gen 3 SRNS and GbE jitter requirements at 125 MHz output
Output Frequency Range	0.16–710 MHz - covers LVPECL/LVDS (≤710 MHz), HCSL (≤250 MHz), CMOS (≤200 MHz), SSTL/HSTL (≤350 MHz)
Input Reference Support	Crystal (8–30 MHz), CMOS (5–200 MHz), SSTL/HSTL (5–350 MHz), differential (5–710 MHz) - enables flexible system clock sourcing
Supply Voltages	VDD = 1.8/2.5/3.3 V ±10%; VDDOx = 1.4–3.63 V - allows mixed-voltage board design with independent output driver rails
Package	24-pin QFN, 4 × 4 mm, 0.5 mm pitch - space-efficient for high-density timing applications
Operating Temperature	–40 to +85 °C - qualified for industrial and telecom line card environments
Power Consumption	45 mA core supply typical at 100 MHz on all outputs - optimized for low thermal impact in multi-output timing systems

Pinout & Package

SI5338M-B04405-GM uses a 24-pin, 4 × 4 mm QFN package with exposed thermal pad. Pin functions are defined per Skyworks Rev. 1.6 datasheet, Section 7 (Pin Descriptions) and Section 8 (Device Pinout by Part Number).

Pin/Terminal	Circuit Role	Design Meaning
IN1, IN2, IN5, IN6	Differential Input Pairs	Accept AC-coupled differential reference clocks up to 710 MHz; require external 100 Ω termination
IN3, IN4	Single-Ended Inputs	Support CMOS/SSTL/HSTL references (5–350 MHz); VIH/VIL thresholds scale with VDD
CLK0A–CLK3B	Differential Output Pairs	Four independent output drivers; each configurable as LVPECL, LVDS, HCSL, CML, or SSTL/HSTL
VDDO0–VDDO3	Output Buffer Supplies	Independent 1.4–3.63 V rails per output bank - enable mixed-signal interface voltage translation
VDD	Core Supply	1.8/2.5/3.3 V ±10% core power; PSRR optimized for clean internal PLL operation
SCL, SDA	I²C Interface	SMBus-compatible serial programming interface (up to 400 kHz); supports ClockBuilder Pro configuration
INTR	Interrupt Output	Open-drain status indicator for loss-of-lock (LOL) and loss-of-signal (LOS) alarms
RSVD_GND	Reserved Ground	Internal test pin; must be connected to GND per layout guidelines

Key Features

Feature	Design Value
Any-frequency synthesis per output	Four independent MultiSynth™ engines deliver 0 ppm precision across 0.16–710 MHz without external crystals
PCIe Gen 1–4 compliance	Meets Common Clock jitter specs (Gen 1–4) and Gen 3 SRNS; validated using Intel Clock Jitter Tool
Independent output voltage control	VDDOx pins allow per-output rail assignment (1.5/1.8/2.5/3.3 V), simplifying interface to mixed-voltage FPGAs and ASICs
Glitchless frequency tuning	1 ppm-step increment/decrement via PINC/FDEC pins enables real-time dynamic frequency adjustment without output interruption
Programmable phase offset	±45 ns range with <20 ps resolution per output - supports precise skew alignment in multi-lane SerDes systems
Configurable spread spectrum	0.5–5.0% down-spread at 33–63 kHz on any output - reduces EMI in noise-sensitive embedded systems

Applications

Ethernet Switch/Router Timing	PCIe Gen 3/4 Clock Distribution
Use Scenario: High-port-count 1/10 GbE switches requiring synchronized 125 MHz and 156.25 MHz clocks across multiple PHYs and MACs. IC Role / Device Role / Timing Role: Quad-output clock generator providing four low-jitter, phase-aligned clocks - two for SERDES lanes, one for management CPU, one for packet buffer controller. Use Value: Eliminates four discrete oscillators; achieves <0.7 ps RMS jitter meeting IEEE 802.3bj and PCIe Gen 4 common clock specs.	Use Scenario: Server motherboard with dual x16 PCIe Gen 4 slots, CPU, and chipset requiring compliant 100 MHz reference clocks with tight skew and low additive jitter. IC Role / Device Role / Timing Role: PCIe-compliant clock source delivering four independent 100 MHz HCSL outputs with SRNS validation and <0.32 ps RMS jitter. Use Value: Enables single-chip replacement of multiple oscillators while satisfying PCIe Base Spec 4.0 jitter mask and CDR lock requirements.
FPGA and Processor Clocking	Broadcast Video/Audio Synchronization
Use Scenario: Xilinx Versal or Intel Agilex FPGA platform needing multiple domain clocks (e.g., 300 MHz PL fabric, 200 MHz DDR4 PHY, 100 MHz PCIe, 50 MHz debug). IC Role / Device Role / Timing Role: Configurable quad clock generator synthesizing exact frequencies per domain with independent voltage and format control. Use Value: Reduces BOM count and PCB area; supports mixed I/O standards (LVDS for memory, HCSL for PCIe, CMOS for peripherals) from one IC.	Use Scenario: SMPTE ST 2082-1 (12G-SDI) video router requiring ultra-low-jitter 74.25 MHz and 148.5 MHz reference clocks with sub-100 ps inter-output skew. IC Role / Device Role / Timing Role: Precision timing IC generating synchronized broadcast-grade clocks with programmable phase offsets for frame alignment. Use Value: Delivers <100 ps output-to-output skew and 0.7 ps RMS jitter - meets SMPTE RP 184 and ITU-R BT.601 stability requirements.

Ethernet Switch/Router Timing

PCIe Gen 3/4 Clock Distribution

Use Scenario: High-port-count 1/10 GbE switches requiring synchronized 125 MHz and 156.25 MHz clocks across multiple PHYs and MACs.

IC Role / Device Role / Timing Role: Quad-output clock generator providing four low-jitter, phase-aligned clocks - two for SERDES lanes, one for management CPU, one for packet buffer controller.

Use Value: Eliminates four discrete oscillators; achieves <0.7 ps RMS jitter meeting IEEE 802.3bj and PCIe Gen 4 common clock specs.

Use Scenario: Server motherboard with dual x16 PCIe Gen 4 slots, CPU, and chipset requiring compliant 100 MHz reference clocks with tight skew and low additive jitter.

IC Role / Device Role / Timing Role: PCIe-compliant clock source delivering four independent 100 MHz HCSL outputs with SRNS validation and <0.32 ps RMS jitter.

Use Value: Enables single-chip replacement of multiple oscillators while satisfying PCIe Base Spec 4.0 jitter mask and CDR lock requirements.

FPGA and Processor Clocking

Broadcast Video/Audio Synchronization

Use Scenario: Xilinx Versal or Intel Agilex FPGA platform needing multiple domain clocks (e.g., 300 MHz PL fabric, 200 MHz DDR4 PHY, 100 MHz PCIe, 50 MHz debug).

IC Role / Device Role / Timing Role: Configurable quad clock generator synthesizing exact frequencies per domain with independent voltage and format control.

Use Value: Reduces BOM count and PCB area; supports mixed I/O standards (LVDS for memory, HCSL for PCIe, CMOS for peripherals) from one IC.

Use Scenario: SMPTE ST 2082-1 (12G-SDI) video router requiring ultra-low-jitter 74.25 MHz and 148.5 MHz reference clocks with sub-100 ps inter-output skew.

IC Role / Device Role / Timing Role: Precision timing IC generating synchronized broadcast-grade clocks with programmable phase offsets for frame alignment.

Use Value: Delivers <100 ps output-to-output skew and 0.7 ps RMS jitter - meets SMPTE RP 184 and ITU-R BT.601 stability requirements.

Equivalent & Alternatives

The following parts are listed as comparable options for similar quad clock generator applications.

Alternative Part	Technical Difference	Application Difference	Selection Advice
Si5338A-B-GM	Same Si5338 family; differs in factory-programmed NVM configuration (B04405 vs. default A variant); identical pinout, electrical specs, and package	Pre-configured for specific frequency plan; requires no initial I²C programming for target use case	Select when pre-loaded configuration matches system requirements - reduces firmware initialization overhead
LMK04832ISQE/NOPB	Two PLLs + 14 outputs; higher channel count but larger 64-pin WQFN; 0.18 ps RMS jitter (lower), higher power (90 mA)	Targeted at high-channel-count, ultra-low-jitter applications (e.g., radar, test equipment); not drop-in compatible	Choose for systems needing >4 outputs or sub-0.2 ps jitter; avoid if footprint or power budget is constrained

Compared with Si5338A-B-GM, SI5338M-B04405-GM offers identical hardware but factory-tuned for a specific multi-frequency profile; versus LMK04832ISQE/NOPB, it trades output count and ultimate jitter performance for smaller size, lower power, and direct QFN compatibility in space-constrained designs.

Availability

SI5338M-B04405-GM is available at Aetrix Electronics and suitable for Ethernet switch/router timing, PCIe Gen 4 clock distribution, and FPGA clocking applications requiring stable component supply, long-term lifecycle support, and guaranteed traceable sourcing.

Supply support for SI5338M-B04405-GM includes scheduled delivery planning, volume procurement assistance, BOM continuity management, traceable sourcing, and lifecycle availability coordination for OEM customers, industrial embedded developers, connected-device designers, and electronics production programs.

Manufacturer

Skyworks Solutions is a global semiconductor company specializing in analog and mixed-signal connectivity solutions for wireless, broadband, automotive, and industrial markets.

The Si5338 product line delivers programmable, low-jitter clock generation for high-speed digital systems including PCIe, Ethernet, and broadcast video - designed to replace multiple fixed-frequency oscillators with a single configurable IC.

FAQ

What is the primary function of the SI5338M-B04405-GM in a timing system?

The SI5338M-B04405-GM serves as an I²C-programmable quad clock generator that synthesizes up to four independent, any-frequency output clocks from a single reference input. It replaces multiple discrete oscillators in systems like PCIe Gen 4 motherboards and 10 GbE switches, delivering 0.7 ps RMS typical phase jitter and PCIe SRNS compliance. Its MultiSynth™ architecture ensures true zero-ppm frequency accuracy on all outputs.

Does the SI5338M-B04405-GM support PCIe Gen 4 Common Clock compliance?

Yes, the SI5338M-B04405-GM is explicitly validated for PCIe Gen 4 Common Clock compliance per the PCI-Express Base Specification 4.0 rev. 0.5, achieving ≤0.45 ps RMS jitter (10 kHz–50 MHz) in HCSL 100 MHz output mode with PLL bandwidth set to 2–4 MHz and CDR at 10 MHz. This is confirmed in Table 12 of the Skyworks Rev. 1.6 datasheet and verified using the Skyworks PCIe Clock Jitter Tool.

Can the SI5338M-B04405-GM generate different output formats simultaneously?

Yes, the SI5338M-B04405-GM supports simultaneous mixed-format outputs: for example, CLK0A/B as LVDS (156.25 MHz), CLK1A/B as HCSL (100 MHz), CLK2A/B as LVPECL (312.5 MHz), and CLK3A/B as CMOS (50 MHz). Each of the four output banks is independently configurable for signal format (LVPECL/LVDS/HCSL/CMOS/SSTL/HSTL) and supply voltage (1.5/1.8/2.5/3.3 V), enabling direct interfacing with heterogeneous logic families.

What reference inputs does the SI5338M-B04405-GM accept?

The SI5338M-B04405-GM accepts six reference input types: differential (IN1/IN2, IN5/IN6) up to 710 MHz; single-ended CMOS (IN3/IN4) up to 200 MHz; SSTL/HSTL (IN3/IN4) up to 350 MHz; and external crystal (8–30 MHz) across IN1/IN2. All inputs support automatic loss-of-signal detection with configurable release time (0.01–1 µs), and the device includes dedicated LOS and LOL interrupt signaling via the INTR pin.

How is the SI5338M-B04405-GM programmed and configured?

The SI5338M-B04405-GM is programmed via its I²C/SMBus-compatible serial interface (SCL/SDA pins), supporting standard-mode (100 kHz) and fast-mode (400 kHz) operation. Configuration is simplified using Skyworks' ClockBuilder Pro software, which auto-generates register maps and .hex files. Factory-programmed NVM retains settings across power cycles, and pin-controlled frequency/phase adjustments (PINC/FDEC/OEB) enable real-time tuning without host intervention.

SI5338M-B04405-GM Specifications

Product attributes: Attribute value

Manufacturer:: Skyworks Solutions Inc.

Series:: MultiSynth™

Package/Case:: 24-VFQFN Exposed Pad

Packaging:: Tray

Product Status:: Active

Programmable:: Not Verified

PLL:: -

Main Purpose:: -

Input:: -

Output:: -

Number of Circuits:: -

Ratio - Input:Output:: -

Differential - Input:Output:: -

Frequency - Max:: -

Voltage - Supply:: -

Operating Temperature:: -

Mounting Type:: Surface Mount

Grade:: -

Qualification:: -

Supplier Device Package:: 24-QFN (4x4)

SI5338M-B04405-GM FAQ

1.How can I place an order for SI5338M-B04405-GM through Aetrix?

Please submit a Request for Quotation (RFQ) for SI5338M-B04405-GM on Aetrix. Our sales agent will provide a competitive quotation and guide you through the order confirmation once you accept the terms.

2.Are the price and stock information for SI5338M-B04405-GM reliable?

The price and inventory of SI5338M-B04405-GM are updated periodically and may fluctuate due to market conditions. Stock and pricing data are typically refreshed every 24 hours. Quotation validity for SI5338M-B04405-GM is usually 5 days.

3.What payment methods are accepted for SI5338M-B04405-GM?

We accept Wire Transfer, PayPal, Credit Card, Western Union, MoneyGram, and Escrow for SI5338M-B04405-GM transactions.

Note: Certain payment methods may incur a processing fee.

4.How is shipping managed for SI5338M-B04405-GM?

SI5338M-B04405-GM orders can be shipped via leading logistics carriers, including DHL, UPS, FedEx, TNT, or Registered Mail.

Once your SI5338M-B04405-GM order is processed, you will receive an email with the shipment details and tracking number.

Note: Tracking information may take up to 24 hours to appear. Express delivery typically takes 3–5 business days.

5.How can I obtain technical support or documentation for SI5338M-B04405-GM?

For technical support, including SI5338M-B04405-GM datasheets, pinout diagrams, or application guidance, please contact our engineering support team. They can provide detailed documentation and assistance for your SI5338M-B04405-GM requirements.

6.How does Aetrix verify that SI5338M-B04405-GM is sourced from the original manufacturer or authorized distributors?

All SI5338M-B04405-GM products on Aetrix are procured from qualified distributors and authorized channels. Our dedicated quality assurance team conducts strict verification, including traceability checks and, if necessary, third-party testing. This ensures that SI5338M-B04405-GM meets industry standards.

7.What is the process for return or replacement of SI5338M-B04405-GM?

All SI5338M-B04405-GM units undergo pre-shipment inspection (PSI). If there is an issue with SI5338M-B04405-GM, returns or replacements are accepted under the following conditions:

1.Quantity discrepancies, incorrect items, or visible external defects (such as breakage or corrosion), acknowledged by Aetrix.

2.The issue is reported within 90 days of delivery.

3.The SI5338M-B04405-GM part is unused and in its original packaging.

Return procedure for SI5338M-B04405-GM:

1.Submit a request within 90 days.

2.Obtain a Return Material Authorization (RMA) from Aetrix.

Tech Hub

2026-09-09 Counterfeit Electronic Components: How to Detect, Authenticate, and Test Suspect Parts

Counterfeit components can hide behind convincing markings and passing basic function tests. This engineering reference covers source traceability, external inspection, X-ray, XRF, electrical testing, …

2026-09-08 Obsolete Electronic Components: How to Source and Evaluate Replacements

A practical engineering and sourcing framework covering lifecycle verification, lifetime-buy calculations, replacement qualification, supplier checks and counterfeit-risk controls.

2026-09-07 TTL vs CMOS Logic Levels: 74HC and 74HCT Compatibility Explained

TTL and CMOS logic families differ in thresholds, loading, output drive, power and timing. This engineering guide compares 74HC and 74HCT, calculates noise margins and checks 3.3 V/5 V compatibility.

2026-09-04 Logic Level Shifter: How to Connect 3.3V and 5V Logic Safely

A practical engineering guide to 3.3V and 5V logic compatibility, input thresholds, resistor dividers, translator ICs, MOSFET level shifting, I2C pull-ups, timing limits and power-sequencing risks.

2026-09-03 74HC595 vs TPIC6B595: Output Drive, Pinout, Current, and Load Selection

The 74HC595 uses push-pull logic outputs, while the TPIC6B595 uses 50 V open-drain DMOS sinks for higher-power loads. This guide compares timing, current limits, 3.3 V interfacing, load wiring, thermal…

2026-09-02 74HC595 Pinout, Timing, Output Current, and Applications

The 74HC595 converts serial data into eight stable parallel outputs. This guide covers pin functions, shift and storage timing, OE and MR behavior, drive-current limits, cascading, voltage compatibilit…

2026-09-01 Latch vs Flip-Flop: Timing, Differences and Design Choices

A technical comparison of level-sensitive latches and edge-triggered flip-flops, covering timing windows, setup and hold limits, master–slave operation, time borrowing, race-through, HDL inference and…

2026-08-30 D Latch Circuit: Truth Table, Timing, ICs and Applications

A D latch stores one bit while Enable controls when data can pass. This reference covers gate-level operation, truth tables, transparency, setup and hold timing, LE versus OE, common ICs and practical …

2026-08-28 SR Latch Explained: NOR and NAND Circuits, Truth Tables, and Applications

An SR latch stores one bit through cross-coupled feedback. This engineering reference covers NOR and NAND implementations, truth tables, forbidden-state recovery, gated operation, switch debouncing, fa…

2026-08-27 Latch Circuit: SR and D Latches, Truth Tables, Timing, and Applications

Latch circuits retain one bit through feedback. This technical reference covers SR and D latches, truth tables, transparency, timing limits, latch-versus-flip-flop behavior, applications and common log…