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Home > Products > Integrated Circuits (ICs) > Clock/Timing > Application Specific Clock/Timing

Skyworks Solutions Inc. SI5338M-B04405-GMR

Name: SI5338M-B04405-GMR
Brand: Skyworks Solutions Inc.
SKU: SI5338M-B04405-GMR
Price: 2.40 USD
Availability: InStock
Rating: 5 (2 reviews)

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Part No.:: SI5338M-B04405-GMR

Manufacturer:: Skyworks Solutions Inc.

Category:: Application Specific Clock/Timing

Package:: 24-VFQFN Exposed Pad

Datasheet:: SI5338M-B04405-GMR.pdf

Description:: I2C CONTROL, 4-OUTPUT, ANY FREQU

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Product details

Overview

SI5338M-B04405-GMR from Skyworks Solutions is a quad-output, I²C-programmable clock generator with MultiSynth™ frequency synthesis. It delivers four independent, any-frequency outputs (0.16–710 MHz) with 0.7 ps RMS typical phase jitter, PCIe Gen 1–4 Common Clock and Gen 3 SRNS compliance, and support for LVPECL/LVDS/HCSL/CMOS/SSTL/HSTL output formats. It serves as a low-jitter replacement for up to four crystal oscillators in high-speed serial interface timing.

For engineers reviewing the SI5338M-B04405-GMR datasheet, SI5338M-B04405-GMR pinout, SI5338M-B04405-GMR application, or SI5338M-B04405-GMR equivalent, key selection criteria include its 24-QFN package, independent per-output voltage control (1.5/1.8/2.5/3.3 V), ±45 ns programmable phase offset, 1 ppm frequency increment/decrement resolution, and spread-spectrum capability (0.5–5.0% deviation, 33–63 kHz modulation).

Technical Context

The SI5338M-B04405-GMR implements a two-stage PLL architecture: a high-stability reference stage followed by four independent MultiSynth™ fractional-N synthesizers. Each output path includes configurable divider chains (R/M/N/P), selectable output drivers, and dedicated voltage supplies (VDDO0–VDDO3).

It supports flexible input references - external 8–30 MHz crystal, CMOS (5–200 MHz), SSTL/HSTL (5–350 MHz), or differential (5–710 MHz) - and enables zero-delay mode via external feedback. Loss-of-lock and loss-of-signal alarms provide real-time status monitoring over the I²C/SMBus interface.

Key Specifications

Parameter	Value and Actual Design Meaning
Output count & type	Four differential clock outputs (CLK0A/B through CLK3A/B); supports LVPECL, LVDS, HCSL, CML, CMOS, SSTL, HSTL
Frequency range	0.16–710 MHz per output; integer/fractional synthesis with 1 ppb resolution
Phase jitter (RMS)	0.7 ps typical (12 kHz–20 MHz), compliant with PCIe Gen 3 SRNS and GbE jitter requirements
Supply voltages	Core: 1.8/2.5/3.3 V; independent output buffers: 1.5/1.8/2.5/3.3 V per driver
Operating temperature	–40 °C to +85 °C ambient, qualified for industrial and telecom line card environments
Package	24-pin QFN, 4 mm × 4 mm, 0.5 mm pitch, exposed thermal pad
I²C interface	Standard-mode (100 kHz) and fast-mode (400 kHz) compatible; supports SMBus alert response

Pinout & Package

SI5338M-B04405-GMR is housed in a 24-lead, 4 mm × 4 mm QFN package with wettable flank leads and an exposed thermal pad. Pin numbering follows standard top-view orientation with Pin 1 at top-left corner.

Pin/Terminal	Circuit Role	Design Meaning
IN1, IN2	Differential reference input pair	Accepts 5–710 MHz AC-coupled differential clocks; internal 100 Ω termination enabled
IN3, IN4	Single-ended reference inputs	Support CMOS/SSTL/HSTL signals (5–350 MHz); configurable as primary or backup reference
IN5, IN6	Secondary differential reference pair	Redundant input path for failover or multi-reference architectures
CLK0A, CLK0B – CLK3A, CLK3B	Differential clock outputs	Four independent pairs; each configurable for format, voltage, slew, and termination
VDDO0–VDDO3	Output buffer supply rails	Independent 1.5/1.8/2.5/3.3 V supplies per output bank enable mixed-voltage system interfacing
VDD	Core logic supply	Single 1.8/2.5/3.3 V supply powers PLL, NVM, and control logic; >60 dB PSRR
SCL, SDA	I²C serial interface	Configurable address (default 0x70); supports clock stretching and repeated start
INTR	Interrupt output	Open-drain status indicator for loss-of-lock, loss-of-signal, or configuration error

Key Features

Feature	Design Value
MultiSynth™ synthesis	Four independent fractional-N synthesizers enabling true zero-ppm accuracy on all outputs simultaneously
Per-output voltage control	Each of four output banks powered by separate VDDOx rail (1.5/1.8/2.5/3.3 V) for direct interface with mixed-voltage FPGAs and ASICs
Programmable phase offset	±45 ns adjustment in <20 ps steps per output - enables precise skew management across high-speed SerDes lanes
Spread spectrum clocking	Configurable on any output: 0.5–5.0% down-spread, 33–63 kHz modulation rate - reduces EMI without affecting timing margin
Glitchless frequency tuning	1 ppm step size with pin-controlled increment/decrement; update time <667 ns above 18 MHz - enables dynamic rate adaptation
PCIe Gen 4 compliance	0.15–0.45 ps RMS jitter in Common Clock mode (100 MHz HCSL), verified per PCIe Base Spec 4.0 rev 0.5

Applications

PCIe Gen 4 Switch Timing	Ethernet Switch Clocking
Use Scenario: High-density 32-lane PCIe Gen 4 switch ASIC requiring four synchronized, low-jitter reference clocks for SerDes blocks and PHY layers. IC Role / Device Role / Timing Role: Quad clock generator providing independent 100 MHz HCSL clocks with matched phase alignment and <0.45 ps RMS jitter. Use Value: Meets PCIe Gen 4 Common Clock jitter mask without external jitter cleaners; eliminates need for four discrete oscillators and associated layout complexity.	Use Scenario: 10 GbE/25 GbE Ethernet switch line card needing scalable, reconfigurable clocks for MAC, PHY, and packet buffer interfaces. IC Role / Device Role / Timing Role: Programmable clock source delivering 125 MHz LVDS (MAC), 156.25 MHz HCSL (PHY), and 200 MHz CMOS (buffer control) from single device. Use Value: Enables field-upgradable clock configurations via I²C; supports multiple speed grades and protocol variants without hardware change.
Broadcast Video Synchronization	FPGA-Based Test Equipment
Use Scenario: SMPTE ST 2082/2110 video router requiring genlock-capable, ultra-low-jitter clocks for pixel clock, reference sync, and audio sample rate generation. IC Role / Device Role / Timing Role: Multi-format clock synthesizer generating 74.25 MHz (HD), 148.5 MHz (UHD), and 297 MHz (4K) with sub-20 ps inter-output skew. Use Value: Achieves broadcast-grade timing stability (<1 ps RMS additive jitter in buffer mode); supports frame-accurate switching between sources.	Use Scenario: High-speed digital pattern generator using FPGA fabric where deterministic clock phase relationships are critical for signal integrity validation. IC Role / Device Role / Timing Role: Precision timing engine supplying 500 MHz LVPECL (sampling), 250 MHz LVDS (trigger), and 100 MHz CMOS (control) with programmable phase offsets. Use Value: Enables nanosecond-level timing calibration across stimulus and capture paths; eliminates external delay lines and manual trimming.

PCIe Gen 4 Switch Timing

Ethernet Switch Clocking

Use Scenario: High-density 32-lane PCIe Gen 4 switch ASIC requiring four synchronized, low-jitter reference clocks for SerDes blocks and PHY layers.

IC Role / Device Role / Timing Role: Quad clock generator providing independent 100 MHz HCSL clocks with matched phase alignment and <0.45 ps RMS jitter.

Use Value: Meets PCIe Gen 4 Common Clock jitter mask without external jitter cleaners; eliminates need for four discrete oscillators and associated layout complexity.

Use Scenario: 10 GbE/25 GbE Ethernet switch line card needing scalable, reconfigurable clocks for MAC, PHY, and packet buffer interfaces.

IC Role / Device Role / Timing Role: Programmable clock source delivering 125 MHz LVDS (MAC), 156.25 MHz HCSL (PHY), and 200 MHz CMOS (buffer control) from single device.

Use Value: Enables field-upgradable clock configurations via I²C; supports multiple speed grades and protocol variants without hardware change.

Broadcast Video Synchronization

FPGA-Based Test Equipment

Use Scenario: SMPTE ST 2082/2110 video router requiring genlock-capable, ultra-low-jitter clocks for pixel clock, reference sync, and audio sample rate generation.

IC Role / Device Role / Timing Role: Multi-format clock synthesizer generating 74.25 MHz (HD), 148.5 MHz (UHD), and 297 MHz (4K) with sub-20 ps inter-output skew.

Use Value: Achieves broadcast-grade timing stability (<1 ps RMS additive jitter in buffer mode); supports frame-accurate switching between sources.

Use Scenario: High-speed digital pattern generator using FPGA fabric where deterministic clock phase relationships are critical for signal integrity validation.

IC Role / Device Role / Timing Role: Precision timing engine supplying 500 MHz LVPECL (sampling), 250 MHz LVDS (trigger), and 100 MHz CMOS (control) with programmable phase offsets.

Use Value: Enables nanosecond-level timing calibration across stimulus and capture paths; eliminates external delay lines and manual trimming.

Equivalent & Alternatives

The following parts are listed as comparable options for similar quad-output programmable clock generator applications.

Alternative Part	Technical Difference	Application Difference	Selection Advice
Si5332A-D05889-GM	Higher integration: 8 outputs, integrated jitter cleaner, lower 0.35 ps RMS jitter; requires external 100 MHz reference for optimal performance	Targeted at 100G/400G optical modules and AI accelerator cards demanding ultra-low jitter and higher channel count	Select when >4 outputs or <0.4 ps RMS jitter is required; not drop-in due to different pinout and register map
ICS8430I-01T	Fixed-frequency, non-programmable quad LVDS clock buffer; no synthesis capability; 1.2 ps RMS jitter; 3.3 V only	Suitable only for static clock fanout in legacy systems where frequency agility is unnecessary	Choose only for cost-sensitive, fixed-clock designs with no requirement for I²C configuration or frequency translation

Compared with Si5332A-D05889-GM and ICS8430I-01T, SI5338M-B04405-GMR uniquely balances full I²C programmability, four independent synthesizers, PCIe Gen 4 compliance, and compact 4×4 mm footprint - making it optimal for space-constrained, multi-protocol embedded systems requiring field-reconfigurable timing.

Availability

SI5338M-B04405-GMR is available at Aetrix Electronics and suitable for PCIe Gen 4 switch timing, Ethernet switch clocking, broadcast video synchronization, and FPGA-based test equipment requiring stable component supply and long-term design continuity.

Supply support for SI5338M-B04405-GMR includes scheduled delivery planning, volume procurement assistance, BOM continuity management, traceable sourcing, and lifecycle availability coordination for OEM customers, industrial embedded developers, connected-device designers, and electronics production programs.

Manufacturer

Skyworks Solutions is a global leader in analog and mixed-signal semiconductors, specializing in RF, timing, and connectivity solutions for infrastructure, automotive, and industrial markets.

The SI5338 family was designed to replace multiple discrete oscillators and buffers in high-speed serial interface systems, delivering programmable, low-jitter clock generation in minimal PCB area - specifically targeting PCIe, Ethernet, and broadcast video timing challenges.

FAQ

What is the default I²C address for SI5338M-B04405-GMR?

The SI5338M-B04405-GMR ships with a factory-default I²C slave address of 0x70 (7-bit). This address can be permanently modified via OTP memory using ClockBuilder Pro software. The device supports standard-mode (100 kHz) and fast-mode (400 kHz) I²C operation, and the SCL/SDA pins include internal pull-ups compatible with 3.3 V bus levels. SI5338M-B04405-GMR also responds to SMBus Alert commands on the INTR pin.

Does SI5338M-B04405-GMR support PCIe Gen 4 Separate Reference No Spread (SRNS) mode?

Yes, SI5338M-B04405-GMR supports PCIe Gen 4 SRNS mode with 0.11–0.32 ps RMS jitter (typical), verified per PCI-SIG specification using a 2–5 MHz PLL bandwidth and 10 MHz CDR filter. This mode requires configuring the device for external reference feedback and disabling spread spectrum. SI5338M-B04405-GMR achieves this performance using its low-noise VCO and optimized loop filter settings stored in OTP.

Can SI5338M-B04405-GMR generate frequencies above 350 MHz on all four outputs simultaneously?

No. SI5338M-B04405-GMR supports up to two unique frequencies above 350 MHz simultaneously - specifically Fvco/4 and Fvco/6 - due to VCO frequency constraints. Outputs above 350 MHz must use LVPECL, LVDS, or CML formats. For example, it can deliver 473.33 MHz and 710 MHz concurrently, but not four distinct >350 MHz frequencies. SI5338M-B04405-GMR's datasheet explicitly limits simultaneous high-frequency outputs to preserve jitter performance and synthesis accuracy.

How is the crystal load capacitance configured for SI5338M-B04405-GMR?

SI5338M-B04405-GMR supports on-chip crystal load capacitance of 11–13 pF (adjustable via registers) for crystals from 8–30 MHz. Recommended external crystal CL is 17–19 pF. Configuration is performed using ClockBuilder Pro, which auto-calculates register values based on measured crystal parameters. SI5338M-B04405-GMR's AN360 application note provides detailed guidance for tuning CL and drive level to ensure reliable startup and aging stability.

What power supply sequencing is required for SI5338M-B04405-GMR?

SI5338M-B04405-GMR has no strict power supply sequencing requirement between VDD (core) and VDDOx (output buffers). All supplies may be ramped simultaneously or in any order. However, VDD must be stable before I²C communication begins. The device incorporates internal POR circuitry that holds outputs in high-impedance until VDD reaches 1.6 V and remains stable for >100 µs. SI5338M-B04405-GMR's 24-QFN package includes an exposed thermal pad that must be soldered to a solid ground plane for thermal and electrical stability.

SI5338M-B04405-GMR Specifications

Product attributes: Attribute value

Manufacturer:: Skyworks Solutions Inc.

Series:: MultiSynth™

Package/Case:: 24-VFQFN Exposed Pad

Packaging:: Tape & Reel (TR)

Product Status:: Active

Programmable:: Not Verified

PLL:: -

Main Purpose:: -

Input:: -

Output:: -

Number of Circuits:: -

Ratio - Input:Output:: -

Differential - Input:Output:: -

Frequency - Max:: -

Voltage - Supply:: -

Operating Temperature:: -

Mounting Type:: Surface Mount

Grade:: -

Qualification:: -

Supplier Device Package:: 24-QFN (4x4)

SI5338M-B04405-GMR FAQ

1.How can I place an order for SI5338M-B04405-GMR through Aetrix?

Please submit a Request for Quotation (RFQ) for SI5338M-B04405-GMR on Aetrix. Our sales agent will provide a competitive quotation and guide you through the order confirmation once you accept the terms.

2.Are the price and stock information for SI5338M-B04405-GMR reliable?

The price and inventory of SI5338M-B04405-GMR are updated periodically and may fluctuate due to market conditions. Stock and pricing data are typically refreshed every 24 hours. Quotation validity for SI5338M-B04405-GMR is usually 5 days.

3.What payment methods are accepted for SI5338M-B04405-GMR?

We accept Wire Transfer, PayPal, Credit Card, Western Union, MoneyGram, and Escrow for SI5338M-B04405-GMR transactions.

Note: Certain payment methods may incur a processing fee.

4.How is shipping managed for SI5338M-B04405-GMR?

SI5338M-B04405-GMR orders can be shipped via leading logistics carriers, including DHL, UPS, FedEx, TNT, or Registered Mail.

Once your SI5338M-B04405-GMR order is processed, you will receive an email with the shipment details and tracking number.

Note: Tracking information may take up to 24 hours to appear. Express delivery typically takes 3–5 business days.

5.How can I obtain technical support or documentation for SI5338M-B04405-GMR?

For technical support, including SI5338M-B04405-GMR datasheets, pinout diagrams, or application guidance, please contact our engineering support team. They can provide detailed documentation and assistance for your SI5338M-B04405-GMR requirements.

6.How does Aetrix verify that SI5338M-B04405-GMR is sourced from the original manufacturer or authorized distributors?

All SI5338M-B04405-GMR products on Aetrix are procured from qualified distributors and authorized channels. Our dedicated quality assurance team conducts strict verification, including traceability checks and, if necessary, third-party testing. This ensures that SI5338M-B04405-GMR meets industry standards.

7.What is the process for return or replacement of SI5338M-B04405-GMR?

All SI5338M-B04405-GMR units undergo pre-shipment inspection (PSI). If there is an issue with SI5338M-B04405-GMR, returns or replacements are accepted under the following conditions:

1.Quantity discrepancies, incorrect items, or visible external defects (such as breakage or corrosion), acknowledged by Aetrix.

2.The issue is reported within 90 days of delivery.

3.The SI5338M-B04405-GMR part is unused and in its original packaging.

Return procedure for SI5338M-B04405-GMR:

1.Submit a request within 90 days.

2.Obtain a Return Material Authorization (RMA) from Aetrix.

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