Skyworks Solutions Inc. SI5338M-B04505-GM
- Part No.:
- SI5338M-B04505-GM
- Manufacturer:
- Skyworks Solutions Inc.
- Category:
- Application Specific Clock/Timing
- Package:
- 24-VFQFN Exposed Pad
- Datasheet:
-
SI5338M-B04505-GM.pdf
- Description:
- I2C CONTROL, 4-OUTPUT, ANY FREQU
- Quantity:
- Payment:

- Shipping:

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Product details
Overview
SI5338M-B04505-GM from Skyworks Solutions is a quad-output, I²C-programmable clock generator with MultiSynth™ frequency synthesis. It delivers four independent, any-frequency outputs (0.16–710 MHz) with 0.7 ps RMS phase jitter, PCIe Gen 1–4 Common Clock and Gen 3 SRNS compliance, and support for LVPECL/LVDS/HCSL/CMOS/SSTL/HSTL signal formats across 1.5–3.3 V output supplies. It serves as a drop-in replacement for up to four crystal oscillators in high-speed serial interface timing.
For engineers reviewing the SI5338M-B04505-GM datasheet, SI5338M-B04505-GM pinout, SI5338M-B04505-GM application, or SI5338M-B04505-GM equivalent, key selection criteria include differential output jitter performance at PCIe Gen 4, independent per-output voltage configuration, spread-spectrum control range (0.5–5.0%), and I²C-based field reprogramming capability without hardware changes.
Technical Context
The SI5338M-B04505-GM implements a two-stage PLL architecture: a high-stability input stage locking to external references (crystal, CMOS, or differential inputs), followed by four independent MultiSynth™ fractional-N synthesizers. Each synthesizer drives one of four configurable output drivers, enabling true zero-ppm frequency accuracy on all outputs simultaneously.
It supports flexible reference inputs (8–30 MHz crystal, 5–710 MHz differential), independent output voltage selection (1.5/1.8/2.5/3.3 V per driver), and glitchless frequency/phase adjustment via dedicated pins or I²C - with 1 ppm frequency step resolution and <20 ps phase step accuracy.
Key Specifications
| Parameter | Value and Actual Design Meaning |
|---|---|
| Output Count | Four independent differential or single-ended clock outputs (CLK0A/B through CLK3A/B) |
| Phase Jitter (RMS) | 0.7 ps typical (12 kHz–20 MHz); meets PCIe Gen 4 common clock jitter spec (≤0.45 ps RMS) |
| Frequency Range | 0.16–710 MHz per output; supports LVPECL/LVDS (≤710 MHz), HCSL (≤250 MHz), CMOS (≤200 MHz) |
| Input Reference | Crystal (8–30 MHz), CMOS (5–200 MHz), SSTL/HSTL (5–350 MHz), differential (5–710 MHz) |
| Supply Voltages | Core: 1.8/2.5/3.3 V; Output buffers: independently configurable 1.5/1.8/2.5/3.3 V per driver |
| Package | 24-pin QFN, 4 mm × 4 mm, 0.5 mm pitch, exposed thermal pad |
| Operating Temp | –40 °C to +85 °C ambient; qualified for industrial and telecom line card environments |
Pinout & Package
SI5338M-B04505-GM is housed in a 24-lead, 4 mm × 4 mm QFN package with wettable flanks and an exposed thermal pad. Pin 1 is top-left corner (IN1), pin 24 is bottom-right (GND). The package supports standard reflow profiles and requires controlled impedance routing for differential pairs.
| Pin/Terminal | Circuit Role | Design Meaning |
|---|---|---|
| IN1, IN2 | Differential reference input pair | Accepts 5–710 MHz AC-coupled differential clocks; internal 100 Ω termination enabled |
| IN3, IN4 | Single-ended reference inputs | Support CMOS/SSTL/HSTL signals (5–350 MHz); 20 kΩ internal pull-up/pull-down selectable |
| CLK0A–CLK3B | Differential clock outputs (4 pairs) | Each pair independently configurable for LVPECL/LVDS/HCSL/CML; 22 Ω series resistors integrated |
| VDDO0–VDDO3 | Output buffer supply rails | Separate 1.5/1.8/2.5/3.3 V supplies per output bank; enables mixed-voltage system interfacing |
| SCL, SDA | I²C/SMBus programming interface | Standard 100 kHz / 400 kHz operation; supports multi-device addressing and register read/write |
| INTR | Interrupt output | Open-drain status indicator for loss-of-lock (LOL) and loss-of-signal (LOS) events |
Key Features
| Feature | Design Value |
|---|---|
| MultiSynth™ synthesis | Four independent fractional-N synthesizers enable simultaneous zero-ppm precision outputs at arbitrary frequencies |
| PCIe Gen 4 compliance | Meets PCIe Base Spec 4.0 common clock jitter requirement (≤0.45 ps RMS, 10 kHz–50 MHz) |
| Independent output voltage control | Each of four output banks powered separately (1.5/1.8/2.5/3.3 V), eliminating level-shifter ICs in mixed-voltage designs |
| Glitchless frequency tuning | Pin-controlled frequency increment/decrement in 1 ppm steps with ≤667 ns update time above 18 MHz |
| Programmable spread spectrum | Configurable SSC on any output: 0.5–5.0% spread, 33–63 kHz modulation rate, no firmware change required |
| Zero-delay mode support | External feedback path enables synchronous clock distribution with matched input-to-output propagation delay (2.5–4 ns) |
Applications
| PCIe Gen 4 Switch Timing | Ethernet Switch Clocking |
|---|---|
Use Scenario: High-density 32-lane PCIe Gen 4 switch ASIC requiring four synchronized, low-jitter reference clocks for SerDes lanes and management logic. IC Role / Device Role / Timing Role: Primary clock generator providing four independent 100 MHz HCSL clocks with sub-0.45 ps RMS jitter and matched skew (<100 ps). Use Value: Eliminates need for four discrete oscillators and external jitter cleaners while meeting PCIe Gen 4 CDR jitter mask requirements. |
Use Scenario: 10 GbE/25 GbE Ethernet switch fabric with multiple PHYs and MACs needing synchronized clocks across different voltage domains. IC Role / Device Role / Timing Role: Quad-output timing source delivering 156.25 MHz LVDS (PHY), 125 MHz CMOS (MAC), 250 MHz HCSL (PCS), and 100 MHz LVPECL (control plane) from one device. Use Value: Reduces BOM count and PCB area by consolidating four clock sources into a single 4×4 mm QFN with per-output voltage and format control. |
| Broadcast Video Sync Generator | FPGA-Based Telecom Line Card |
Use Scenario: SMPTE ST 2082/2110 video transport system requiring precise 27 MHz, 74.25 MHz, 148.5 MHz, and 297 MHz clocks with sub-1 ps RMS jitter. IC Role / Device Role / Timing Role: Any-frequency clock synthesizer generating exact broadcast-standard frequencies with programmable phase alignment across outputs. Use Value: Enables frame-accurate synchronization across SDI, HDMI, and IP video paths without custom crystal sets or external dividers. |
Use Scenario: Carrier-grade PON/DSLAM line card with FPGA, DSP, and analog front-end requiring multiple domain-specific clocks (e.g., 122.88 MHz for JESD204B, 155.52 MHz for SONET, 100 MHz for PCIe, 25 MHz for management). IC Role / Device Role / Timing Role: Reconfigurable clock hub supporting hot-swappable firmware updates via I²C to adapt to varying line card configurations. Use Value: Simplifies inventory and field upgrades - same SI5338M-B04505-GM part number supports multiple line card SKUs via software-defined clocking. |
Equivalent & Alternatives
The following parts are listed as comparable options for similar quad-output programmable clock generator applications.
| Alternative Part | Technical Difference | Application Difference | Selection Advice |
|---|---|---|---|
| Si5332A-D05589-GM | Higher integration: includes integrated crystal, lower power (32 mA typ), but fixed 4-output LVDS-only; no HCSL/LVPECL support | Best suited for space-constrained, crystal-free LVDS-only systems where HCSL/LVPECL drive strength is unnecessary | Select when board area and BOM count are prioritized over output format flexibility and external crystal control |
| ICS854S01AGI-01LFT | Non-programmable, fixed-frequency quad LVDS generator; 1.2 ps RMS jitter; no I²C interface or frequency agility | Applicable only in stable, unchanging clock tree designs with known fixed frequencies and no field tuning needs | Select only for cost-sensitive, static clocking where reprogrammability and jitter margin are secondary to unit price |
Compared with Si5332A-D05589-GM and ICS854S01AGI-01LFT, the SI5338M-B04505-GM uniquely balances field-reprogrammability, multi-format output flexibility, and PCIe Gen 4 jitter compliance - making it optimal for evolving high-speed serial interface platforms requiring hardware reuse across generations.
Availability
SI5338M-B04505-GM is available at Aetrix Electronics and suitable for PCIe Gen 4 switch timing, Ethernet switch clocking, broadcast video sync generation, and FPGA-based telecom line card applications requiring stable component supply, long-term lifecycle assurance, and traceable sourcing.
Supply support for SI5338M-B04505-GM includes scheduled delivery planning, volume procurement assistance, BOM continuity management, traceable sourcing, and lifecycle availability coordination for OEM customers, industrial embedded developers, connected-device designers, and electronics production programs.
Manufacturer
Skyworks Solutions is a global leader in high-performance analog semiconductors, specializing in RF, timing, and connectivity solutions for infrastructure, automotive, and mobile markets.
The SI5338 family was designed for high-speed serial interface timing in datacenter, telecom, and broadcast equipment - delivering programmable, low-jitter clock synthesis in compact packages with robust industrial temperature operation.
FAQ
What is the maximum output frequency supported by SI5338M-B04505-GM in LVPECL mode?
The SI5338M-B04505-GM supports LVPECL outputs up to 710 MHz, as confirmed in Table 6 of the datasheet. This applies when using differential outputs with proper 100 Ω termination and VDDO ≥ 2.5 V. Operation above 350 MHz is limited to two unique frequencies simultaneously (Fvco/4 and Fvco/6) due to VCO constraints within the MultiSynth™ architecture.
Does SI5338M-B04505-GM support PCIe Gen 4 Separate Reference No Spread (SRNS) mode?
Yes, the SI5338M-B04505-GM is explicitly compliant with PCIe Gen 3 SRNS and Gen 4 Common Clock specifications. Its measured RMS jitter is ≤0.32 ps (Gen 3 SRNS) and ≤0.45 ps (Gen 4 Common Clock) under specified test conditions (PLL BW 2–5 MHz, CDR = 10 MHz), satisfying PCI-SIG requirements per Table 12.
Can SI5338M-B04505-GM generate four different output voltages simultaneously?
Yes - SI5338M-B04505-GM provides four independent VDDO supply pins (VDDO0–VDDO3), each configurable for 1.5 V, 1.8 V, 2.5 V, or 3.3 V. This allows concurrent LVPECL (3.3 V), LVDS (2.5 V), HCSL (1.8 V), and CMOS (1.5 V) outputs without external level shifters, as verified in the "Output Stage" section and Table 3 DC characteristics.
Is an external crystal required for SI5338M-B04505-GM operation?
No - SI5338M-B04505-GM accepts multiple reference types: external 8–30 MHz crystal (differential), CMOS (5–200 MHz), SSTL/HSTL (5–350 MHz), or differential inputs (5–710 MHz). Crystal use is optional; the device operates fully with a clean external clock on IN1/IN2 or IN3/IN4, enabling crystal-free designs where timing stability permits.
How is SI5338M-B04505-GM programmed in-system?
The SI5338M-B04505-GM is programmed via its I²C/SMBus-compatible interface (SCL/SDA pins) using Skyworks' ClockBuilder Pro software. Configuration can be performed during manufacturing or in-field via microcontroller host, with nonvolatile memory (OTP) storing settings for automatic boot-up. Pin-based frequency/phase control is also supported for real-time dynamic tuning.
SI5338M-B04505-GM Specifications
- Product attributes
- Attribute value
- Manufacturer:
- Skyworks Solutions Inc.
- Series:
- MultiSynth™
- Package/Case:
- 24-VFQFN Exposed Pad
- Packaging:
- Tray
- Product Status:
- Active
- Programmable:
- Not Verified
- PLL:
- -
- Main Purpose:
- -
- Input:
- -
- Output:
- -
- Number of Circuits:
- -
- Ratio - Input:Output:
- -
- Differential - Input:Output:
- -
- Frequency - Max:
- -
- Voltage - Supply:
- -
- Operating Temperature:
- -
- Mounting Type:
- Surface Mount
- Grade:
- -
- Qualification:
- -
- Supplier Device Package:
- 24-QFN (4x4)
SI5338M-B04505-GM FAQ
1.How can I place an order for SI5338M-B04505-GM through Aetrix?
Please submit a Request for Quotation (RFQ) for SI5338M-B04505-GM on Aetrix. Our sales agent will provide a competitive quotation and guide you through the order confirmation once you accept the terms.
2.Are the price and stock information for SI5338M-B04505-GM reliable?
The price and inventory of SI5338M-B04505-GM are updated periodically and may fluctuate due to market conditions. Stock and pricing data are typically refreshed every 24 hours. Quotation validity for SI5338M-B04505-GM is usually 5 days.
3.What payment methods are accepted for SI5338M-B04505-GM?
We accept Wire Transfer, PayPal, Credit Card, Western Union, MoneyGram, and Escrow for SI5338M-B04505-GM transactions.
Note: Certain payment methods may incur a processing fee.
4.How is shipping managed for SI5338M-B04505-GM?
SI5338M-B04505-GM orders can be shipped via leading logistics carriers, including DHL, UPS, FedEx, TNT, or Registered Mail.
Once your SI5338M-B04505-GM order is processed, you will receive an email with the shipment details and tracking number.
Note: Tracking information may take up to 24 hours to appear. Express delivery typically takes 3–5 business days.
5.How can I obtain technical support or documentation for SI5338M-B04505-GM?
For technical support, including SI5338M-B04505-GM datasheets, pinout diagrams, or application guidance, please contact our engineering support team. They can provide detailed documentation and assistance for your SI5338M-B04505-GM requirements.
6.How does Aetrix verify that SI5338M-B04505-GM is sourced from the original manufacturer or authorized distributors?
All SI5338M-B04505-GM products on Aetrix are procured from qualified distributors and authorized channels. Our dedicated quality assurance team conducts strict verification, including traceability checks and, if necessary, third-party testing. This ensures that SI5338M-B04505-GM meets industry standards.
7.What is the process for return or replacement of SI5338M-B04505-GM?
All SI5338M-B04505-GM units undergo pre-shipment inspection (PSI). If there is an issue with SI5338M-B04505-GM, returns or replacements are accepted under the following conditions:
1.Quantity discrepancies, incorrect items, or visible external defects (such as breakage or corrosion), acknowledged by Aetrix.
2.The issue is reported within 90 days of delivery.
3.The SI5338M-B04505-GM part is unused and in its original packaging.
Return procedure for SI5338M-B04505-GM:
1.Submit a request within 90 days.
2.Obtain a Return Material Authorization (RMA) from Aetrix.
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