Send an Inquiry

To receive a quote for your project, please fill in the following information, and we’ll get back to you promptly.

Submit Inventory List

Please fill in the following information, and we’ll get back to you promptly.

Home > Products > Integrated Circuits (ICs) > Clock/Timing > Application Specific Clock/Timing

Skyworks Solutions Inc. SI5338M-B04505-GMR

Name: SI5338M-B04505-GMR
Brand: Skyworks Solutions Inc.
SKU: SI5338M-B04505-GMR
Price: 2.40 USD
Availability: InStock
Rating: 5 (2 reviews)

Compare

Part No.:: SI5338M-B04505-GMR

Manufacturer:: Skyworks Solutions Inc.

Category:: Application Specific Clock/Timing

Package:: 24-VFQFN Exposed Pad

Datasheet:: SI5338M-B04505-GMR.pdf

Description:: I2C CONTROL, 4-OUTPUT, ANY FREQU

Quantity:: RFQ Add To RFQ list

Payment:

Shipping:

Inventory:2,865

Please send an inquiry. Send us your inquiry, and we will respond immediately.

Product details

Overview

SI5338M-B04505-GMR from Skyworks Solutions is an I²C-programmable quad clock generator with four independently configurable differential or single-ended outputs, 0.7 ps RMS typical phase jitter, PCIe Gen 1–4 Common Clock and Gen 3 SRNS compliance, and operation across –40 to +85 °C. It replaces up to four crystal oscillators in high-speed serial interface timing applications such as PCIe root complexes and FPGA clock trees.

For engineers reviewing the SI5338M-B04505-GMR datasheet, SI5338M-B04505-GMR pinout, SI5338M-B04505-GMR application, or SI5338M-B04505-GMR equivalent, key selection considerations include its MultiSynth™ fractional-N synthesis architecture, independent output voltage per driver (1.5/1.8/2.5/3.3 V), 0 ppm frequency accuracy on all outputs, and support for LVPECL/LVDS/HCSL/CMOS/SSTL/HSTL formats up to 710 MHz.

Technical Context

The SI5338M-B04505-GMR implements a two-stage PLL architecture: a high-stability integer-N Phase-Locked Loop (Stage 1) locks to one of six input references (crystal, CMOS, SSTL/HSTL, or differential), followed by four independent MultiSynth™ fractional-N synthesis blocks (Stage 2) generating each output. Each output supports programmable phase offset (<20 ps step resolution), glitchless frequency increment/decrement in 1 ppm steps, and spread-spectrum modulation (0.5–5.0% spread, 33–63 kHz rate).

It features loss-of-lock and loss-of-signal alarms, external feedback mode for zero-delay operation, and I²C/SMBus-compatible configuration via 24-bit address space. The device uses on-chip OTP NVM for factory programming and supports dynamic reconfiguration without reset.

Key Specifications

Parameter	Value and Actual Design Meaning
Phase Jitter (RMS)	0.7 ps - meets PCIe Gen 3 SRNS and Gen 4 Common Clock jitter requirements at 100 MHz HCSL output
Output Frequency Range	0.16–710 MHz - supports LVPECL/LVDS up to 710 MHz, HCSL up to 250 MHz, CMOS up to 200 MHz
Input Reference Support	8–30 MHz crystal, 5–200 MHz CMOS, 5–350 MHz SSTL/HSTL, 5–710 MHz differential - enables flexible system clock sourcing
Supply Voltages	VDD = 1.8/2.5/3.3 V ±10%; VDDOx = 1.4–3.63 V - allows independent output voltage per driver for mixed-voltage board designs
Operating Temperature	–40 to +85 °C - qualified for industrial and telecom line card environments
Core Supply Current	45 mA typ at 100 MHz on all outputs - enables low-power clocking in dense FPGA/ASIC systems
Package	24-pin QFN, 4 × 4 mm - space-efficient footprint compatible with automated SMT assembly

Pinout & Package

SI5338M-B04505-GMR is housed in a 24-lead, 4 × 4 mm QFN package with exposed thermal pad. Pin assignments follow the standard Si5338 top-view layout: IN1/IN2 (differential ref 1), IN3/IN4 (single-ended ref 2), IN5/IN6 (differential ref 3), CLK0A/CLK0B through CLK3A/CLK3B (four differential output pairs), VDDO0–VDDO3 (independent output supply pins), VDD (core supply), SCL/SDA (I²C interface), INTR (interrupt output), and RSVD_GND (reserved ground).

Pin/Terminal	Circuit Role	Design Meaning
CLK0A / CLK0B	Differential Output Pair 0	LVPECL/LVDS/HCSL/CML-capable; independently configured frequency, format, and VDDO0 voltage
CLK1A / CLK1B	Differential Output Pair 1	Same configurability as CLK0; supports phase alignment with CLK0 via programmable offset
CLK2A / CLK2B	Differential Output Pair 2	Independent MultiSynth™ channel; supports SSC modulation and glitchless frequency tuning
CLK3A / CLK3B	Differential Output Pair 3	Full feature set including loss-of-signal detection and programmable drive strength
IN1 / IN2	Differential Input 1	Accepts 5–710 MHz reference; internal 100 Ω termination enabled; supports crystal oscillator mode (8–30 MHz)
IN3 / IN4	Single-Ended Input 2	CMOS-compatible; 5–200 MHz range; VIH/VIL thresholds scale with VDD
SCL / SDA	I²C Serial Interface	Standard 100/400 kHz operation; supports multi-master bus; pull-up required externally
INTR	Interrupt Output	Open-drain status flag indicating loss-of-lock, loss-of-signal, or register write completion
VDDO0–VDDO3	Output Buffer Supplies	Each powers one output pair; allows mixed-signal board interfacing (e.g., 1.8 V FPGA + 3.3 V PHY)
VDD	Core Supply	Powers PLL, MultiSynth™ engines, and logic; accepts 1.8/2.5/3.3 V with ±10% tolerance

Key Features

Feature	Design Value
MultiSynth™ Any-Frequency Synthesis	Four independent outputs each synthesize any frequency from 0.16 to 710 MHz with true zero ppm accuracy
PCIe Gen 1–4 Compliance	Fully compliant with PCIe Gen 1/2/3 Common Clock and Gen 3 Separate Reference No Spread (SRNS) jitter specs
Programmable Phase Offset	±45 ns range with <20 ps step resolution per output - enables precise skew control across high-speed SerDes lanes
Glitchless Frequency Tuning	Independent 1 ppm-step increment/decrement per output via pin or I²C - no output interruption during dynamic frequency adjustment
Flexible Spread Spectrum	Configurable on any output: 0.5–5.0% spread depth, 33–63 kHz modulation rate - reduces EMI without affecting timing margin
Zero-Delay Mode Support	External feedback path enables synchronous clock distribution with minimal propagation delay - critical for deterministic latency in real-time systems

Applications

PCIe Root Complex Timing	FPGA/ASIC Clock Tree
Use Scenario: Providing synchronized 100 MHz REFCLK to multiple PCIe endpoints and switches in a server motherboard. IC Role / Device Role / Timing Role: Quad-output clock generator delivering four independent, low-jitter PCIe-compliant reference clocks with matched phase alignment. Use Value: Eliminates need for four discrete oscillators; ensures Gen 3 SRNS and Gen 4 jitter compliance across all slots via single-point calibration.	Use Scenario: Distributing multiple clock domains (e.g., 250 MHz fabric, 125 MHz transceiver, 50 MHz management, 10 MHz debug) from a single FPGA design. IC Role / Device Role / Timing Role: Programmable clock source enabling dynamic reconfiguration of clock frequencies and formats without hardware change. Use Value: Reduces BOM count and PCB area; supports post-silicon validation and field firmware updates to clock tree parameters.
Ethernet Switch Line Card	Broadcast Video Timing
Use Scenario: Generating 156.25 MHz, 312.5 MHz, and 625 MHz clocks for 1G/10G/25G Ethernet PHYs and MACs on a telecom line card. IC Role / Device Role / Timing Role: High-precision frequency translator converting a common 25 MHz crystal reference into multiple SerDes line rates. Use Value: Achieves sub-1 ps RMS jitter required for 25G KR compliance; supports mixed-voltage PHY interfaces via independent VDDO supplies.	Use Scenario: Synchronizing frame-locked audio/video processing pipelines in broadcast equipment using SMPTE 2082/2081 timing standards. IC Role / Device Role / Timing Role: Low-phase-noise clock synthesizer generating 74.25 MHz, 148.5 MHz, and 297 MHz video sample clocks with tight inter-output skew. Use Value: Enables sub-100 ps output-to-output skew for multi-channel video capture/playback; meets SMPTE ST 2082-1 jitter limits.

PCIe Root Complex Timing

FPGA/ASIC Clock Tree

Use Scenario: Providing synchronized 100 MHz REFCLK to multiple PCIe endpoints and switches in a server motherboard.

IC Role / Device Role / Timing Role: Quad-output clock generator delivering four independent, low-jitter PCIe-compliant reference clocks with matched phase alignment.

Use Value: Eliminates need for four discrete oscillators; ensures Gen 3 SRNS and Gen 4 jitter compliance across all slots via single-point calibration.

Use Scenario: Distributing multiple clock domains (e.g., 250 MHz fabric, 125 MHz transceiver, 50 MHz management, 10 MHz debug) from a single FPGA design.

IC Role / Device Role / Timing Role: Programmable clock source enabling dynamic reconfiguration of clock frequencies and formats without hardware change.

Use Value: Reduces BOM count and PCB area; supports post-silicon validation and field firmware updates to clock tree parameters.

Ethernet Switch Line Card

Broadcast Video Timing

Use Scenario: Generating 156.25 MHz, 312.5 MHz, and 625 MHz clocks for 1G/10G/25G Ethernet PHYs and MACs on a telecom line card.

IC Role / Device Role / Timing Role: High-precision frequency translator converting a common 25 MHz crystal reference into multiple SerDes line rates.

Use Value: Achieves sub-1 ps RMS jitter required for 25G KR compliance; supports mixed-voltage PHY interfaces via independent VDDO supplies.

Use Scenario: Synchronizing frame-locked audio/video processing pipelines in broadcast equipment using SMPTE 2082/2081 timing standards.

IC Role / Device Role / Timing Role: Low-phase-noise clock synthesizer generating 74.25 MHz, 148.5 MHz, and 297 MHz video sample clocks with tight inter-output skew.

Use Value: Enables sub-100 ps output-to-output skew for multi-channel video capture/playback; meets SMPTE ST 2082-1 jitter limits.

Equivalent & Alternatives

The following parts are listed as comparable options for similar quad-output clock generator applications.

Alternative Part	Technical Difference	Application Difference	Selection Advice
Si5332A-A05505-GM	Higher integration: includes integrated crystal, smaller 3 × 3 mm package, lower 0.35 ps RMS jitter, but only three outputs	Best for space-constrained designs requiring ultra-low jitter and crystal integration; not suitable when four independent outputs are mandatory	Select SI5338M-B04505-GMR when four fully independent outputs with independent VDDO supplies and full MultiSynth™ configurability are required
ICS853S01AG-01LF	Fixed-frequency, non-programmable quad LVDS buffer; no synthesis capability; 0.9 ps RMS jitter; 16-pin TSSOP	Only suitable for fixed-ratio fanout or translation from existing clocks; cannot generate arbitrary frequencies	Choose SI5338M-B04505-GMR when any-frequency synthesis, I²C programmability, or PCIe SRNS compliance is needed

Compared with Si5332A-A05505-GM and ICS853S01AG-01LF, SI5338M-B04505-GMR uniquely delivers four independently synthesized, voltage-configurable outputs with PCIe Gen 4 Common Clock compliance and field-upgradable timing parameters - making it optimal for complex, multi-standard timing architectures where flexibility and future-proofing outweigh minimal size or jitter advantages.

Availability

SI5338M-B04505-GMR is available at Aetrix Electronics and suitable for PCIe Gen 4 switch designs, FPGA-based test equipment, and telecom line cards requiring stable component supply, long-term lifecycle support, and guaranteed traceable sourcing.

Supply support for SI5338M-B04505-GMR includes scheduled delivery planning, volume procurement assistance, BOM continuity management, traceable sourcing, and lifecycle availability coordination for OEM customers, industrial embedded developers, connected-device designers, and electronics production programs.

Manufacturer

Skyworks Solutions is a global semiconductor company specializing in analog and mixed-signal connectivity solutions, with leadership in RF, timing, and power management ICs for infrastructure, automotive, and mobile markets.

The Si5338 product line was designed specifically for high-performance, multi-protocol clock generation in data center, networking, and broadcast video systems - emphasizing low jitter, software-defined flexibility, and robust industrial qualification.

FAQ

What is the maximum output frequency supported by SI5338M-B04505-GMR in LVPECL format?

The SI5338M-B04505-GMR supports LVPECL output frequencies up to 710 MHz, as confirmed in Table 6 of the official datasheet. This capability applies when operating in MultiSynth™ synthesis mode with appropriate VDDO supply (2.5 V or 3.3 V) and load termination. Frequencies above 350 MHz require use of Fvco/4 or Fvco/6 synthesis paths, limiting simultaneous high-frequency outputs to two unique values.

Does SI5338M-B04505-GMR support PCIe Gen 4 timing requirements?

Yes, SI5338M-B04505-GMR meets PCIe Gen 4 Common Clock jitter specifications with ≤0.45 ps RMS (10 kHz–50 MHz band), as verified in Table 12 of the datasheet. It also satisfies Gen 3 Separate Reference No Spread (SRNS) requirements at ≤0.32 ps RMS and supports the required PLL bandwidth (2–5 MHz) and CDR frequency (10 MHz) for compliance testing.

How many independent supply voltages can be applied to the outputs of SI5338M-B04505-GMR?

SI5338M-B04505-GMR supports four independent output supply voltages via dedicated VDDO0, VDDO1, VDDO2, and VDDO3 pins. Each can be set to 1.5 V, 1.8 V, 2.5 V, or 3.3 V, enabling direct interfacing with mixed-voltage components such as 1.8 V FPGAs, 2.5 V SerDes PHYs, and 3.3 V legacy peripherals without level shifters.

Can SI5338M-B04505-GMR generate different frequencies on all four outputs simultaneously?

Yes, SI5338M-B04505-GMR uses four independent MultiSynth™ synthesis blocks to generate any frequency from 0.16 to 710 MHz on each of its four outputs - with true zero ppm precision and no shared dividers. This enables concurrent generation of, for example, 100 MHz (PCIe), 156.25 MHz (Ethernet), 297 MHz (video), and 50 MHz (management) from a single 25 MHz crystal reference.

What development tools are available for configuring SI5338M-B04505-GMR?

Skyworks provides ClockBuilder Pro software for intuitive GUI-based configuration of SI5338M-B04505-GMR - supporting frequency planning, jitter analysis, register export, and .hex file generation for OTP programming. The PCIe Clock Jitter Tool is also available for rapid compliance validation. Both tools are free and downloadable from the official Skyworks website.

SI5338M-B04505-GMR Specifications

Product attributes: Attribute value

Manufacturer:: Skyworks Solutions Inc.

Series:: MultiSynth™

Package/Case:: 24-VFQFN Exposed Pad

Packaging:: Tape & Reel (TR)

Product Status:: Active

Programmable:: Not Verified

PLL:: -

Main Purpose:: -

Input:: -

Output:: -

Number of Circuits:: -

Ratio - Input:Output:: -

Differential - Input:Output:: -

Frequency - Max:: -

Voltage - Supply:: -

Operating Temperature:: -

Mounting Type:: Surface Mount

Grade:: -

Qualification:: -

Supplier Device Package:: 24-QFN (4x4)

SI5338M-B04505-GMR FAQ

1.How can I place an order for SI5338M-B04505-GMR through Aetrix?

Please submit a Request for Quotation (RFQ) for SI5338M-B04505-GMR on Aetrix. Our sales agent will provide a competitive quotation and guide you through the order confirmation once you accept the terms.

2.Are the price and stock information for SI5338M-B04505-GMR reliable?

The price and inventory of SI5338M-B04505-GMR are updated periodically and may fluctuate due to market conditions. Stock and pricing data are typically refreshed every 24 hours. Quotation validity for SI5338M-B04505-GMR is usually 5 days.

3.What payment methods are accepted for SI5338M-B04505-GMR?

We accept Wire Transfer, PayPal, Credit Card, Western Union, MoneyGram, and Escrow for SI5338M-B04505-GMR transactions.

Note: Certain payment methods may incur a processing fee.

4.How is shipping managed for SI5338M-B04505-GMR?

SI5338M-B04505-GMR orders can be shipped via leading logistics carriers, including DHL, UPS, FedEx, TNT, or Registered Mail.

Once your SI5338M-B04505-GMR order is processed, you will receive an email with the shipment details and tracking number.

Note: Tracking information may take up to 24 hours to appear. Express delivery typically takes 3–5 business days.

5.How can I obtain technical support or documentation for SI5338M-B04505-GMR?

For technical support, including SI5338M-B04505-GMR datasheets, pinout diagrams, or application guidance, please contact our engineering support team. They can provide detailed documentation and assistance for your SI5338M-B04505-GMR requirements.

6.How does Aetrix verify that SI5338M-B04505-GMR is sourced from the original manufacturer or authorized distributors?

All SI5338M-B04505-GMR products on Aetrix are procured from qualified distributors and authorized channels. Our dedicated quality assurance team conducts strict verification, including traceability checks and, if necessary, third-party testing. This ensures that SI5338M-B04505-GMR meets industry standards.

7.What is the process for return or replacement of SI5338M-B04505-GMR?

All SI5338M-B04505-GMR units undergo pre-shipment inspection (PSI). If there is an issue with SI5338M-B04505-GMR, returns or replacements are accepted under the following conditions:

1.Quantity discrepancies, incorrect items, or visible external defects (such as breakage or corrosion), acknowledged by Aetrix.

2.The issue is reported within 90 days of delivery.

3.The SI5338M-B04505-GMR part is unused and in its original packaging.

Return procedure for SI5338M-B04505-GMR:

1.Submit a request within 90 days.

2.Obtain a Return Material Authorization (RMA) from Aetrix.

Tech Hub

2026-09-09 Counterfeit Electronic Components: How to Detect, Authenticate, and Test Suspect Parts

Counterfeit components can hide behind convincing markings and passing basic function tests. This engineering reference covers source traceability, external inspection, X-ray, XRF, electrical testing, …

2026-09-08 Obsolete Electronic Components: How to Source and Evaluate Replacements

A practical engineering and sourcing framework covering lifecycle verification, lifetime-buy calculations, replacement qualification, supplier checks and counterfeit-risk controls.

2026-09-07 TTL vs CMOS Logic Levels: 74HC and 74HCT Compatibility Explained

TTL and CMOS logic families differ in thresholds, loading, output drive, power and timing. This engineering guide compares 74HC and 74HCT, calculates noise margins and checks 3.3 V/5 V compatibility.

2026-09-04 Logic Level Shifter: How to Connect 3.3V and 5V Logic Safely

A practical engineering guide to 3.3V and 5V logic compatibility, input thresholds, resistor dividers, translator ICs, MOSFET level shifting, I2C pull-ups, timing limits and power-sequencing risks.

2026-09-03 74HC595 vs TPIC6B595: Output Drive, Pinout, Current, and Load Selection

The 74HC595 uses push-pull logic outputs, while the TPIC6B595 uses 50 V open-drain DMOS sinks for higher-power loads. This guide compares timing, current limits, 3.3 V interfacing, load wiring, thermal…

2026-09-02 74HC595 Pinout, Timing, Output Current, and Applications

The 74HC595 converts serial data into eight stable parallel outputs. This guide covers pin functions, shift and storage timing, OE and MR behavior, drive-current limits, cascading, voltage compatibilit…

2026-09-01 Latch vs Flip-Flop: Timing, Differences and Design Choices

A technical comparison of level-sensitive latches and edge-triggered flip-flops, covering timing windows, setup and hold limits, master–slave operation, time borrowing, race-through, HDL inference and…

2026-08-30 D Latch Circuit: Truth Table, Timing, ICs and Applications

A D latch stores one bit while Enable controls when data can pass. This reference covers gate-level operation, truth tables, transparency, setup and hold timing, LE versus OE, common ICs and practical …

2026-08-28 SR Latch Explained: NOR and NAND Circuits, Truth Tables, and Applications

An SR latch stores one bit through cross-coupled feedback. This engineering reference covers NOR and NAND implementations, truth tables, forbidden-state recovery, gated operation, switch debouncing, fa…

2026-08-27 Latch Circuit: SR and D Latches, Truth Tables, Timing, and Applications

Latch circuits retain one bit through feedback. This technical reference covers SR and D latches, truth tables, transparency, timing limits, latch-versus-flip-flop behavior, applications and common log…