Skyworks Solutions Inc. SI5338M-B04751-GM
- Part No.:
- SI5338M-B04751-GM
- Manufacturer:
- Skyworks Solutions Inc.
- Category:
- Application Specific Clock/Timing
- Package:
- 24-VFQFN Exposed Pad
- Datasheet:
-
SI5338M-B04751-GM.pdf
- Description:
- I2C CONTROL, 4-OUTPUT, ANY FREQU
- Quantity:
- Payment:

- Shipping:

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Product details
Overview
SI5338M-B04751-GM from Skyworks Solutions is an I²C-programmable quad clock generator with four independently configurable differential or single-ended outputs, 0.7 ps RMS typical phase jitter, PCIe Gen 1–4 Common Clock and Gen 3 SRNS compliance, and operation from 1.8/2.5/3.3 V core supply in a 4 × 4 mm 24-QFN package. It replaces up to four crystal oscillators in Ethernet switch/router and FPGA clocking systems.
For engineers reviewing the SI5338M-B04751-GM datasheet, SI5338M-B04751-GM pinout, SI5338M-B04751-GM application, or SI5338M-B04751-GM equivalent, key selection criteria include PCIe Gen 4 jitter compliance (0.15–0.45 ps RMS), independent output voltage per driver (1.5/1.8/2.5/3.3 V), MultiSynth™ frequency synthesis resolution (0 ppm accuracy), and flexible input support (8–30 MHz crystal, 5–710 MHz differential).
Technical Context
The SI5338M-B04751-GM implements a two-stage PLL architecture: a high-stability reference stage (Phase Frequency Detector + Loop Filter + VCO) feeding four independent MultiSynth™ fractional-N synthesis blocks, each driving one output pair. Each MultiSynth supports integer or fractional mode with <20 ps programmable phase step resolution and 1 ppm frequency increment/decrement capability.
Input flexibility includes six dedicated clock inputs (IN1–IN6): differential pairs (IN1/IN2, IN5/IN6) supporting 5–710 MHz, and single-ended pins (IN3/IN4) accepting 5–200 MHz CMOS. Output drivers support LVPECL/LVDS/HCSL/CMOS/SSTL/HSTL formats across 0.16–710 MHz, with independent VDDOx supplies per output bank (1.4–3.63 V).
Key Specifications
| Parameter | Value and Actual Design Meaning |
|---|---|
| Phase Jitter (RMS) | 0.7 ps typical (12 kHz–20 MHz); meets PCIe Gen 4 common clock jitter spec (0.15–0.45 ps RMS) |
| Output Count & Type | Four differential output pairs (CLK0A/B–CLK3A/B); supports up to eight single-ended clocks via configuration |
| Frequency Range | 0.16–710 MHz per output; LVPECL/LVDS up to 710 MHz, HCSL up to 250 MHz, CMOS up to 200 MHz |
| Input Reference | External crystal (8–30 MHz), CMOS (5–200 MHz), SSTL/HSTL (5–350 MHz), differential (5–710 MHz) |
| Supply Voltages | Core: 1.8/2.5/3.3 V ±10%; Output buffers: independently configurable 1.5/1.8/2.5/3.3 V per bank |
| Package | 24-pin QFN, 4 × 4 mm, 0.5 mm pitch; RoHS-compliant, –40 to +85 °C operating range |
| Interface | I²C/SMBus-compatible serial interface (SCL/SDA); supports ClockBuilder Pro programming |
Pinout & Package
SI5338M-B04751-GM uses a 24-lead QFN package (4 × 4 mm, 0.5 mm pitch) with exposed thermal pad. Pin assignments are fixed per Skyworks Si5338 family specification.
| Pin/Terminal | Circuit Role | Design Meaning |
|---|---|---|
| IN1, IN2, IN5, IN6 | Differential clock inputs | Accept 5–710 MHz AC-coupled differential signals; require external 100 Ω termination |
| IN3, IN4 | Single-ended clock inputs | Accept 5–200 MHz CMOS-level signals; support DC-coupled operation |
| CLK0A–CLK3B (x4 pairs) | Differential output drivers | Each pair supports LVPECL/LVDS/HCSL/CML/SSTL/HSTL; independently voltage- and format-configurable |
| VDDO0–VDDO3 | Output buffer supply rails | Independent 1.4–3.63 V supplies per output bank; enable mixed-voltage system interfacing |
| VDD | Core supply | 1.8/2.5/3.3 V ±10% core power; PSRR optimized for low-noise timing |
| SCL, SDA | I²C interface | Standard SMBus-compatible serial control; supports ClockBuilder Pro configuration |
| INTR | Interrupt output | Open-drain status indicator for loss-of-lock and loss-of-signal alarms |
Key Features
| Feature | Design Value |
|---|---|
| MultiSynth™ synthesis | Four independent fractional-N synthesizers enabling true zero-ppm frequency accuracy on all outputs |
| PCIe Gen 4 compliance | Meets Common Clock jitter spec (0.15–0.45 ps RMS) and SRNS requirements for Gen 3; validated with Intel Clock Jitter Tool |
| Independent output control | Per-output voltage (1.5/1.8/2.5/3.3 V), format (LVDS/LVPECL/HCSL/CMOS), and phase offset (<20 ps steps) |
| Spread spectrum clocking | Configurable SSC on any output: 0.5–5.0% spread, 33–63 kHz modulation rate, 5–350 MHz frequency range |
| Glitchless frequency tuning | Pin-controlled or I²C-based frequency increment/decrement in 1 ppm steps without output interruption |
Applications
| Ethernet Switch/Router Timing | PCIe Gen 1–4 Clock Distribution |
|---|---|
Use Scenario: High-density 1/10 GbE switching fabric requiring synchronized clocks across multiple PHYs, MACs, and packet processors. IC Role / Device Role / Timing Role: Primary quad-output clock source generating 125 MHz, 156.25 MHz, and 250 MHz clocks with sub-ps jitter for SerDes lanes and control logic. Use Value: Eliminates four discrete oscillators; enables deterministic inter-lane skew control (<100 ps) and PCIe Gen 4 jitter compliance. | Use Scenario: Server motherboard with multiple PCIe slots (Gen 3/4), CPU, and chipset requiring common reference clocks and separate reference-noise-suppressed (SRNS) clocks. IC Role / Device Role / Timing Role: Generates PCIe Common Clock (100 MHz) and SRNS reference (100 MHz) with independent jitter optimization per output. Use Value: Meets PCIe Gen 4 total jitter limit (≤33.6 ps pk-pk) and SRNS RMS jitter spec (≤0.32 ps) using same device. |
| Broadcast Video/Audio Synchronization | FPGA & Processor Clocking |
Use Scenario: SMPTE ST 2082/2081 video over IP transport system requiring precise 74.25 MHz, 148.5 MHz, and 297 MHz pixel clocks with frame-accurate phase alignment. IC Role / Device Role / Timing Role: Quad-output generator delivering genlock-capable clocks with programmable initial phase offset (±45 ns) and <20 ps step resolution. Use Value: Enables frame-synchronous switching between video sources without visible artifacts via deterministic phase control. | Use Scenario: Industrial FPGA-based controller with heterogeneous peripherals (DDR3/4 memory, ADCs, Gigabit Ethernet, USB 3.0) needing isolated, low-jitter clocks at varying frequencies and voltages. IC Role / Device Role / Timing Role: Configurable clock hub providing 100 MHz (DDR), 125 MHz (Ethernet), 200 MHz (USB), and 300 MHz (FPGA logic) from single chip. Use Value: Reduces BOM count and layout complexity while maintaining <10 ps cycle-cycle jitter for timing-critical interfaces. |
Equivalent & Alternatives
The following parts are listed as comparable options for similar quad clock generator applications.
| Alternative Part | Technical Difference | Application Difference | Selection Advice |
|---|---|---|---|
| Si5338A-B-GM | Same pinout and architecture; factory-programmed with default configuration (no OTP customization); lacks B04751-specific preloaded firmware | Not preconfigured for PCIe Gen 4 SRNS and broadcast video timing profiles; requires full ClockBuilder Pro reprogramming | Select when full field reprogrammability is required and custom initialization is acceptable |
| ICS853S01AGI-01LFT | Fixed-frequency quad LVDS generator (no I²C programming); 1.2 ps RMS jitter; 24-QFN but different pin mapping | Limited to preset frequencies; no spread spectrum, phase adjustment, or multi-format support | Select only for cost-sensitive, static-clock applications where flexibility is unnecessary |
Compared with Si5338A-B-GM and ICS853S01AGI-01LFT, SI5338M-B04751-GM delivers pre-validated PCIe Gen 4 and broadcast timing configurations, independent per-output voltage control, and sub-ps jitter-enabling faster time-to-market for high-performance systems without custom firmware development.
Availability
SI5338M-B04751-GM is available at Aetrix Electronics and suitable for Ethernet switch/router timing, PCIe Gen 1–4 clock distribution, broadcast video/audio synchronization, and FPGA & processor clocking requiring stable component supply and long-term design-in support.
Supply support for SI5338M-B04751-GM includes scheduled delivery planning, volume procurement assistance, BOM continuity management, traceable sourcing, and lifecycle availability coordination for OEM customers, industrial embedded developers, connected-device designers, and electronics production programs.
Manufacturer
Skyworks Solutions is a global semiconductor company specializing in analog and mixed-signal connectivity solutions for wireless, broadband, automotive, and industrial markets.
The Si5338 product line delivers programmable, low-jitter clock generation for high-speed serial interfaces including PCIe, Ethernet, Fibre Channel, and broadcast video-designed to replace multiple fixed-frequency oscillators with a single configurable IC.
FAQ
What is the primary function of the SI5338M-B04751-GM in a timing architecture?
The SI5338M-B04751-GM serves as an I²C-programmable quad clock generator that synthesizes up to four independent, any-frequency output clocks from a single reference input. Its MultiSynth™ technology enables true zero-ppm frequency accuracy on all outputs, making it ideal for replacing multiple crystal oscillators in systems like PCIe root complexes and Ethernet switches. SI5338M-B04751-GM integrates PLL-based synthesis, flexible output formatting, and precise phase control in one 4 × 4 mm QFN package.
Does the SI5338M-B04751-GM support PCIe Gen 4 timing requirements?
Yes, the SI5338M-B04751-GM meets PCIe Gen 4 Common Clock jitter specifications (0.15–0.45 ps RMS) and PCIe Gen 3 Separate Reference No Spread (SRNS) requirements (0.11–0.32 ps RMS). These values are measured per JEDEC standards using the Intel Clock Jitter Tool and validated with 100 MHz HCSL outputs. SI5338M-B04751-GM achieves this through its low-noise PLL architecture, optimized loop bandwidth (2–5 MHz), and differential output drivers.
How many clock inputs does the SI5338M-B04751-GM support, and what types are they?
The SI5338M-B04751-GM supports six clock inputs: two differential pairs (IN1/IN2 and IN5/IN6) accepting 5–710 MHz AC-coupled signals, and two single-ended pins (IN3/IN4) supporting 5–200 MHz CMOS-level inputs. It also accepts an 8–30 MHz parallel-resonant crystal directly on IN1/IN2. All inputs feed into a flexible input multiplexer, allowing dynamic selection of reference sources under I²C control. SI5338M-B04751-GM's input stage includes loss-of-signal detection with 2.6–5 µs response time.
Can the SI5338M-B04751-GM generate both differential and single-ended outputs simultaneously?
Yes, the SI5338M-B04751-GM can generate a mix of differential and single-ended outputs simultaneously. Its four output banks (CLK0–CLK3) each drive a differential pair (e.g., CLK0A/CLK0B), but each bank can be configured for LVPECL, LVDS, HCSL, CML, SSTL, HSTL, or CMOS signaling. When set to CMOS mode, each pair delivers two independent single-ended clocks, enabling up to eight CMOS outputs. SI5338M-B04751-GM maintains jitter performance across all formats, though differential outputs deliver the lowest measured 0.7 ps RMS.
What programming tools are compatible with the SI5338M-B04751-GM?
The SI5338M-B04751-GM is programmed exclusively using Skyworks' ClockBuilder Pro software, a free GUI-based tool that generates configuration files (.cbs) and supports real-time register editing, jitter simulation, and hardware validation via USB adapter. SI5338M-B04751-GM does not require external microcontrollers-the I²C interface (SCL/SDA) handles all configuration, including startup defaults stored in on-chip OTP memory. ClockBuilder Pro also provides PCIe jitter analysis and export to industry-standard formats (e.g., .hex, .csv).
SI5338M-B04751-GM Specifications
- Product attributes
- Attribute value
- Manufacturer:
- Skyworks Solutions Inc.
- Series:
- MultiSynth™
- Package/Case:
- 24-VFQFN Exposed Pad
- Packaging:
- Tray
- Product Status:
- Active
- Programmable:
- Not Verified
- PLL:
- -
- Main Purpose:
- -
- Input:
- -
- Output:
- -
- Number of Circuits:
- -
- Ratio - Input:Output:
- -
- Differential - Input:Output:
- -
- Frequency - Max:
- -
- Voltage - Supply:
- -
- Operating Temperature:
- -
- Mounting Type:
- Surface Mount
- Grade:
- -
- Qualification:
- -
- Supplier Device Package:
- 24-QFN (4x4)
SI5338M-B04751-GM FAQ
1.How can I place an order for SI5338M-B04751-GM through Aetrix?
Please submit a Request for Quotation (RFQ) for SI5338M-B04751-GM on Aetrix. Our sales agent will provide a competitive quotation and guide you through the order confirmation once you accept the terms.
2.Are the price and stock information for SI5338M-B04751-GM reliable?
The price and inventory of SI5338M-B04751-GM are updated periodically and may fluctuate due to market conditions. Stock and pricing data are typically refreshed every 24 hours. Quotation validity for SI5338M-B04751-GM is usually 5 days.
3.What payment methods are accepted for SI5338M-B04751-GM?
We accept Wire Transfer, PayPal, Credit Card, Western Union, MoneyGram, and Escrow for SI5338M-B04751-GM transactions.
Note: Certain payment methods may incur a processing fee.
4.How is shipping managed for SI5338M-B04751-GM?
SI5338M-B04751-GM orders can be shipped via leading logistics carriers, including DHL, UPS, FedEx, TNT, or Registered Mail.
Once your SI5338M-B04751-GM order is processed, you will receive an email with the shipment details and tracking number.
Note: Tracking information may take up to 24 hours to appear. Express delivery typically takes 3–5 business days.
5.How can I obtain technical support or documentation for SI5338M-B04751-GM?
For technical support, including SI5338M-B04751-GM datasheets, pinout diagrams, or application guidance, please contact our engineering support team. They can provide detailed documentation and assistance for your SI5338M-B04751-GM requirements.
6.How does Aetrix verify that SI5338M-B04751-GM is sourced from the original manufacturer or authorized distributors?
All SI5338M-B04751-GM products on Aetrix are procured from qualified distributors and authorized channels. Our dedicated quality assurance team conducts strict verification, including traceability checks and, if necessary, third-party testing. This ensures that SI5338M-B04751-GM meets industry standards.
7.What is the process for return or replacement of SI5338M-B04751-GM?
All SI5338M-B04751-GM units undergo pre-shipment inspection (PSI). If there is an issue with SI5338M-B04751-GM, returns or replacements are accepted under the following conditions:
1.Quantity discrepancies, incorrect items, or visible external defects (such as breakage or corrosion), acknowledged by Aetrix.
2.The issue is reported within 90 days of delivery.
3.The SI5338M-B04751-GM part is unused and in its original packaging.
Return procedure for SI5338M-B04751-GM:
1.Submit a request within 90 days.
2.Obtain a Return Material Authorization (RMA) from Aetrix.
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