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Home > Products > Integrated Circuits (ICs) > Clock/Timing > Application Specific Clock/Timing

Skyworks Solutions Inc. SI5338M-B04914-GMR

Name: SI5338M-B04914-GMR
Brand: Skyworks Solutions Inc.
SKU: SI5338M-B04914-GMR
Price: 2.40 USD
Availability: InStock
Rating: 5 (2 reviews)

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Part No.:: SI5338M-B04914-GMR

Manufacturer:: Skyworks Solutions Inc.

Category:: Application Specific Clock/Timing

Package:: 24-VFQFN Exposed Pad

Datasheet:: SI5338M-B04914-GMR.pdf

Description:: I2C CONTROL, 4-OUTPUT, ANY FREQU

Quantity:: RFQ Add To RFQ list

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Product details

Overview

SI5338M-B04914-GMR from Skyworks Solutions is an I²C-programmable quad clock generator with four independently configurable differential or single-ended outputs, 0.7 ps RMS typical phase jitter, PCIe Gen 1–4 Common Clock and Gen 3 SRNS compliance, and operation across –40 to +85 °C. It replaces up to four crystal oscillators in Ethernet switch/router, PCIe host controller, and FPGA clocking systems.

For engineers reviewing the SI5338M-B04914-GMR datasheet, SI5338M-B04914-GMR pinout, SI5338M-B04914-GMR application, or SI5338M-B04914-GMR equivalent, key selection criteria include its MultiSynth™-based any-frequency synthesis (0.16–710 MHz per output), independent output voltage support (1.5/1.8/2.5/3.3 V), spread-spectrum capability (0.5–5.0% down-spread), and 24-QFN package with I²C/SMBus interface.

Technical Context

The SI5338M-B04914-GMR implements a two-stage PLL architecture: a high-stability integer-N PLL (Stage 1) locks to one of six input references (crystal, CMOS, SSTL/HSTL, or differential), followed by four independent MultiSynth™ fractional-N synthesizers (Stage 2) generating each output. Each MultiSynth supports programmable initial phase offset (±45 ns), glitchless frequency increment/decrement (1 ppm steps), and <20 ps phase step resolution.

Output drivers are fully decoupled-each supports LVPECL/LVDS/HCSL/CMOS/SSTL/HSTL formats, independent VDDO supply (1.4–3.63 V), and configurable slew rate and termination. The device includes loss-of-lock and loss-of-signal alarms, external feedback mode for zero-delay operation, and internal OTP NVM for factory programming.

Key Specifications

Parameter	Value and Actual Design Meaning
Phase Jitter (RMS)	0.7 ps - meets PCIe Gen 3 SRNS and GbE jitter requirements at 125 MHz output
Output Frequency Range	0.16–710 MHz - covers PCIe 100 MHz, Ethernet 125/156.25 MHz, and Fibre Channel 212.5/425 MHz
Input Reference Support	Crystal (8–30 MHz), CMOS (5–200 MHz), SSTL/HSTL (5–350 MHz), differential (5–710 MHz) - enables flexible system clock tree design
Supply Voltages	VDD = 1.8/2.5/3.3 V ±10%; VDDOx = 1.4–3.63 V - allows mixed-voltage board integration without level shifters
Package	24-pin QFN, 4 × 4 mm - space-efficient footprint compatible with standard reflow profiles
Operating Temperature	–40 to +85 °C - qualified for industrial and telecom line card environments
I²C Interface	Standard-mode (100 kHz) and fast-mode (400 kHz) - supports configuration via microcontroller without dedicated programmer

Pinout & Package

SI5338M-B04914-GMR is housed in a 24-lead, 4 × 4 mm QFN package with exposed thermal pad. Pin assignments follow Skyworks' standardized Si5338 pinout: inputs IN1–IN6 (differential and single-ended reference support), four differential output pairs (CLK0A/B through CLK3A/B), six VDDO supplies (VDDO0–VDDO3), dual core VDD pins, SCL/SDA/I²C control, INTR alarm output, and reserved ground.

Pin/Terminal	Circuit Role	Design Meaning
IN1/IN2, IN5/IN6	Differential reference inputs	Accept 5–710 MHz AC-coupled differential clocks; require external 100 Ω termination
IN3/IN4	Single-ended reference inputs	Support 5–200 MHz CMOS, 5–350 MHz SSTL/HSTL with internal biasing
CLK0A/CLK0B – CLK3A/CLK3B	Differential clock outputs	Four independent pairs; each configurable as LVPECL/LVDS/HCSL/CML with per-output VDDO
VDDO0–VDDO3	Output buffer supplies	Enable independent voltage setting per output driver (1.4–3.63 V) for mixed-signal interface compatibility
SCL/SDA	I²C serial interface	Standard SMBus-compatible bus for register configuration and status readback
INTR	Interrupt output	Open-drain alarm signal indicating loss-of-lock or loss-of-signal events

Key Features

Feature	Design Value
MultiSynth™ synthesis engine	Enables true zero-ppm frequency accuracy on all four outputs simultaneously, eliminating need for multiple crystals
Independent output format & voltage	Each of four outputs supports LVPECL/LVDS/HCSL/CMOS/SSTL/HSTL with dedicated VDDO rail - simplifies multi-protocol clock distribution
Glitchless frequency tuning	1 ppm-step frequency increment/decrement via pin or I²C - enables dynamic clock scaling without output interruption
Programmable phase offset	±45 ns adjustment per output in <20 ps steps - supports precise skew management in high-speed SerDes lanes
Spread spectrum clocking (SSC)	Configurable down-spread (0.5–5.0%) and modulation rate (33–63 kHz) on any output - reduces EMI in dense PCB layouts

Applications

PCIe Gen 3/4 Host Controller	Ethernet Switch Timing
Use Scenario: Providing synchronized 100 MHz common clock and 100 MHz SRNS reference to PCIe root complex and endpoint devices in server motherboard designs. IC Role / Device Role / Timing Role: Quad-output clock generator delivering low-jitter, phase-aligned clocks meeting PCIe Gen 3 SRNS and Gen 4 common clock jitter specs. Use Value: Eliminates four discrete oscillators while maintaining <0.32 ps RMS jitter compliance per PCIe Base Spec 4.0 rev 0.5.	Use Scenario: Generating 125 MHz, 156.25 MHz, and 312.5 MHz clocks for 1/10 GbE PHYs, packet processors, and switch fabric interfaces in Layer 3 switches. IC Role / Device Role / Timing Role: Programmable frequency translator converting a single 25 MHz crystal into multiple Ethernet-compliant rates with deterministic phase relationships. Use Value: Reduces BOM count and layout area versus fixed-frequency XO solutions while supporting IEEE 802.3 clause 49/74 jitter masks.
FPGA/ASIC Clock Tree	Broadcast Video Synchronization
Use Scenario: Supplying 100 MHz system clock, 200 MHz transceiver reference, 300 MHz DDR4 memory clock, and 500 MHz video processing clock to Xilinx Versal or Intel Agilex FPGA platforms. IC Role / Device Role / Timing Role: Configurable quad clock source with independent output voltage and format per domain - enabling direct interface to mixed-voltage FPGA banks. Use Value: Avoids external level shifters and buffers; per-output VDDO (1.5/1.8/2.5/3.3 V) matches FPGA I/O bank requirements.	Use Scenario: Delivering SMPTE ST 2059-2 compliant 27 MHz, 74.25 MHz, and 148.5 MHz reference clocks to video encoders, decoders, and genlock circuits in broadcast production switchers. IC Role / Device Role / Timing Role: Low-phase-noise clock generator with sub-1 ps RMS jitter and programmable phase alignment across outputs. Use Value: Meets SMPTE ST 2059-2 wander and jitter limits (≤1.5 ps RMS over 12 kHz–20 MHz) for PTP grandmaster timing applications.

PCIe Gen 3/4 Host Controller

Ethernet Switch Timing

Use Scenario: Providing synchronized 100 MHz common clock and 100 MHz SRNS reference to PCIe root complex and endpoint devices in server motherboard designs.

IC Role / Device Role / Timing Role: Quad-output clock generator delivering low-jitter, phase-aligned clocks meeting PCIe Gen 3 SRNS and Gen 4 common clock jitter specs.

Use Value: Eliminates four discrete oscillators while maintaining <0.32 ps RMS jitter compliance per PCIe Base Spec 4.0 rev 0.5.

Use Scenario: Generating 125 MHz, 156.25 MHz, and 312.5 MHz clocks for 1/10 GbE PHYs, packet processors, and switch fabric interfaces in Layer 3 switches.

IC Role / Device Role / Timing Role: Programmable frequency translator converting a single 25 MHz crystal into multiple Ethernet-compliant rates with deterministic phase relationships.

Use Value: Reduces BOM count and layout area versus fixed-frequency XO solutions while supporting IEEE 802.3 clause 49/74 jitter masks.

FPGA/ASIC Clock Tree

Broadcast Video Synchronization

Use Scenario: Supplying 100 MHz system clock, 200 MHz transceiver reference, 300 MHz DDR4 memory clock, and 500 MHz video processing clock to Xilinx Versal or Intel Agilex FPGA platforms.

IC Role / Device Role / Timing Role: Configurable quad clock source with independent output voltage and format per domain - enabling direct interface to mixed-voltage FPGA banks.

Use Value: Avoids external level shifters and buffers; per-output VDDO (1.5/1.8/2.5/3.3 V) matches FPGA I/O bank requirements.

Use Scenario: Delivering SMPTE ST 2059-2 compliant 27 MHz, 74.25 MHz, and 148.5 MHz reference clocks to video encoders, decoders, and genlock circuits in broadcast production switchers.

IC Role / Device Role / Timing Role: Low-phase-noise clock generator with sub-1 ps RMS jitter and programmable phase alignment across outputs.

Use Value: Meets SMPTE ST 2059-2 wander and jitter limits (≤1.5 ps RMS over 12 kHz–20 MHz) for PTP grandmaster timing applications.

Equivalent & Alternatives

The following parts are listed as comparable options for similar quad-output clock generator applications.

Alternative Part	Technical Difference	Application Difference	Selection Advice
Si5332A-D06114-GM	Higher integration: integrated crystal, lower jitter (0.35 ps RMS), but only two outputs and no SSC	Best for compact, ultra-low-jitter dual-clock applications where spread spectrum is not required	Select when board space is critical and dual-output suffices; avoid if four independent outputs or EMI reduction via SSC is needed
ICS853S01IAGLF	Fixed-frequency, non-programmable; 2.5 V only; 0.9 ps RMS jitter; 4 LVDS outputs	Lower cost for static clock trees where frequency flexibility is unnecessary	Choose for cost-sensitive, high-volume applications with unchanging clock requirements and no need for I²C reconfiguration

Compared with Si5332A-D06114-GM and ICS853S01IAGLF, SI5338M-B04914-GMR uniquely balances full I²C programmability, four independent outputs with per-output voltage/format control, and spread-spectrum capability - making it optimal for evolving, multi-protocol systems requiring field-upgradable timing.

Availability

SI5338M-B04914-GMR is available at Aetrix Electronics and suitable for Ethernet switch/router, PCIe Gen 3/4 host controller, and FPGA/ASIC clocking applications requiring stable component supply, long-term lifecycle assurance, and traceable sourcing.

Supply support for SI5338M-B04914-GMR includes scheduled delivery planning, volume procurement assistance, BOM continuity management, traceable sourcing, and lifecycle availability coordination for OEM customers, industrial embedded developers, connected-device designers, and electronics production programs.

Manufacturer

Skyworks Solutions is a global leader in analog and mixed-signal semiconductors, specializing in RF, timing, and connectivity solutions for infrastructure, automotive, and mobile markets.

The Si5338 product line was designed to replace multiple fixed-frequency oscillators with a single programmable clock generator for high-speed digital systems - targeting PCIe, Ethernet, and broadcast video timing applications demanding low jitter and flexible configuration.

FAQ

What is the primary function of the SI5338M-B04914-GMR in a timing system?

The SI5338M-B04914-GMR serves as an I²C-programmable quad clock generator that synthesizes up to four independent, low-jitter output frequencies from a single reference input. Its MultiSynth™ architecture enables zero-ppm precision across all outputs, replacing multiple discrete oscillators in systems like PCIe root complexes and Ethernet switches. SI5338M-B04914-GMR supports differential and single-ended formats, independent output voltages, and spread-spectrum clocking for EMI reduction.

Does the SI5338M-B04914-GMR support PCIe Gen 4 timing requirements?

Yes, the SI5338M-B04914-GMR meets PCIe Gen 4 common clock jitter specifications with ≤0.45 ps RMS (10 kHz–50 MHz) when configured per Skyworks' recommended PLL bandwidth (2–5 MHz) and CDR settings. It is explicitly validated for PCIe Gen 1/2/3/4 Common Clock and Gen 3 SRNS compliance per the PCI-SIG specification, and jitter performance is verified using the Skyworks PCIe Clock Jitter Tool.

How many reference inputs does the SI5338M-B04914-GMR support, and what types are accepted?

The SI5338M-B04914-GMR supports six reference inputs: two differential pairs (IN1/IN2 and IN5/IN6), two single-ended inputs (IN3 and IN4), and two additional differential-capable pins (IN4 and IN6 used in alternate configurations). It accepts crystal (8–30 MHz), CMOS (5–200 MHz), SSTL/HSTL (5–350 MHz), and differential (5–710 MHz) references - enabling flexible clock tree design with minimal external components.

Can the SI5338M-B04914-GMR generate different output formats simultaneously?

Yes, the SI5338M-B04914-GMR supports simultaneous mixed-format outputs: for example, CLK0A/B as LVDS, CLK1A/B as HCSL, CLK2A/B as LVPECL, and CLK3A/B as CMOS - each with independent VDDO supply (1.5/1.8/2.5/3.3 V). This eliminates external level translators and buffers in multi-protocol systems such as FPGA-based video processing platforms interfacing to DDR4, PCIe, and Gigabit Ethernet PHYs.

Is factory programming required for the SI5338M-B04914-GMR to operate out-of-the-box?

No, the SI5338M-B04914-GMR includes factory-programmed OTP NVM with default configuration enabling immediate operation after power-up. However, full functionality - including custom frequencies, output formats, and spread-spectrum settings - requires I²C programming via ClockBuilder Pro software or host MCU. The device powers up with preloaded settings that meet typical PCIe or Ethernet timing defaults, but user-specific tuning is performed post-deployment.

SI5338M-B04914-GMR Specifications

Product attributes: Attribute value

Manufacturer:: Skyworks Solutions Inc.

Series:: MultiSynth™

Package/Case:: 24-VFQFN Exposed Pad

Packaging:: Tape & Reel (TR)

Product Status:: Active

Programmable:: Not Verified

PLL:: -

Main Purpose:: -

Input:: -

Output:: -

Number of Circuits:: -

Ratio - Input:Output:: -

Differential - Input:Output:: -

Frequency - Max:: -

Voltage - Supply:: -

Operating Temperature:: -

Mounting Type:: Surface Mount

Grade:: -

Qualification:: -

Supplier Device Package:: 24-QFN (4x4)

SI5338M-B04914-GMR FAQ

1.How can I place an order for SI5338M-B04914-GMR through Aetrix?

Please submit a Request for Quotation (RFQ) for SI5338M-B04914-GMR on Aetrix. Our sales agent will provide a competitive quotation and guide you through the order confirmation once you accept the terms.

2.Are the price and stock information for SI5338M-B04914-GMR reliable?

The price and inventory of SI5338M-B04914-GMR are updated periodically and may fluctuate due to market conditions. Stock and pricing data are typically refreshed every 24 hours. Quotation validity for SI5338M-B04914-GMR is usually 5 days.

3.What payment methods are accepted for SI5338M-B04914-GMR?

We accept Wire Transfer, PayPal, Credit Card, Western Union, MoneyGram, and Escrow for SI5338M-B04914-GMR transactions.

Note: Certain payment methods may incur a processing fee.

4.How is shipping managed for SI5338M-B04914-GMR?

SI5338M-B04914-GMR orders can be shipped via leading logistics carriers, including DHL, UPS, FedEx, TNT, or Registered Mail.

Once your SI5338M-B04914-GMR order is processed, you will receive an email with the shipment details and tracking number.

Note: Tracking information may take up to 24 hours to appear. Express delivery typically takes 3–5 business days.

5.How can I obtain technical support or documentation for SI5338M-B04914-GMR?

For technical support, including SI5338M-B04914-GMR datasheets, pinout diagrams, or application guidance, please contact our engineering support team. They can provide detailed documentation and assistance for your SI5338M-B04914-GMR requirements.

6.How does Aetrix verify that SI5338M-B04914-GMR is sourced from the original manufacturer or authorized distributors?

All SI5338M-B04914-GMR products on Aetrix are procured from qualified distributors and authorized channels. Our dedicated quality assurance team conducts strict verification, including traceability checks and, if necessary, third-party testing. This ensures that SI5338M-B04914-GMR meets industry standards.

7.What is the process for return or replacement of SI5338M-B04914-GMR?

All SI5338M-B04914-GMR units undergo pre-shipment inspection (PSI). If there is an issue with SI5338M-B04914-GMR, returns or replacements are accepted under the following conditions:

1.Quantity discrepancies, incorrect items, or visible external defects (such as breakage or corrosion), acknowledged by Aetrix.

2.The issue is reported within 90 days of delivery.

3.The SI5338M-B04914-GMR part is unused and in its original packaging.

Return procedure for SI5338M-B04914-GMR:

1.Submit a request within 90 days.

2.Obtain a Return Material Authorization (RMA) from Aetrix.

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