Send an Inquiry

To receive a quote for your project, please fill in the following information, and we’ll get back to you promptly.

Submit Inventory List

Please fill in the following information, and we’ll get back to you promptly.

Home > Products > Integrated Circuits (ICs) > Clock/Timing > Application Specific Clock/Timing

Skyworks Solutions Inc. SI5338M-B04945-GMR

Name: SI5338M-B04945-GMR
Brand: Skyworks Solutions Inc.
SKU: SI5338M-B04945-GMR
Price: 2.40 USD
Availability: InStock
Rating: 5 (2 reviews)

Compare

Part No.:: SI5338M-B04945-GMR

Manufacturer:: Skyworks Solutions Inc.

Category:: Application Specific Clock/Timing

Package:: 24-VFQFN Exposed Pad

Datasheet:: SI5338M-B04945-GMR.pdf

Description:: I2C CONTROL, 4-OUTPUT, ANY FREQU

Quantity:: RFQ Add To RFQ list

Payment:

Shipping:

Inventory:3,780

Please send an inquiry. Send us your inquiry, and we will respond immediately.

Product details

Overview

SI5338M-B04945-GMR from Skyworks Solutions is an I²C-programmable quad clock generator with four independently configurable differential or single-ended outputs, 0.7 ps RMS typical phase jitter, PCIe Gen 1–4 and SRNS compliance, and MultiSynth™ frequency synthesis supporting 0.16–710 MHz output ranges. It replaces up to four crystal oscillators in high-speed serial interface timing applications such as PCIe root complexes and FPGA clock trees.

For engineers reviewing the SI5338M-B04945-GMR datasheet, SI5338M-B04945-GMR pinout, SI5338M-B04945-GMR application, or SI5338M-B04945-GMR equivalent, key selection criteria include its 24-QFN package, independent output voltage per driver (1.5/1.8/2.5/3.3 V), spread-spectrum capability (0.5–5.0% down-spread), glitchless frequency adjustment in 1 ppm steps, and support for external crystal (8–30 MHz), CMOS (5–200 MHz), or differential (5–710 MHz) reference inputs.

Technical Context

The SI5338M-B04945-GMR implements a two-stage PLL architecture: a high-stability integer-N PLL (Stage 1) locks to the input reference, followed by four independent MultiSynth™ fractional-N synthesis blocks (Stage 2) generating each output. Each output supports programmable format (LVPECL/LVDS/HCSL/CMOS/SSTL/HSTL), voltage (1.5–3.3 V), phase offset (±45 ns), and spread-spectrum modulation (33–63 kHz rate, 0.5–5.0% deviation).

It features loss-of-lock and loss-of-signal alarms, I²C/SMBus-compatible configuration, and flexible input handling-including external crystal oscillator (8–30 MHz), single-ended CMOS (5–200 MHz), SSTL/HSTL (5–350 MHz), and differential (5–710 MHz) references-enabling use in both free-running clock generation and synchronous frequency translation modes.

Key Specifications

Parameter	Value and Actual Design Meaning
Phase Jitter (RMS)	0.7 ps typical (12 kHz–20 MHz); meets PCIe Gen 3/4 SRNS and GbE jitter requirements.
Output Frequency Range	0.16–710 MHz per channel; supports LVPECL/LVDS up to 710 MHz, HCSL up to 250 MHz, CMOS up to 200 MHz.
Input Reference Support	Crystal (8–30 MHz), CMOS (5–200 MHz), SSTL/HSTL (5–350 MHz), differential (5–710 MHz).
Output Voltage Per Driver	Independently configurable at 1.5 V, 1.8 V, 2.5 V, or 3.3 V-enables mixed-voltage system clocking without level shifters.
Spread Spectrum	Configurable on any output: 0.5–5.0% deviation, 33–63 kHz modulation rate-reduces EMI in dense PCB layouts.
Core Supply	Single 1.8 V / 2.5 V / 3.3 V supply; 45 mA typical current draw at 100 MHz on all outputs with 25 MHz refclk.
Operating Temperature	–40 °C to +85 °C ambient; qualified for industrial and telecom line card environments.

Pinout & Package

SI5338M-B04945-GMR is housed in a 4 mm × 4 mm, 24-lead QFN package with exposed thermal pad. Pin assignments follow the standard Si5338 top-view layout: IN1/IN2 (differential input 1), IN3/IN4 (single-ended inputs), IN5/IN6 (differential input 2), CLK0A/CLK0B through CLK3A/CLK3B (four differential output pairs), VDDO0–VDDO3 (independent output supply pins), VDD (core supply), SCL/SDA (I²C interface), INTR (interrupt output), and RSVD_GND (reserved ground).

Pin/Terminal	Circuit Role	Design Meaning
CLK0A / CLK0B	Differential Output Pair 0	LVPECL/LVDS/HCSL/CML-capable; independently configured frequency, format, voltage, and phase.
CLK1A / CLK1B	Differential Output Pair 1	Same configurability as CLK0; supports integer/fractional synthesis and ±45 ns phase offset.
CLK2A / CLK2B	Differential Output Pair 2	Independent MultiSynth™ block; enables simultaneous generation of non-harmonically related clocks.
CLK3A / CLK3B	Differential Output Pair 3	Full feature parity with other outputs; supports spread spectrum and glitchless frequency increment/decrement.
VDDO0–VDDO3	Output Buffer Supply	Each powers one output pair; allows mixed-signal systems to drive 1.8 V FPGAs and 3.3 V legacy peripherals simultaneously.
SCL / SDA	I²C Serial Interface	Standard 2-wire bus (up to 400 kHz) for register programming, status readback, and dynamic reconfiguration.
INTR	Interrupt Output	Open-drain signal asserting loss-of-lock or loss-of-signal events; simplifies system-level fault monitoring.
IN1/IN2, IN5/IN6	Differential Reference Inputs	Accept 5–710 MHz AC-coupled signals; internal 100 Ω termination enables direct connection to LVDS/HCSL sources.
IN3 / IN4	Single-Ended Reference Inputs	Support CMOS/SSTL/HSTL (5–350 MHz); internal biasing eliminates need for external resistors in most cases.

Key Features

Feature	Design Value
MultiSynth™ Any-Frequency Synthesis	Four independent synthesizers deliver true zero-ppm accuracy across 0.16–710 MHz-eliminates need for multiple crystals or fixed-ratio PLLs.
PCIe Gen 1–4 & SRNS Compliance	Meets total jitter (33.6 ps pk-pk Gen 2), RMS jitter (0.11–0.45 ps RMS Gen 3/4), and spread-spectrum requirements-certified for server and switch timing.
Independent Output Voltage Control	Each of four output drivers powered by dedicated VDDOx pin (1.5/1.8/2.5/3.3 V)-removes external level translators in heterogeneous SoC/FPGA designs.
Glitchless Frequency Adjustment	1 ppm step size via PINC/FDEC pins or I²C; no output interruption during real-time clock tuning-critical for adaptive SERDES rate control.
Programmable Phase Offset	±45 ns range in <20 ps steps per output-enables precise skew management across multi-lane interfaces like PCIe x16 or DDR memory channels.
External Feedback Mode	Supports zero-delay buffer operation using external feedback path-maintains deterministic latency for clock distribution networks.

Applications

PCIe Gen 3/4 Root Complex Timing	Ethernet Switch Clock Tree
Use Scenario: Providing synchronized 100 MHz common clock and 100 MHz SRNS reference to CPU, PCH, and PCIe endpoint devices in enterprise servers. IC Role / Device Role / Timing Role: Quad-output clock generator delivering PCIe-compliant jitter performance with independent voltage control for mixed-voltage endpoints. Use Value: Replaces four discrete oscillators while meeting Gen 4 SRNS RMS jitter ≤0.32 ps and enabling board-level EMI reduction via spread spectrum.	Use Scenario: Generating 125 MHz, 156.25 MHz, and 312.5 MHz clocks for 1/10/25 GbE PHYs, MACs, and packet processors in modular switches. IC Role / Device Role / Timing Role: Programmable frequency translator converting a single 25 MHz crystal into multiple Ethernet-standard rates with sub-ps jitter. Use Value: Eliminates custom clock ICs per port; supports hot-plug rate negotiation and IEEE 1588 timestamp synchronization via precise phase alignment.
FPGA-Based Broadcast Video System	Telecom Line Card Synchronization
Use Scenario: Delivering frame-synchronized 74.25 MHz (HD-SDI), 148.5 MHz (3G-SDI), and 297 MHz (12G-SDI) clocks to video processing FPGAs and serializers. IC Role / Device Role / Timing Role: Any-frequency clock generator producing exact SMPTE-standard frequencies with zero ppm error and <10 ps cycle-cycle jitter. Use Value: Enables drop-in replacement of legacy crystal-based solutions while supporting future 4K/8K upgrade paths via firmware reprogramming.	Use Scenario: Distributing Stratum 3–compliant 2.048 MHz, 19.44 MHz, and 155.52 MHz clocks across TDM, OTN, and CPRI interfaces in wireless baseband units. IC Role / Device Role / Timing Role: High-stability clock source with OC-12 compliant jitter (≤1 ps RMS) and loss-of-signal alarm for network element redundancy. Use Value: Meets Telcordia GR-1244-CORE holdover and wander specifications when paired with TCXO reference; reduces BOM count vs. discrete PLL+VCXO solutions.

PCIe Gen 3/4 Root Complex Timing

Ethernet Switch Clock Tree

Use Scenario: Providing synchronized 100 MHz common clock and 100 MHz SRNS reference to CPU, PCH, and PCIe endpoint devices in enterprise servers.

IC Role / Device Role / Timing Role: Quad-output clock generator delivering PCIe-compliant jitter performance with independent voltage control for mixed-voltage endpoints.

Use Value: Replaces four discrete oscillators while meeting Gen 4 SRNS RMS jitter ≤0.32 ps and enabling board-level EMI reduction via spread spectrum.

Use Scenario: Generating 125 MHz, 156.25 MHz, and 312.5 MHz clocks for 1/10/25 GbE PHYs, MACs, and packet processors in modular switches.

IC Role / Device Role / Timing Role: Programmable frequency translator converting a single 25 MHz crystal into multiple Ethernet-standard rates with sub-ps jitter.

Use Value: Eliminates custom clock ICs per port; supports hot-plug rate negotiation and IEEE 1588 timestamp synchronization via precise phase alignment.

FPGA-Based Broadcast Video System

Telecom Line Card Synchronization

Use Scenario: Delivering frame-synchronized 74.25 MHz (HD-SDI), 148.5 MHz (3G-SDI), and 297 MHz (12G-SDI) clocks to video processing FPGAs and serializers.

IC Role / Device Role / Timing Role: Any-frequency clock generator producing exact SMPTE-standard frequencies with zero ppm error and <10 ps cycle-cycle jitter.

Use Value: Enables drop-in replacement of legacy crystal-based solutions while supporting future 4K/8K upgrade paths via firmware reprogramming.

Use Scenario: Distributing Stratum 3–compliant 2.048 MHz, 19.44 MHz, and 155.52 MHz clocks across TDM, OTN, and CPRI interfaces in wireless baseband units.

IC Role / Device Role / Timing Role: High-stability clock source with OC-12 compliant jitter (≤1 ps RMS) and loss-of-signal alarm for network element redundancy.

Use Value: Meets Telcordia GR-1244-CORE holdover and wander specifications when paired with TCXO reference; reduces BOM count vs. discrete PLL+VCXO solutions.

Equivalent & Alternatives

The following parts are listed as comparable options for similar quad-output clock generator applications.

Alternative Part	Technical Difference	Application Difference	Selection Advice
Si5338A-B04945-GMR	Same silicon die and pinout; differs only in factory-programmed NVM configuration (different default output frequencies and formats).	Pre-configured for alternate reference input or output set; requires no reprogramming for drop-in use in legacy designs.	Select if pre-programmed startup behavior matches existing system requirements-avoids initial ClockBuilder Pro setup.
LMK04832ISQE/NOPB	Two-stage jitter cleaner with dual PLLs; higher power (120 mA), larger 36-QFN package; supports JESD204B deterministic latency.	Better suited for RF sampling and ADC/DAC synchronization where sub-100 fs jitter and deterministic delay matter more than cost or footprint.	Choose when ultra-low additive jitter (<50 fs) or JESD204B SYSREF alignment is required-SI5338M-B04945-GMR is preferred for cost-sensitive, space-constrained PCIe/Ethernet timing.

Compared with Si5338A-B04945-GMR, the SI5338M-B04945-GMR offers identical hardware but different factory OTP settings; versus LMK04832ISQE/NOPB, it trades jitter cleaning capability and JESD204B support for lower power, smaller footprint, and simpler I²C-only configuration-making it optimal for high-volume infrastructure clocking where PCIe/ETH compliance and design flexibility are primary.

Availability

SI5338M-B04945-GMR is available at Aetrix Electronics and suitable for PCIe Gen 4 server motherboards, 25/100 GbE switch fabric cards, broadcast video FPGA platforms, and telecom line cards requiring stable component supply, long-term lifecycle support, and guaranteed traceable sourcing.

Supply support for SI5338M-B04945-GMR includes scheduled delivery planning, volume procurement assistance, BOM continuity management, traceable sourcing, and lifecycle availability coordination for OEM customers, industrial embedded developers, connected-device designers, and electronics production programs.

Manufacturer

Skyworks Solutions is a global semiconductor company specializing in analog and mixed-signal connectivity solutions for infrastructure, automotive, and mobile markets.

The Si5338 product line delivers programmable, low-jitter clock generation for high-speed serial interfaces-designed specifically to replace multiple fixed-frequency oscillators and simplify timing architecture in data center, networking, and broadcast equipment.

FAQ

What is the default factory configuration of the SI5338M-B04945-GMR?

The SI5338M-B04945-GMR ships with factory-programmed OTP memory defining its default output frequencies, formats, and voltage levels. Unlike blank Si5338 variants, this part boots with a known, tested configuration-enabling immediate operation without I²C programming. The specific configuration is documented in Skyworks' device-specific configuration file (CFG) associated with B04945, accessible via ClockBuilder Pro. SI5338M-B04945-GMR retains full field reprogrammability via I²C after power-up.

Does the SI5338M-B04945-GMR support PCIe Gen 4 Separate Reference No Spread (SRNS) mode?

Yes, the SI5338M-B04945-GMR is explicitly validated for PCIe Gen 4 SRNS operation with ≤0.32 ps RMS jitter (typical) under specified conditions: PLL loop bandwidth of 2–4 MHz or 2–5 MHz and CDR frequency of 10 MHz. This compliance is confirmed in Table 12 of the official datasheet and verified using the Skyworks PCIe Clock Jitter Tool. SI5338M-B04945-GMR achieves this using its MultiSynth™ fractional-N synthesis and optimized PLL filtering-no external components required.

Can the SI5338M-B04945-GMR generate three different frequencies above 350 MHz simultaneously?

No. The SI5338M-B04945-GMR can output only two unique frequencies above 350 MHz at once-specifically Fvco/4 and Fvco/6-as stated in Note 6 of Table 6. Attempting to configure three outputs >350 MHz will result in invalid synthesis or degraded jitter performance. For applications requiring >350 MHz on three or more outputs, users must select frequencies within the 0.16–350 MHz range or use Fvco/4 and Fvco/6 as the two high-frequency outputs while assigning others below 350 MHz. This limitation is inherent to the Si5338's VCO architecture and applies identically to SI5338M-B04945-GMR.

What is the maximum output current per VDDO pin on the SI5338M-B04945-GMR?

The SI5338M-B04945-GMR does not specify a maximum current per VDDO pin in absolute terms; instead, its DC characteristics define output buffer supply current (IDDOx) based on format and frequency-for example, LVPECL at 710 MHz draws ≤30 mA, LVDS at 710 MHz draws ≤8 mA, and CMOS at 200 MHz draws ≤18 mA (3.3 V). Total VDDO supply current depends on active outputs and formats. Designers must ensure each VDDOx net has adequate copper area and decoupling to handle peak transient loads, especially during simultaneous edge transitions across multiple outputs.

Is the SI5338M-B04945-GMR RoHS and REACH compliant?

Yes, the SI5338M-B04945-GMR is RoHS Directive 2011/65/EU compliant and REACH SVHC-free per Skyworks' material declarations. It uses lead-free (Pb-free) 24-QFN packaging with NiPdAu terminal finish and conforms to JEDEC J-STD-020 moisture sensitivity level 3 (MSL3) for surface-mount assembly. Full compliance documentation-including substance declarations and test reports-is available through Skyworks' Quality Portal and is referenced in the "Environmental Compliance" section of the Si5338 datasheet revision 1.6. SI5338M-B04945-GMR meets export requirements for EU, China, Korea, and Turkey.

SI5338M-B04945-GMR Specifications

Product attributes: Attribute value

Manufacturer:: Skyworks Solutions Inc.

Series:: MultiSynth™

Package/Case:: 24-VFQFN Exposed Pad

Packaging:: Tape & Reel (TR)

Product Status:: Active

Programmable:: Not Verified

PLL:: -

Main Purpose:: -

Input:: -

Output:: -

Number of Circuits:: -

Ratio - Input:Output:: -

Differential - Input:Output:: -

Frequency - Max:: -

Voltage - Supply:: -

Operating Temperature:: -

Mounting Type:: Surface Mount

Grade:: -

Qualification:: -

Supplier Device Package:: 24-QFN (4x4)

SI5338M-B04945-GMR FAQ

1.How can I place an order for SI5338M-B04945-GMR through Aetrix?

Please submit a Request for Quotation (RFQ) for SI5338M-B04945-GMR on Aetrix. Our sales agent will provide a competitive quotation and guide you through the order confirmation once you accept the terms.

2.Are the price and stock information for SI5338M-B04945-GMR reliable?

The price and inventory of SI5338M-B04945-GMR are updated periodically and may fluctuate due to market conditions. Stock and pricing data are typically refreshed every 24 hours. Quotation validity for SI5338M-B04945-GMR is usually 5 days.

3.What payment methods are accepted for SI5338M-B04945-GMR?

We accept Wire Transfer, PayPal, Credit Card, Western Union, MoneyGram, and Escrow for SI5338M-B04945-GMR transactions.

Note: Certain payment methods may incur a processing fee.

4.How is shipping managed for SI5338M-B04945-GMR?

SI5338M-B04945-GMR orders can be shipped via leading logistics carriers, including DHL, UPS, FedEx, TNT, or Registered Mail.

Once your SI5338M-B04945-GMR order is processed, you will receive an email with the shipment details and tracking number.

Note: Tracking information may take up to 24 hours to appear. Express delivery typically takes 3–5 business days.

5.How can I obtain technical support or documentation for SI5338M-B04945-GMR?

For technical support, including SI5338M-B04945-GMR datasheets, pinout diagrams, or application guidance, please contact our engineering support team. They can provide detailed documentation and assistance for your SI5338M-B04945-GMR requirements.

6.How does Aetrix verify that SI5338M-B04945-GMR is sourced from the original manufacturer or authorized distributors?

All SI5338M-B04945-GMR products on Aetrix are procured from qualified distributors and authorized channels. Our dedicated quality assurance team conducts strict verification, including traceability checks and, if necessary, third-party testing. This ensures that SI5338M-B04945-GMR meets industry standards.

7.What is the process for return or replacement of SI5338M-B04945-GMR?

All SI5338M-B04945-GMR units undergo pre-shipment inspection (PSI). If there is an issue with SI5338M-B04945-GMR, returns or replacements are accepted under the following conditions:

1.Quantity discrepancies, incorrect items, or visible external defects (such as breakage or corrosion), acknowledged by Aetrix.

2.The issue is reported within 90 days of delivery.

3.The SI5338M-B04945-GMR part is unused and in its original packaging.

Return procedure for SI5338M-B04945-GMR:

1.Submit a request within 90 days.

2.Obtain a Return Material Authorization (RMA) from Aetrix.

Tech Hub

2026-09-09 Counterfeit Electronic Components: How to Detect, Authenticate, and Test Suspect Parts

Counterfeit components can hide behind convincing markings and passing basic function tests. This engineering reference covers source traceability, external inspection, X-ray, XRF, electrical testing, …

2026-09-08 Obsolete Electronic Components: How to Source and Evaluate Replacements

A practical engineering and sourcing framework covering lifecycle verification, lifetime-buy calculations, replacement qualification, supplier checks and counterfeit-risk controls.

2026-09-07 TTL vs CMOS Logic Levels: 74HC and 74HCT Compatibility Explained

TTL and CMOS logic families differ in thresholds, loading, output drive, power and timing. This engineering guide compares 74HC and 74HCT, calculates noise margins and checks 3.3 V/5 V compatibility.

2026-09-04 Logic Level Shifter: How to Connect 3.3V and 5V Logic Safely

A practical engineering guide to 3.3V and 5V logic compatibility, input thresholds, resistor dividers, translator ICs, MOSFET level shifting, I2C pull-ups, timing limits and power-sequencing risks.

2026-09-03 74HC595 vs TPIC6B595: Output Drive, Pinout, Current, and Load Selection

The 74HC595 uses push-pull logic outputs, while the TPIC6B595 uses 50 V open-drain DMOS sinks for higher-power loads. This guide compares timing, current limits, 3.3 V interfacing, load wiring, thermal…

2026-09-02 74HC595 Pinout, Timing, Output Current, and Applications

The 74HC595 converts serial data into eight stable parallel outputs. This guide covers pin functions, shift and storage timing, OE and MR behavior, drive-current limits, cascading, voltage compatibilit…

2026-09-01 Latch vs Flip-Flop: Timing, Differences and Design Choices

A technical comparison of level-sensitive latches and edge-triggered flip-flops, covering timing windows, setup and hold limits, master–slave operation, time borrowing, race-through, HDL inference and…

2026-08-30 D Latch Circuit: Truth Table, Timing, ICs and Applications

A D latch stores one bit while Enable controls when data can pass. This reference covers gate-level operation, truth tables, transparency, setup and hold timing, LE versus OE, common ICs and practical …

2026-08-28 SR Latch Explained: NOR and NAND Circuits, Truth Tables, and Applications

An SR latch stores one bit through cross-coupled feedback. This engineering reference covers NOR and NAND implementations, truth tables, forbidden-state recovery, gated operation, switch debouncing, fa…

2026-08-27 Latch Circuit: SR and D Latches, Truth Tables, Timing, and Applications

Latch circuits retain one bit through feedback. This technical reference covers SR and D latches, truth tables, transparency, timing limits, latch-versus-flip-flop behavior, applications and common log…