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Home > Products > Integrated Circuits (ICs) > Clock/Timing > Application Specific Clock/Timing

Skyworks Solutions Inc. SI5338M-B05075-GMR

Name: SI5338M-B05075-GMR
Brand: Skyworks Solutions Inc.
SKU: SI5338M-B05075-GMR
Price: 2.40 USD
Availability: InStock
Rating: 5 (2 reviews)

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Part No.:: SI5338M-B05075-GMR

Manufacturer:: Skyworks Solutions Inc.

Category:: Application Specific Clock/Timing

Package:: 24-VFQFN Exposed Pad

Datasheet:: SI5338M-B05075-GMR.pdf

Description:: I2C CONTROL, 4-OUTPUT, ANY FREQU

Quantity:: RFQ Add To RFQ list

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Product details

Overview

SI5338M-B05075-GMR from Skyworks Solutions is a quad-output, I²C-programmable clock generator with MultiSynth™ frequency synthesis, delivering four independent differential or single-ended clocks (0.16–710 MHz), 0.7 ps RMS typical phase jitter, PCIe Gen 1–4 and SRNS compliance, and operation from 1.8/2.5/3.3 V core supply in a 4×4 mm 24-QFN package. It replaces up to four crystal oscillators in high-speed serial interface timing applications.

For engineers reviewing the SI5338M-B05075-GMR datasheet, SI5338M-B05075-GMR pinout, SI5338M-B05075-GMR application, or SI5338M-B05075-GMR equivalent, key selection criteria include PCIe Gen 4 SRNS jitter performance (0.15–0.45 ps RMS), independent output voltage per driver (1.5/1.8/2.5/3.3 V), programmable phase adjustment (<20 ps steps), spread-spectrum capability (0.5–5.0% at 33–63 kHz), and flexible reference input support (8–30 MHz crystal, 5–710 MHz differential).

Technical Context

The SI5338M-B05075-GMR implements a two-stage PLL architecture: a high-stability integer-N PLL synthesizes a VCO frequency (Fvco), followed by four independent MultiSynth™ fractional-N dividers enabling any-frequency generation on each of CLK0A/B through CLK3A/B. Each output stage supports format selection (LVPECL/LVDS/HCSL/CMOS/SSTL/HSTL) and independent VDDO supply (1.4–3.63 V).

It features dual reference inputs (IN1/IN2 differential, IN3/IN4 single-ended, IN5/IN6 differential), loss-of-lock and loss-of-signal alarms, I²C/SMBus configuration interface, and pin-controlled frequency/phase increment/decrement with glitchless 1 ppm step resolution and <20 ps phase step accuracy.

Key Specifications

Parameter	Value and Actual Design Meaning
Phase Jitter (RMS)	0.7 ps typical (12 kHz–20 MHz); meets PCIe Gen 3/4 SRNS and GbE jitter requirements
Output Frequency Range	0.16–710 MHz per channel; supports Fvco/4 and Fvco/6 for >350 MHz outputs
Input Reference Support	8–30 MHz crystal, 5–200 MHz CMOS, 5–350 MHz SSTL/HSTL, 5–710 MHz differential
Output Driver Flexibility	Up to 4 differential (LVPECL/LVDS/HCSL/CML) or 8 single-ended (CMOS/SSTL/HSTL) outputs
Supply Voltages	Core: 1.8/2.5/3.3 V ±10%; Output buffers: independently configurable 1.5/1.8/2.5/3.3 V
Operating Temperature	–40 °C to +85 °C; qualified for industrial embedded and telecom line card environments
Package	24-pin QFN, 4 × 4 mm, 0.5 mm pitch; thermally enhanced with exposed pad

Pinout & Package

SI5338M-B05075-GMR uses a 24-lead QFN package (4 × 4 mm, 0.5 mm pitch) with exposed thermal pad. Pin assignments are fixed across Si5338 family variants per Skyworks Rev. 1.6 datasheet.

Pin/Terminal	Circuit Role	Design Meaning
IN1, IN2	Differential reference input pair	Accepts 5–710 MHz AC-coupled differential clock; requires external 100 Ω termination
IN3, IN4	Single-ended reference inputs	Support 5–200 MHz CMOS-level signals; VIH = 0.7×VDD, VIL = 0.3×VDD
CLK0A, CLK0B – CLK3A, CLK3B	Differential clock outputs	Four independent pairs; each configurable as LVPECL/LVDS/HCSL/CML with dedicated VDDOx
VDDO0–VDDO3	Output buffer supply pins	Enable independent voltage setting per output bank (1.4–3.63 V)
VDD	Core supply	1.8/2.5/3.3 V ±10%; PSRR optimized for low-noise timing operation
SCL, SDA	I²C/SMBus interface	Standard 100/400 kHz operation; supports ClockBuilder Pro programming
INTR	Interrupt output	Open-drain status signal for loss-of-lock and loss-of-signal alarms

Key Features

Feature	Design Value
MultiSynth™ Any-Frequency Synthesis	Four independent outputs with true zero-ppm accuracy and 1 ppb resolution - eliminates need for multiple crystals
PCIe Gen 4 Common Clock Compliance	0.15–0.45 ps RMS jitter (10 kHz–50 MHz) meets PCIe Base Spec 4.0 rev. 0.5 for common clock mode
Independent Output Voltage Control	Each of four output banks powered separately (1.5/1.8/2.5/3.3 V), enabling mixed-voltage system interfacing without level shifters
Glitchless Frequency Adjustment	Pin-controlled 1 ppm step increments/decrements with sub-1 ns update time - enables real-time dynamic frequency scaling
Programmable Phase Offset	±45 ns range with <20 ps step resolution per output - supports precise skew alignment in multi-lane SerDes systems
Configurable Spread Spectrum	0.5–5.0% down-spread at 33–63 kHz on any output - reduces EMI without compromising timing integrity

Applications

PCIe Gen 4 Switch Timing	Ethernet Switch/Routing
Use Scenario: High-density 32-lane PCIe Gen 4 switch ASIC requiring synchronized, low-jitter clocks for SERDES lanes and management logic. IC Role / Device Role / Timing Role: Primary clock generator providing four independent 100 MHz HCSL clocks (two for root complex, two for endpoint interfaces) with SRNS-compliant jitter. Use Value: Meets PCIe Gen 4 SRNS RMS jitter limit (≤0.32 ps) while eliminating four discrete oscillators and reducing board area by >60%.	Use Scenario: 10 GbE/25 GbE Ethernet switch fabric with multi-port PHYs needing phase-aligned clocks across data paths and control planes. IC Role / Device Role / Timing Role: Quad-output timing source delivering 156.25 MHz LVDS (PHY), 125 MHz LVDS (MAC), 25 MHz CMOS (management), and 100 MHz HCSL (PCIe host interface). Use Value: Independent voltage per output (1.8 V for LVDS, 3.3 V for CMOS) avoids external level translation; <20 ps phase step enables fine-grained skew tuning.
Broadcast Video Timing	Processor & FPGA Clocking
Use Scenario: SMPTE ST 2082/ST 2110 broadcast video router requiring ultra-low-jitter, phase-coherent clocks for 12G-SDI and IP media transport. IC Role / Device Role / Timing Role: Master clock synthesizer generating 27 MHz (SDI), 74.25 MHz (HD-SDI), 148.5 MHz (3G-SDI), and 297 MHz (12G-SDI) from a single 25 MHz crystal reference. Use Value: 0.7 ps RMS jitter ensures compliance with SMPTE RP 184 jitter tolerance; MultiSynth™ eliminates crystal inventory complexity.	Use Scenario: Heterogeneous compute platform with ARM SoC, Xilinx FPGA, and DDR4 memory subsystem requiring coordinated clock domains. IC Role / Device Role / Timing Role: Central timing hub supplying 500 MHz LVDS (FPGA transceivers), 200 MHz LVDS (SoC AXI), 100 MHz HCSL (PCIe), and 133 MHz CMOS (DDR4 controller). Use Value: Independent output format and voltage per channel (e.g., 1.8 V LVDS for FPGA, 2.5 V HCSL for PCIe) simplifies power domain partitioning and reduces BOM count.

PCIe Gen 4 Switch Timing

Ethernet Switch/Routing

Use Scenario: High-density 32-lane PCIe Gen 4 switch ASIC requiring synchronized, low-jitter clocks for SERDES lanes and management logic.

IC Role / Device Role / Timing Role: Primary clock generator providing four independent 100 MHz HCSL clocks (two for root complex, two for endpoint interfaces) with SRNS-compliant jitter.

Use Value: Meets PCIe Gen 4 SRNS RMS jitter limit (≤0.32 ps) while eliminating four discrete oscillators and reducing board area by >60%.

Use Scenario: 10 GbE/25 GbE Ethernet switch fabric with multi-port PHYs needing phase-aligned clocks across data paths and control planes.

IC Role / Device Role / Timing Role: Quad-output timing source delivering 156.25 MHz LVDS (PHY), 125 MHz LVDS (MAC), 25 MHz CMOS (management), and 100 MHz HCSL (PCIe host interface).

Use Value: Independent voltage per output (1.8 V for LVDS, 3.3 V for CMOS) avoids external level translation; <20 ps phase step enables fine-grained skew tuning.

Broadcast Video Timing

Processor & FPGA Clocking

Use Scenario: SMPTE ST 2082/ST 2110 broadcast video router requiring ultra-low-jitter, phase-coherent clocks for 12G-SDI and IP media transport.

IC Role / Device Role / Timing Role: Master clock synthesizer generating 27 MHz (SDI), 74.25 MHz (HD-SDI), 148.5 MHz (3G-SDI), and 297 MHz (12G-SDI) from a single 25 MHz crystal reference.

Use Value: 0.7 ps RMS jitter ensures compliance with SMPTE RP 184 jitter tolerance; MultiSynth™ eliminates crystal inventory complexity.

Use Scenario: Heterogeneous compute platform with ARM SoC, Xilinx FPGA, and DDR4 memory subsystem requiring coordinated clock domains.

IC Role / Device Role / Timing Role: Central timing hub supplying 500 MHz LVDS (FPGA transceivers), 200 MHz LVDS (SoC AXI), 100 MHz HCSL (PCIe), and 133 MHz CMOS (DDR4 controller).

Use Value: Independent output format and voltage per channel (e.g., 1.8 V LVDS for FPGA, 2.5 V HCSL for PCIe) simplifies power domain partitioning and reduces BOM count.

Equivalent & Alternatives

The following parts are listed as comparable options for similar quad-output programmable clock generator applications.

Alternative Part	Technical Difference	Application Difference	Selection Advice
Si5332A-D05089-GM	Higher integration: 8 outputs, integrated jitter cleaner, lower 0.35 ps RMS jitter; 5×5 mm 32-QFN package	Targeted at ultra-low-jitter 100G/400G optical modules and AI accelerator timing; requires more PCB area and higher cost	Select when sub-0.4 ps RMS jitter and >4 outputs are required; not drop-in compatible due to pin count and footprint change
ICS853S01AGI-01LFT	Fixed-frequency quad LVDS generator (100/125/156.25/200 MHz); no I²C programming; 0.9 ps RMS jitter; 4×4 mm 24-QFN	Designed for cost-sensitive, high-volume Ethernet PHY clocking where frequency flexibility is unnecessary	Choose for simplified design and lower unit cost if only standard Ethernet frequencies are needed; lacks reprogrammability and spread spectrum

Compared with Si5332A-D05089-GM and ICS853S01AGI-01LFT, SI5338M-B05075-GMR uniquely balances field-programmability, PCIe Gen 4 compliance, and compact 24-QFN packaging - making it optimal for mid-range networking and embedded systems where flexibility, jitter margin, and board space are co-constrained.

Availability

SI5338M-B05075-GMR is available at Aetrix Electronics and suitable for PCIe Gen 4 switch timing, Ethernet switching/routing, broadcast video infrastructure, and processor/FPGA clocking applications requiring stable component supply, long-term lifecycle support, and traceable sourcing.

Supply support for SI5338M-B05075-GMR includes scheduled delivery planning, volume procurement assistance, BOM continuity management, traceable sourcing, and lifecycle availability coordination for OEM customers, industrial embedded developers, connected-device designers, and electronics production programs.

Manufacturer

Skyworks Solutions is a global leader in analog and mixed-signal semiconductors, specializing in RF, mobile, infrastructure, and timing solutions with over 40 years of RF and clocking innovation.

The Si5338 product line was designed specifically for high-performance, multi-protocol serial interface timing - targeting PCIe, Ethernet, Fibre Channel, and broadcast video systems requiring flexible, low-jitter, software-configurable clock synthesis in minimal footprint.

FAQ

What is the maximum output frequency supported by SI5338M-B05075-GMR?

The SI5338M-B05075-GMR supports up to 710 MHz on LVPECL/LVDS/CML outputs, 350 MHz on SSTL/HSTL, 250 MHz on HCSL, and 200 MHz on CMOS. However, only two unique frequencies above 350 MHz can be simultaneously generated (Fvco/4 and Fvco/6), as defined in the Si5338 functional description. All outputs maintain 0.7 ps RMS typical jitter within their respective format limits.

Does SI5338M-B05075-GMR support PCIe Gen 4 Separate Reference No Spread (SRNS) mode?

Yes, SI5338M-B05075-GMR is explicitly compliant with PCIe Gen 4 SRNS requirements, achieving 0.11–0.32 ps RMS jitter (10 kHz–50 MHz) when configured with PLL bandwidth of 2–4 MHz or 2–5 MHz and CDR = 10 MHz. This is verified per PCI-Express Base Specification 4.0 rev. 0.5 and measured using the Skyworks PCIe Clock Jitter Tool.

Can SI5338M-B05075-GMR generate different output voltages on each channel?

Yes, SI5338M-B05075-GMR provides independent VDDO0–VDDO3 pins, allowing each of its four output banks to be powered at 1.5 V, 1.8 V, 2.5 V, or 3.3 V. This enables direct interfacing with mixed-voltage devices (e.g., 1.8 V FPGA transceivers, 3.3 V microcontrollers) without external level shifters, reducing BOM count and signal integrity risk.

How is SI5338M-B05075-GMR programmed, and is ClockBuilder Pro required?

SI5338M-B05075-GMR is programmed via its I²C/SMBus interface (SCL/SDA pins). While ClockBuilder Pro software from Skyworks simplifies configuration and validation, register-level programming is fully documented in the Si5338 register map. The device ships with factory-programmed default settings, and all configurations - including frequency, format, voltage, and spread spectrum - are stored in one-time-programmable (OTP) NVM.

What reference inputs does SI5338M-B05075-GMR accept?

SI5338M-B05075-GMR accepts six reference inputs: two differential pairs (IN1/IN2, IN5/IN6) supporting 5–710 MHz; two single-ended inputs (IN3, IN4) supporting 5–200 MHz CMOS; and an on-chip oscillator for 8–30 MHz crystals. Input flexibility allows use with legacy crystals, high-speed differential sources, or low-cost single-ended clocks - all while maintaining sub-ps jitter performance.

SI5338M-B05075-GMR Specifications

Product attributes: Attribute value

Manufacturer:: Skyworks Solutions Inc.

Series:: MultiSynth™

Package/Case:: 24-VFQFN Exposed Pad

Packaging:: Tape & Reel (TR)

Product Status:: Active

Programmable:: Not Verified

PLL:: -

Main Purpose:: -

Input:: -

Output:: -

Number of Circuits:: -

Ratio - Input:Output:: -

Differential - Input:Output:: -

Frequency - Max:: -

Voltage - Supply:: -

Operating Temperature:: -

Mounting Type:: Surface Mount

Grade:: -

Qualification:: -

Supplier Device Package:: 24-QFN (4x4)

SI5338M-B05075-GMR FAQ

1.How can I place an order for SI5338M-B05075-GMR through Aetrix?

Please submit a Request for Quotation (RFQ) for SI5338M-B05075-GMR on Aetrix. Our sales agent will provide a competitive quotation and guide you through the order confirmation once you accept the terms.

2.Are the price and stock information for SI5338M-B05075-GMR reliable?

The price and inventory of SI5338M-B05075-GMR are updated periodically and may fluctuate due to market conditions. Stock and pricing data are typically refreshed every 24 hours. Quotation validity for SI5338M-B05075-GMR is usually 5 days.

3.What payment methods are accepted for SI5338M-B05075-GMR?

We accept Wire Transfer, PayPal, Credit Card, Western Union, MoneyGram, and Escrow for SI5338M-B05075-GMR transactions.

Note: Certain payment methods may incur a processing fee.

4.How is shipping managed for SI5338M-B05075-GMR?

SI5338M-B05075-GMR orders can be shipped via leading logistics carriers, including DHL, UPS, FedEx, TNT, or Registered Mail.

Once your SI5338M-B05075-GMR order is processed, you will receive an email with the shipment details and tracking number.

Note: Tracking information may take up to 24 hours to appear. Express delivery typically takes 3–5 business days.

5.How can I obtain technical support or documentation for SI5338M-B05075-GMR?

For technical support, including SI5338M-B05075-GMR datasheets, pinout diagrams, or application guidance, please contact our engineering support team. They can provide detailed documentation and assistance for your SI5338M-B05075-GMR requirements.

6.How does Aetrix verify that SI5338M-B05075-GMR is sourced from the original manufacturer or authorized distributors?

All SI5338M-B05075-GMR products on Aetrix are procured from qualified distributors and authorized channels. Our dedicated quality assurance team conducts strict verification, including traceability checks and, if necessary, third-party testing. This ensures that SI5338M-B05075-GMR meets industry standards.

7.What is the process for return or replacement of SI5338M-B05075-GMR?

All SI5338M-B05075-GMR units undergo pre-shipment inspection (PSI). If there is an issue with SI5338M-B05075-GMR, returns or replacements are accepted under the following conditions:

1.Quantity discrepancies, incorrect items, or visible external defects (such as breakage or corrosion), acknowledged by Aetrix.

2.The issue is reported within 90 days of delivery.

3.The SI5338M-B05075-GMR part is unused and in its original packaging.

Return procedure for SI5338M-B05075-GMR:

1.Submit a request within 90 days.

2.Obtain a Return Material Authorization (RMA) from Aetrix.

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