Skyworks Solutions Inc. SI5338M-B05237-GM

Overview

SI5338M-B05237-GM from Skyworks Solutions is a quad-output, I²C-programmable clock generator with MultiSynth™ frequency synthesis. It delivers four independent, any-frequency outputs (0.16–710 MHz) with 0.7 ps RMS typical phase jitter, PCIe Gen 1–4 compliance, and support for LVPECL/LVDS/HCSL/CMOS/SSTL/HSTL formats. It serves as a low-jitter replacement for up to four crystal oscillators in high-speed serial interface timing.

For engineers reviewing the SI5338M-B05237-GM datasheet, SI5338M-B05237-GM pinout, SI5338M-B05237-GM application, or SI5338M-B05237-GM equivalent, key selection criteria include differential output jitter performance (0.7 ps RMS), PCIe Gen 4 SRNS compliance, independent per-output voltage control (1.5–3.3 V), spread-spectrum programmability (0.5–5.0% down-spread), and 24-QFN package compatibility with space-constrained FPGA/ASIC clock trees.

Technical Context

The SI5338M-B05237-GM implements a two-stage PLL architecture: a high-stability reference stage followed by four independent MultiSynth™ fractional-N synthesis blocks. Each output driver operates with its own R, M, and P dividers, enabling true zero-ppm frequency accuracy across all four outputs without shared divider constraints.

It supports flexible input references-including 8–30 MHz crystals, 5–200 MHz CMOS, and 5–710 MHz differential inputs-and provides independent phase adjustment (<20 ps step resolution), glitchless frequency increment/decrement (1 ppm steps), and loss-of-lock/loss-of-signal monitoring via dedicated INTR pin.

Key Specifications

Pinout & Package

SI5338M-B05237-GM is housed in a 24-lead, 4 mm × 4 mm QFN package with wettable flank leads and an exposed thermal pad. Pin 1 is located at top-left (IN1), with pins numbered counter-clockwise. The package supports reflow soldering per JEDEC J-STD-020 (peak 260 °C).

Key Features

Applications

Equivalent & Alternatives

The following parts are listed as comparable options for similar quad-output programmable clock generator applications.

Compared with Si5332A-D05237-GM, SI5338M-B05237-GM offers lower cost and smaller footprint but lacks integrated LDOs and has higher jitter floor; compared with ICS853S02AMT, SI5338M-B05237-GM trades off absolute jitter for full frequency programmability and multi-format flexibility-critical for evolving multi-standard platforms.

Availability

SI5338M-B05237-GM is available at Aetrix Electronics and suitable for PCIe Gen 4 switch timing, Ethernet switch clocking, broadcast video sync generation, and FPGA-based video processing requiring stable component supply, long-term lifecycle assurance, and traceable sourcing.

Supply support for SI5338M-B05237-GM includes scheduled delivery planning, volume procurement assistance, BOM continuity management, traceable sourcing, and lifecycle availability coordination for OEM customers, industrial embedded developers, connected-device designers, and electronics production programs.

Manufacturer

Skyworks Solutions is a global semiconductor company specializing in analog and mixed-signal connectivity solutions, with leadership in RF, timing, and power management ICs for infrastructure, automotive, and mobile markets.

The SI5338 family is designed as a high-performance, software-configurable clock generator platform targeting high-speed serial interface timing in datacenter, telecom, and broadcast equipment-emphasizing jitter performance, output flexibility, and ease of configuration via ClockBuilder Pro.

FAQ

What is the maximum output frequency supported by SI5338M-B05237-GM?

The SI5338M-B05237-GM supports up to 710 MHz on LVPECL/LVDS/CML outputs, 250 MHz on HCSL, and 200 MHz on CMOS. However, only two unique frequencies above 350 MHz can be generated simultaneously-specifically Fvco/4 and Fvco/6-as defined by the internal VCO architecture. All frequencies are synthesized with 0 ppm precision using MultiSynth™ technology.

Does SI5338M-B05237-GM support PCIe Gen 4 Separate Reference No Spread (SRNS) compliance?

Yes, SI5338M-B05237-GM meets PCIe Gen 4 SRNS requirements with ≤0.32 ps RMS jitter (typical) when configured with a PLL bandwidth of 2–4 MHz and CDR = 10 MHz. This is verified per PCI Express Base Specification 4.0 rev. 0.5 and measured using the Skyworks PCIe Clock Jitter Tool and Intel Clock Jitter Tool v1.6.4.

Can SI5338M-B05237-GM generate different output voltage levels on each clock pair?

Yes, SI5338M-B05237-GM provides four independent VDDOx supply pins (VDDO0–VDDO3), each configurable for 1.5 V, 1.8 V, 2.5 V, or 3.3 V. This allows mixed-signal systems-such as those combining LVDS (2.5 V) and HCSL (1.8 V) outputs-to drive diverse receivers without level-shifting components.

How is SI5338M-B05237-GM programmed, and is external non-volatile memory required?

SI5338M-B05237-GM is programmed via its I²C/SMBus interface using Skyworks' ClockBuilder Pro software. Configuration is stored in on-chip one-time-programmable (OTP) memory, so no external EEPROM or flash is required. Factory pre-programmed devices boot with valid clocks within 2 ms of power-on.

What input reference options does SI5338M-B05237-GM support?

SI5338M-B05237-GM accepts multiple reference sources: an 8–30 MHz fundamental-mode crystal on IN1/IN2; 5–200 MHz CMOS on IN3/IN4; or 5–710 MHz differential signals (LVPECL/LVDS/HCSL/CML) on IN1/IN2 or IN5/IN6. Input flexibility enables use in both crystal-referenced and system-synchronized timing architectures.