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Home > Products > Integrated Circuits (ICs) > Clock/Timing > Application Specific Clock/Timing

Skyworks Solutions Inc. SI5338M-B05693-GMR

Name: SI5338M-B05693-GMR
Brand: Skyworks Solutions Inc.
SKU: SI5338M-B05693-GMR
Price: 2.40 USD
Availability: InStock
Rating: 5 (2 reviews)

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Part No.:: SI5338M-B05693-GMR

Manufacturer:: Skyworks Solutions Inc.

Category:: Application Specific Clock/Timing

Package:: 24-VFQFN Exposed Pad

Datasheet:: SI5338M-B05693-GMR.pdf

Description:: I2C CONTROL, 4-OUTPUT, ANY FREQU

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Product details

Overview

SI5338M-B05693-GMR from Skyworks Solutions is an I²C-programmable quad clock generator with four independently configurable differential or single-ended outputs, 0.7 ps RMS typical phase jitter, PCIe Gen 1–4 Common Clock and Gen 3 SRNS compliance, and operation from 1.8/2.5/3.3 V core supply in a 4 × 4 mm 24-QFN package. It replaces up to four crystal oscillators in Ethernet switch/router and FPGA clocking systems.

For engineers reviewing the SI5338M-B05693-GMR datasheet, SI5338M-B05693-GMR pinout, SI5338M-B05693-GMR application, or SI5338M-B05693-GMR equivalent, key selection considerations include its MultiSynth™-based any-frequency synthesis (0.16–710 MHz per output), independent output voltage per driver (1.5–3.3 V), spread-spectrum capability (0.5–5.0% down-spread), loss-of-lock/loss-of-signal alarms, and I²C/SMBus programmability.

Technical Context

The SI5338M-B05693-GMR implements a two-stage PLL architecture: a high-stability input stage with programmable R-divider followed by a fractional-N MultiSynth™ synthesis stage per output path. Each of the four output drivers supports independent format selection (LVPECL/LVDS/HCSL/CMOS/SSTL/HSTL) and voltage rail (VDDO0–VDDO3).

It features independent phase adjustment (<20 ps step resolution), frequency increment/decrement (1 ppm steps), and configurable spread-spectrum modulation (33–63 kHz rate, 0.5–5.0% deviation) on any output. External feedback mode enables zero-delay operation, while dedicated INTR pin reports loss-of-lock and loss-of-signal events.

Key Specifications

Parameter	Value and Actual Design Meaning
Phase Jitter (RMS)	0.7 ps - meets PCIe Gen 3 SRNS and GbE jitter requirements at 125 MHz output
Output Frequency Range	0.16–710 MHz - supports LVPECL/LVDS up to 710 MHz, HCSL up to 250 MHz, CMOS up to 200 MHz
Input Reference Support	Crystal (8–30 MHz), CMOS (5–200 MHz), SSTL/HSTL (5–350 MHz), differential (5–710 MHz)
Supply Voltages	VDD = 1.8/2.5/3.3 V ±10%; VDDOx = 1.4–3.63 V - enables mixed-voltage system interfacing
Package	24-pin QFN, 4 × 4 mm - space-constrained PCBs with exposed thermal pad
Operating Temperature	–40 to +85 °C - industrial-grade thermal performance without derating
Core Supply Current	45 mA typ at 100 MHz on all outputs - low-power timing for thermally sensitive designs

Pinout & Package

SI5338M-B05693-GMR uses a 24-pin QFN package (4 × 4 mm, 0.5 mm pitch) with exposed thermal pad. Pin functions are defined per Skyworks Rev. 1.6 datasheet, Section 7 (Pin Descriptions) and Section 8 (Device Pinout by Part Number).

Pin/Terminal	Circuit Role	Design Meaning
IN1, IN2, IN5, IN6	Differential Input Pairs	Accept AC-coupled differential reference clocks up to 710 MHz; require external 100 Ω termination
IN3, IN4	Single-Ended Input Pins	Support CMOS/SSTL/HSTL inputs (5–350 MHz); VIH/VIL referenced to VDD
CLK0A–CLK3B	Differential Output Pairs	Four independent output channels; each pair configurable as LVPECL/LVDS/HCSL/CML
VDDO0–VDDO3	Output Buffer Supplies	Independent voltage rails per output bank enable mixed-signal interface (e.g., 1.8 V FPGA + 3.3 V PHY)
SCL, SDA	I²C Interface	Standard SMBus-compatible 2-wire serial bus for configuration and status readback
INTR	Interrupt Output	Open-drain alarm signal indicating loss-of-lock or loss-of-signal on any input

Key Features

Feature	Design Value
MultiSynth™ Any-Frequency Synthesis	Generates four independent output frequencies with true zero-ppm accuracy and 1 ppb resolution
PCIe Gen 1–4 Compliance	Fully satisfies PCIe Gen 3 SRNS and Gen 4 common-clock jitter specs (≤0.32 ps RMS)
Independent Output Voltage Control	VDDO0–VDDO3 pins allow per-output voltage setting (1.5/1.8/2.5/3.3 V) for multi-rail system clocking
Glitchless Frequency Adjustment	Hardware-supported frequency increment/decrement via PINC/FDEC pins in 1 ppm steps without output interruption
Programmable Spread Spectrum	Configurable SSC on any output: 0.5–5.0% spread, 33–63 kHz modulation rate, down-spread only
Loss Detection Alarms	Dedicated INTR pin asserts on loss-of-lock (tLOL ≤ 10 ms) or loss-of-signal (tLOS ≤ 5 µs) for system monitoring

Applications

Ethernet Switch/Router Timing	PCIe Gen 3/4 Clocking
Use Scenario: High-port-count 10GbE/25GbE switches requiring multiple synchronized clocks for MAC, PHY, and packet buffer interfaces. IC Role / Device Role / Timing Role: Quad clock generator providing independent 156.25 MHz (XAUI), 125 MHz (XFI), 100 MHz (PCIe), and 25 MHz (management) clocks with sub-ps jitter. Use Value: Eliminates four discrete oscillators; ensures PCIe Gen 3 SRNS compliance (≤0.32 ps RMS) and <100 ps output skew across ports.	Use Scenario: Server motherboard with dual CPU sockets, multiple PCIe Gen 4 x16 slots, and integrated CXL memory controllers. IC Role / Device Role / Timing Role: Common clock source delivering 100 MHz PCIe reference to root complex, endpoint, and switch ICs with matched trace lengths. Use Value: Meets PCIe Gen 4 common-clock TJ spec (≤33.6 ps pk-pk) and supports simultaneous spread-spectrum on selected outputs to reduce EMI.
Broadcast Video/Audio Sync	FPGA & Processor Clocking
Use Scenario: SMPTE 2110 IP video router with genlock, frame sync, and audio sample rate conversion across 64+ channels. IC Role / Device Role / Timing Role: Precision clock synthesizer generating 27 MHz (SDI), 74.25 MHz (HD-SDI), 148.5 MHz (3G-SDI), and 48 kHz audio word clock from a single 10 MHz GPSDO reference. Use Value: Achieves <±20 ps phase step resolution and <0.7 ps RMS jitter-critical for lip-sync accuracy and AES67 audio timing.	Use Scenario: Industrial FPGA-based motion controller with real-time EtherCAT, encoder feedback, and analog I/O subsystems. IC Role / Device Role / Timing Role: Configurable clock hub supplying 100 MHz FPGA fabric clock, 50 MHz ADC sampling clock, 200 MHz DDR3 interface clock, and 1 MHz watchdog timer clock. Use Value: Enables single-chip clock tree with independent voltage rails (1.2 V FPGA core, 3.3 V I/O, 2.5 V ADC) and glitchless frequency tuning during runtime.

Ethernet Switch/Router Timing

PCIe Gen 3/4 Clocking

Use Scenario: High-port-count 10GbE/25GbE switches requiring multiple synchronized clocks for MAC, PHY, and packet buffer interfaces.

IC Role / Device Role / Timing Role: Quad clock generator providing independent 156.25 MHz (XAUI), 125 MHz (XFI), 100 MHz (PCIe), and 25 MHz (management) clocks with sub-ps jitter.

Use Value: Eliminates four discrete oscillators; ensures PCIe Gen 3 SRNS compliance (≤0.32 ps RMS) and <100 ps output skew across ports.

Use Scenario: Server motherboard with dual CPU sockets, multiple PCIe Gen 4 x16 slots, and integrated CXL memory controllers.

IC Role / Device Role / Timing Role: Common clock source delivering 100 MHz PCIe reference to root complex, endpoint, and switch ICs with matched trace lengths.

Use Value: Meets PCIe Gen 4 common-clock TJ spec (≤33.6 ps pk-pk) and supports simultaneous spread-spectrum on selected outputs to reduce EMI.

Broadcast Video/Audio Sync

FPGA & Processor Clocking

Use Scenario: SMPTE 2110 IP video router with genlock, frame sync, and audio sample rate conversion across 64+ channels.

IC Role / Device Role / Timing Role: Precision clock synthesizer generating 27 MHz (SDI), 74.25 MHz (HD-SDI), 148.5 MHz (3G-SDI), and 48 kHz audio word clock from a single 10 MHz GPSDO reference.

Use Value: Achieves <±20 ps phase step resolution and <0.7 ps RMS jitter-critical for lip-sync accuracy and AES67 audio timing.

Use Scenario: Industrial FPGA-based motion controller with real-time EtherCAT, encoder feedback, and analog I/O subsystems.

IC Role / Device Role / Timing Role: Configurable clock hub supplying 100 MHz FPGA fabric clock, 50 MHz ADC sampling clock, 200 MHz DDR3 interface clock, and 1 MHz watchdog timer clock.

Use Value: Enables single-chip clock tree with independent voltage rails (1.2 V FPGA core, 3.3 V I/O, 2.5 V ADC) and glitchless frequency tuning during runtime.

Equivalent & Alternatives

The following parts are listed as comparable options for similar quad clock generator applications.

Alternative Part	Technical Difference	Application Difference	Selection Advice
Si5332A-D05693-GM	Higher integration: 8 outputs, lower jitter (0.35 ps RMS), supports JESD204B deterministic latency	Targeted at high-speed data converters and radar systems requiring sub-100 fs jitter and deterministic delay	Select when >4 outputs or JESD204B deterministic latency is required; not drop-in compatible due to different pinout and register map
ICS8430I-01T	Fixed-frequency quad LVDS generator (no I²C programming); 1.2 ps RMS jitter; 3.3 V only	Cost-sensitive applications with static clock trees (e.g., legacy telecom line cards)	Select only for fixed-frequency, non-programmable use cases; lacks spread spectrum, phase adjustment, and multi-voltage outputs

Compared with Si5332A-D05693-GM and ICS8430I-01T, SI5338M-B05693-GMR uniquely balances field-programmability, PCIe Gen 4 compliance, and mixed-voltage output flexibility in a compact 4×4 mm footprint-making it optimal for mid-complexity FPGA, switch, and broadcast platforms where reconfiguration and BOM consolidation are critical.

Availability

SI5338M-B05693-GMR is available at Aetrix Electronics and suitable for Ethernet switch/router timing, PCIe Gen 3/4 clocking, broadcast video/audio synchronization, and FPGA processor clocking requiring stable component supply and long-term design-in support.

Supply support for SI5338M-B05693-GMR includes scheduled delivery planning, volume procurement assistance, BOM continuity management, traceable sourcing, and lifecycle availability coordination for OEM customers, industrial embedded developers, connected-device designers, and electronics production programs.

Manufacturer

Skyworks Solutions is a global semiconductor company specializing in analog and mixed-signal connectivity solutions for wireless, broadband, automotive, and industrial markets.

The Si5338 product line delivers programmable, low-jitter clock generation for high-speed serial interfaces-including PCIe, Ethernet, and broadcast video-enabling system-level timing consolidation and jitter-critical signal integrity.

FAQ

What is the maximum output frequency supported by SI5338M-B05693-GMR in LVPECL mode?

The SI5338M-B05693-GMR supports LVPECL output frequencies up to 710 MHz, as specified in Table 6 of the Skyworks Rev. 1.6 datasheet. This capability applies when using differential outputs with appropriate termination and layout practices to maintain signal integrity and sub-ps jitter performance. The device achieves this using its MultiSynth™ fractional-N synthesis engine with Fvco/4 and Fvco/6 output paths enabled for frequencies above 350 MHz.

Does SI5338M-B05693-GMR support PCIe Gen 4 Common Clock compliance?

Yes, SI5338M-B05693-GMR meets PCIe Gen 4 Common Clock total jitter specification of ≤33.6 ps pk-pk and RMS jitter of ≤0.45 ps (10 kHz–50 MHz) per Table 12 in the Skyworks Rev. 1.6 datasheet. It achieves this with a PLL loop bandwidth of 2–5 MHz and is validated using the Skyworks PCIe Clock Jitter Tool and Intel Clock Jitter Tool v1.6.4 under HCSL 100 MHz output conditions.

Can SI5338M-B05693-GMR generate four different output voltages simultaneously?

Yes, SI5338M-B05693-GMR supports independent output voltage rails via VDDO0, VDDO1, VDDO2, and VDDO3 pins, enabling simultaneous 1.5 V, 1.8 V, 2.5 V, and 3.3 V outputs. Each output driver bank is powered separately, allowing direct interfacing with mixed-voltage components such as 1.2 V FPGAs, 1.8 V SerDes, 2.5 V PHYs, and 3.3 V microcontrollers without level shifters.

How is spread-spectrum clocking configured on SI5338M-B05693-GMR?

Spread-spectrum clocking on SI5338M-B05693-GMR is configured per-output via I²C registers controlling modulation rate (33–63 kHz), spread percentage (0.5–5.0%), and direction (down-spread only). Default settings are ~31.5 kHz rate and 0.5% down-spread. Configuration requires ClockBuilder Pro software or direct register writes; hardware pin control is not supported for SSC parameters.

What reference clock sources are compatible with SI5338M-B05693-GMR?

SI5338M-B05693-GMR accepts multiple reference types: external crystals (8–30 MHz), CMOS single-ended inputs (5–200 MHz), SSTL/HSTL inputs (5–350 MHz), and differential inputs (5–710 MHz). Crystal support includes on-chip load capacitance tuning (11–13 pF) and drive-level limiting (≤100 µW), verified per Tables 8–11 in the Skyworks Rev. 1.6 datasheet.

SI5338M-B05693-GMR Specifications

Product attributes: Attribute value

Manufacturer:: Skyworks Solutions Inc.

Series:: MultiSynth™

Package/Case:: 24-VFQFN Exposed Pad

Packaging:: Tape & Reel (TR)

Product Status:: Active

Programmable:: Not Verified

PLL:: -

Main Purpose:: -

Input:: -

Output:: -

Number of Circuits:: -

Ratio - Input:Output:: -

Differential - Input:Output:: -

Frequency - Max:: -

Voltage - Supply:: -

Operating Temperature:: -

Mounting Type:: Surface Mount

Grade:: -

Qualification:: -

Supplier Device Package:: 24-QFN (4x4)

SI5338M-B05693-GMR FAQ

1.How can I place an order for SI5338M-B05693-GMR through Aetrix?

Please submit a Request for Quotation (RFQ) for SI5338M-B05693-GMR on Aetrix. Our sales agent will provide a competitive quotation and guide you through the order confirmation once you accept the terms.

2.Are the price and stock information for SI5338M-B05693-GMR reliable?

The price and inventory of SI5338M-B05693-GMR are updated periodically and may fluctuate due to market conditions. Stock and pricing data are typically refreshed every 24 hours. Quotation validity for SI5338M-B05693-GMR is usually 5 days.

3.What payment methods are accepted for SI5338M-B05693-GMR?

We accept Wire Transfer, PayPal, Credit Card, Western Union, MoneyGram, and Escrow for SI5338M-B05693-GMR transactions.

Note: Certain payment methods may incur a processing fee.

4.How is shipping managed for SI5338M-B05693-GMR?

SI5338M-B05693-GMR orders can be shipped via leading logistics carriers, including DHL, UPS, FedEx, TNT, or Registered Mail.

Once your SI5338M-B05693-GMR order is processed, you will receive an email with the shipment details and tracking number.

Note: Tracking information may take up to 24 hours to appear. Express delivery typically takes 3–5 business days.

5.How can I obtain technical support or documentation for SI5338M-B05693-GMR?

For technical support, including SI5338M-B05693-GMR datasheets, pinout diagrams, or application guidance, please contact our engineering support team. They can provide detailed documentation and assistance for your SI5338M-B05693-GMR requirements.

6.How does Aetrix verify that SI5338M-B05693-GMR is sourced from the original manufacturer or authorized distributors?

All SI5338M-B05693-GMR products on Aetrix are procured from qualified distributors and authorized channels. Our dedicated quality assurance team conducts strict verification, including traceability checks and, if necessary, third-party testing. This ensures that SI5338M-B05693-GMR meets industry standards.

7.What is the process for return or replacement of SI5338M-B05693-GMR?

All SI5338M-B05693-GMR units undergo pre-shipment inspection (PSI). If there is an issue with SI5338M-B05693-GMR, returns or replacements are accepted under the following conditions:

1.Quantity discrepancies, incorrect items, or visible external defects (such as breakage or corrosion), acknowledged by Aetrix.

2.The issue is reported within 90 days of delivery.

3.The SI5338M-B05693-GMR part is unused and in its original packaging.

Return procedure for SI5338M-B05693-GMR:

1.Submit a request within 90 days.

2.Obtain a Return Material Authorization (RMA) from Aetrix.

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