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Home > Products > Integrated Circuits (ICs) > Clock/Timing > Application Specific Clock/Timing

Skyworks Solutions Inc. SI5338M-B05694-GM

Name: SI5338M-B05694-GM
Brand: Skyworks Solutions Inc.
SKU: SI5338M-B05694-GM
Price: 2.40 USD
Availability: InStock
Rating: 5 (2 reviews)

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Part No.:: SI5338M-B05694-GM

Manufacturer:: Skyworks Solutions Inc.

Category:: Application Specific Clock/Timing

Package:: 24-VFQFN Exposed Pad

Datasheet:: SI5338M-B05694-GM.pdf

Description:: I2C CONTROL, 4-OUTPUT, ANY FREQU

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Product details

Overview

SI5338M-B05694-GM from Skyworks Solutions is a quad-output, I²C-programmable clock generator implementing MultiSynth™ frequency synthesis with 0 ppm precision per output, 0.7 ps RMS typical phase jitter, PCIe Gen 1–4 Common Clock and Gen 3 SRNS compliance, and support for LVPECL/LVDS/HCSL/CMOS/SSTL/HSTL outputs up to 710 MHz. It replaces multiple crystal oscillators in FPGA, processor, and high-speed serial interface timing systems.

For engineers reviewing the SI5338M-B05694-GM datasheet, SI5338M-B05694-GM pinout, SI5338M-B05694-GM application, or SI5338M-B05694-GM equivalent, key selection criteria include differential output jitter performance at PCIe Gen 4, independent per-output voltage (1.5/1.8/2.5/3.3 V), programmable phase/frequency step resolution (<20 ps / 1 ppm), and 4×4 mm 24-QFN package compatibility with space-constrained board layouts.

Technical Context

The SI5338M-B05694-GM integrates a dual-stage PLL architecture: a high-stability reference stage (input range 5–710 MHz) feeding a fractional-N MultiSynth™ VCO (Fvco = 3.2–4.0 GHz), followed by four independent synthesis paths each with configurable R/M/N dividers and output drivers. Each output supports integer or fractional mode operation, enabling true zero-ppm accuracy across all four clocks.

It features dedicated loss-of-signal (2.6–5 µs detection) and loss-of-lock (5–10 ms) alarms, external feedback capability for zero-delay mode, and independent spread-spectrum control (0.5–5.0% spread, 33–63 kHz modulation) on any output - all managed via I²C/SMBus interface with ClockBuilder Pro configuration software.

Key Specifications

Parameter	Value and Actual Design Meaning
Output count & type	Four differential clock outputs (CLK0A/B through CLK3A/B), configurable as LVPECL/LVDS/HCSL/CML/SSTL/HSTL/CMOS
Frequency range	0.16–710 MHz per output; supports two >350 MHz frequencies simultaneously (Fvco/4 and Fvco/6)
Phase jitter (RMS)	0.7 ps typical (12 kHz–20 MHz), compliant with PCIe Gen 4 Common Clock and OC-12 requirements
Supply voltages	Core: 1.8/2.5/3.3 V ±10%; Output buffers: independently configurable 1.5/1.8/2.5/3.3 V
Input reference	External crystal (8–30 MHz), CMOS (5–200 MHz), SSTL/HSTL (5–350 MHz), or differential (5–710 MHz)
Package	24-pin QFN, 4 × 4 mm, 0.5 mm pitch, exposed thermal pad
Operating temp	–40 °C to +85 °C ambient, suitable for industrial and telecom line card environments

Pinout & Package

SI5338M-B05694-GM uses a 24-lead QFN package (4 × 4 mm, 0.5 mm pitch) with exposed thermal pad. Pin assignments are fixed per the Si5338 family and validated for this variant.

Pin/Terminal	Circuit Role	Design Meaning
IN1, IN2, IN5, IN6	Differential input pairs	Accept AC-coupled differential clocks (5–710 MHz); require external 100 Ω termination
IN3, IN4	Single-ended inputs	Support CMOS/SSTL/HSTL (5–350 MHz); VIH/VIL referenced to VDD
CLK0A–CLK3B	Differential output pairs	Four independent outputs; each pair supports LVPECL/LVDS/HCSL/CML with per-driver VDDO
VDDO0–VDDO3	Output buffer supplies	Independent 1.5/1.8/2.5/3.3 V rails per output bank; enable mixed-voltage system interfacing
VDD	Core supply	Single 1.8/2.5/3.3 V rail powers PLL, logic, and memory; PSRR optimized for noise immunity
SCL, SDA	I²C interface	SMBus-compatible 100/400 kHz bus; supports in-system programming and runtime reconfiguration
INTR	Interrupt output	Open-drain status signal indicating loss-of-lock or loss-of-signal events

Key Features

Feature	Design Value
MultiSynth™ synthesis	Enables independent, any-frequency generation on all four outputs with true zero-ppm accuracy and <1 ppb resolution
Per-output voltage control	Each of four output banks powered by separate VDDO pins (1.5/1.8/2.5/3.3 V), eliminating level-shifter components
Glitchless frequency tuning	Pin-controlled or I²C-based frequency increment/decrement in 1 ppm steps without output interruption
Programmable phase offset	±45 ns initial phase adjustment per output with <20 ps step resolution for skew compensation in parallel buses
Spread spectrum control	Configurable SSC on any output: 0.5–5.0% down-spread, 33–63 kHz modulation rate, reducing EMI in dense PCB layouts

Applications

PCIe Gen 4 Switch Timing	Ethernet Switch Clocking
Use Scenario: Providing synchronized 100 MHz reference clocks to multiple PCIe Gen 4 switch ICs in a 1U server backplane. IC Role / Device Role / Timing Role: Quad-output clock generator delivering four low-jitter, phase-aligned clocks meeting PCIe Gen 4 Common Clock jitter spec (≤0.45 ps RMS). Use Value: Eliminates four discrete oscillators and associated layout complexity while maintaining sub-0.5 ps RMS jitter across all lanes.	Use Scenario: Generating 125 MHz, 156.25 MHz, and 312.5 MHz clocks for 1 GbE/10 GbE PHYs and packet processors in a carrier-grade Ethernet switch. IC Role / Device Role / Timing Role: Any-frequency synthesizer producing precise Ethernet-compliant frequencies from a single 25 MHz crystal reference. Use Value: Reduces BOM count and enables dynamic reconfiguration for multi-rate port provisioning without hardware change.
FPGA Processor Clocking	Broadcast Video Timing
Use Scenario: Supplying 300 MHz system clock, 200 MHz DDR4 interface clock, 100 MHz PCIe root complex clock, and 50 MHz debug clock to a Xilinx Versal ACAP. IC Role / Device Role / Timing Role: Configurable quad clock source supporting mixed-signal domain partitioning with independent voltage and format per output. Use Value: Enables single-chip timing for heterogeneous SoC subsystems, avoiding inter-clock domain skew and power domain conflicts.	Use Scenario: Delivering SMPTE ST 2059-2–compliant 27 MHz, 74.25 MHz, and 148.5 MHz video reference clocks to SDI transceivers and frame synchronizers in broadcast infrastructure. IC Role / Device Role / Timing Role: Low-phase-jitter generator meeting broadcast-grade wander and jitter specifications (≤1 ps RMS) across multiple video standards. Use Value: Ensures frame-accurate synchronization across distributed video processing nodes without external jitter cleaners.

PCIe Gen 4 Switch Timing

Ethernet Switch Clocking

Use Scenario: Providing synchronized 100 MHz reference clocks to multiple PCIe Gen 4 switch ICs in a 1U server backplane.

IC Role / Device Role / Timing Role: Quad-output clock generator delivering four low-jitter, phase-aligned clocks meeting PCIe Gen 4 Common Clock jitter spec (≤0.45 ps RMS).

Use Value: Eliminates four discrete oscillators and associated layout complexity while maintaining sub-0.5 ps RMS jitter across all lanes.

Use Scenario: Generating 125 MHz, 156.25 MHz, and 312.5 MHz clocks for 1 GbE/10 GbE PHYs and packet processors in a carrier-grade Ethernet switch.

IC Role / Device Role / Timing Role: Any-frequency synthesizer producing precise Ethernet-compliant frequencies from a single 25 MHz crystal reference.

Use Value: Reduces BOM count and enables dynamic reconfiguration for multi-rate port provisioning without hardware change.

FPGA Processor Clocking

Broadcast Video Timing

Use Scenario: Supplying 300 MHz system clock, 200 MHz DDR4 interface clock, 100 MHz PCIe root complex clock, and 50 MHz debug clock to a Xilinx Versal ACAP.

IC Role / Device Role / Timing Role: Configurable quad clock source supporting mixed-signal domain partitioning with independent voltage and format per output.

Use Value: Enables single-chip timing for heterogeneous SoC subsystems, avoiding inter-clock domain skew and power domain conflicts.

Use Scenario: Delivering SMPTE ST 2059-2–compliant 27 MHz, 74.25 MHz, and 148.5 MHz video reference clocks to SDI transceivers and frame synchronizers in broadcast infrastructure.

IC Role / Device Role / Timing Role: Low-phase-jitter generator meeting broadcast-grade wander and jitter specifications (≤1 ps RMS) across multiple video standards.

Use Value: Ensures frame-accurate synchronization across distributed video processing nodes without external jitter cleaners.

Equivalent & Alternatives

The following parts are listed as comparable options for similar quad-output programmable clock generator applications.

Alternative Part	Technical Difference	Application Difference	Selection Advice
Si5332A-D05694-GM	Higher integration: includes integrated crystal, lower jitter (0.35 ps RMS), but limited to three outputs and no HCSL support	Preferred for compact designs where crystal integration and ultra-low jitter outweigh need for fourth output or HCSL drive	Select when footprint and jitter are prioritized over output count and HCSL compatibility
ICS853S02IAGLF	Fixed-frequency, non-programmable quad LVDS clock fanout buffer; no synthesis, no I²C, higher jitter (1.2 ps RMS)	Suitable only for static clock distribution, not frequency translation or flexible timing architectures	Choose only for cost-sensitive, fixed-frequency applications with no requirement for programmability or low jitter

Compared with Si5332A-D05694-GM and ICS853S02IAGLF, the SI5338M-B05694-GM uniquely balances full I²C programmability, four independent outputs with HCSL support, and PCIe Gen 4–compliant jitter in a standard 24-QFN package - making it optimal for reconfigurable, multi-standard timing in FPGA and switch platforms.

Availability

SI5338M-B05694-GM is available at Aetrix Electronics and suitable for PCIe Gen 4 switch timing, Ethernet switch clocking, and FPGA processor clocking requiring stable component supply, long-term lifecycle assurance, and traceable sourcing.

Supply support for SI5338M-B05694-GM includes scheduled delivery planning, volume procurement assistance, BOM continuity management, traceable sourcing, and lifecycle availability coordination for OEM customers, industrial embedded developers, connected-device designers, and electronics production programs.

Manufacturer

Skyworks Solutions is a global semiconductor company specializing in analog and mixed-signal connectivity solutions for wireless, broadband, automotive, and industrial markets.

The Si5338 product line delivers highly configurable, low-jitter clock generation for high-speed serial interfaces including PCIe, Ethernet, Fibre Channel, and broadcast video - designed to replace multiple discrete oscillators with a single programmable device.

FAQ

What is the maximum output frequency supported by SI5338M-B05694-GM in LVPECL format?

The SI5338M-B05694-GM supports LVPECL outputs up to 710 MHz. This is confirmed in Table 6 of the datasheet under "Output Clocks (Differential)" for LVPECL, LVDS, and CML formats. Operation above 350 MHz requires using Fvco/4 or Fvco/6 synthesis paths, with only two unique frequencies >350 MHz allowed simultaneously.

Does SI5338M-B05694-GM support PCIe Gen 4 Common Clock compliance?

Yes, the SI5338M-B05694-GM meets PCIe Gen 4 Common Clock jitter requirements with ≤0.45 ps RMS (12 kHz–20 MHz), as specified in Table 12 of the datasheet. It also satisfies Gen 3 SRNS and Gen 1/2/3 Common Clock specs, verified using the Skyworks PCIe Clock Jitter Tool and Intel Clock Jitter Tool v1.6.4.

Can SI5338M-B05694-GM generate different output voltages on each channel?

Yes, SI5338M-B05694-GM provides independent VDDO0–VDDO3 pins, allowing each of its four output banks to be powered at 1.5 V, 1.8 V, 2.5 V, or 3.3 V. This enables direct interfacing with mixed-voltage devices (e.g., 1.8 V FPGA I/O and 3.3 V legacy peripherals) without external level shifters.

What is the phase adjustment resolution and range for SI5338M-B05694-GM outputs?

The SI5338M-B05694-GM offers programmable initial phase offset from –45 ns to +45 ns per output, with <20 ps step resolution. Phase increment/decrement updates occur in ≤667 ns (for outputs >18 MHz) via pin control or I²C, enabling precise skew alignment in parallel data paths.

Is an external crystal required for SI5338M-B05694-GM operation?

No - SI5338M-B05694-GM accepts multiple reference sources: external 8–30 MHz crystal, single-ended CMOS (5–200 MHz), SSTL/HSTL (5–350 MHz), or differential clock (5–710 MHz). Crystal is optional; the device operates fully with any supported external clock input.

SI5338M-B05694-GM Specifications

Product attributes: Attribute value

Manufacturer:: Skyworks Solutions Inc.

Series:: MultiSynth™

Package/Case:: 24-VFQFN Exposed Pad

Packaging:: Tray

Product Status:: Active

Programmable:: Not Verified

PLL:: -

Main Purpose:: -

Input:: -

Output:: -

Number of Circuits:: -

Ratio - Input:Output:: -

Differential - Input:Output:: -

Frequency - Max:: -

Voltage - Supply:: -

Operating Temperature:: -

Mounting Type:: Surface Mount

Grade:: -

Qualification:: -

Supplier Device Package:: 24-QFN (4x4)

SI5338M-B05694-GM FAQ

1.How can I place an order for SI5338M-B05694-GM through Aetrix?

Please submit a Request for Quotation (RFQ) for SI5338M-B05694-GM on Aetrix. Our sales agent will provide a competitive quotation and guide you through the order confirmation once you accept the terms.

2.Are the price and stock information for SI5338M-B05694-GM reliable?

The price and inventory of SI5338M-B05694-GM are updated periodically and may fluctuate due to market conditions. Stock and pricing data are typically refreshed every 24 hours. Quotation validity for SI5338M-B05694-GM is usually 5 days.

3.What payment methods are accepted for SI5338M-B05694-GM?

We accept Wire Transfer, PayPal, Credit Card, Western Union, MoneyGram, and Escrow for SI5338M-B05694-GM transactions.

Note: Certain payment methods may incur a processing fee.

4.How is shipping managed for SI5338M-B05694-GM?

SI5338M-B05694-GM orders can be shipped via leading logistics carriers, including DHL, UPS, FedEx, TNT, or Registered Mail.

Once your SI5338M-B05694-GM order is processed, you will receive an email with the shipment details and tracking number.

Note: Tracking information may take up to 24 hours to appear. Express delivery typically takes 3–5 business days.

5.How can I obtain technical support or documentation for SI5338M-B05694-GM?

For technical support, including SI5338M-B05694-GM datasheets, pinout diagrams, or application guidance, please contact our engineering support team. They can provide detailed documentation and assistance for your SI5338M-B05694-GM requirements.

6.How does Aetrix verify that SI5338M-B05694-GM is sourced from the original manufacturer or authorized distributors?

All SI5338M-B05694-GM products on Aetrix are procured from qualified distributors and authorized channels. Our dedicated quality assurance team conducts strict verification, including traceability checks and, if necessary, third-party testing. This ensures that SI5338M-B05694-GM meets industry standards.

7.What is the process for return or replacement of SI5338M-B05694-GM?

All SI5338M-B05694-GM units undergo pre-shipment inspection (PSI). If there is an issue with SI5338M-B05694-GM, returns or replacements are accepted under the following conditions:

1.Quantity discrepancies, incorrect items, or visible external defects (such as breakage or corrosion), acknowledged by Aetrix.

2.The issue is reported within 90 days of delivery.

3.The SI5338M-B05694-GM part is unused and in its original packaging.

Return procedure for SI5338M-B05694-GM:

1.Submit a request within 90 days.

2.Obtain a Return Material Authorization (RMA) from Aetrix.

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