Skyworks Solutions Inc. SI5338M-B05695-GM

Overview

SI5338M-B05695-GM from Skyworks Solutions is an I²C-programmable quad clock generator with four independently configurable differential or single-ended outputs, 0.7 ps RMS typical phase jitter, PCIe Gen 1–4 Common Clock and Gen 3 SRNS compliance, and operation across –40 to +85 °C. It replaces up to four crystal oscillators in high-speed serial interface timing applications such as PCIe switch cards and FPGA clock trees.

For engineers reviewing the SI5338M-B05695-GM datasheet, SI5338M-B05695-GM pinout, SI5338M-B05695-GM application, or SI5338M-B05695-GM equivalent, key selection criteria include its MultiSynth™-based any-frequency synthesis (0.16–710 MHz per output), independent output voltage support (1.5/1.8/2.5/3.3 V), spread-spectrum capability (0.5–5.0% down-spread), and 24-QFN package compatibility with space-constrained PCB layouts.

Technical Context

The SI5338M-B05695-GM implements a two-stage PLL architecture: a high-stability input stage with programmable R-divider and a fractional-N MultiSynth™ synthesis stage per output, enabling independent frequency, phase, and format configuration. Its core operates from a single 1.8/2.5/3.3 V supply with 45 mA typical current draw.

Each of the four output drivers supports LVPECL/LVDS/HCSL/CMOS/SSTL/HSTL formats with independent VDDO supplies, programmable initial phase offset (±45 ns), and glitchless frequency increment/decrement in 1 ppm steps. Input flexibility includes external crystal (8–30 MHz), CMOS (5–200 MHz), SSTL/HSTL (5–350 MHz), or differential (5–710 MHz) references.

Key Specifications

Pinout & Package

SI5338M-B05695-GM uses a 24-lead, 4 × 4 mm QFN package with exposed thermal pad. Pin 1 is top-left corner (IN1), pin 24 is bottom-right (GND). The package supports standard JEDEC reflow profiles and requires controlled-impedance routing for differential inputs/outputs.

Key Features

Applications

Equivalent & Alternatives

The following parts are listed as comparable options for similar clock generator applications.

Compared with Si5332A-D05695-GM and ICS8430I-01LG, SI5338M-B05695-GM delivers optimal balance of programmability, PCIe Gen 4 readiness, and 4-output density in a compact 4×4 mm footprint-making it ideal for mid-tier FPGA, switch, and embedded networking platforms where design flexibility and qualification assurance are critical.

Availability

SI5338M-B05695-GM is available at Aetrix Electronics and suitable for PCIe switch timing, Ethernet PHY clocking, FPGA clock tree generation, and broadcast video synchronization requiring stable component supply and long-term lifecycle support.

Supply support for SI5338M-B05695-GM includes scheduled delivery planning, volume procurement assistance, BOM continuity management, traceable sourcing, and lifecycle availability coordination for OEM customers, industrial embedded developers, connected-device designers, and electronics production programs.

Manufacturer

Skyworks Solutions is a global semiconductor company specializing in analog and mixed-signal connectivity solutions for wireless, broadband, automotive, and industrial markets.

The Si5338 product line was designed for high-performance, software-configurable clock generation in data center, telecom, and embedded systems-enabling consolidation of multiple timing sources into a single, field-upgradable IC.

FAQ

What is the primary function of the SI5338M-B05695-GM?

The SI5338M-B05695-GM is an I²C-programmable quad clock generator that synthesizes up to four independent, low-jitter output frequencies from a single input reference. It replaces multiple crystal oscillators in applications requiring flexible, high-precision timing-such as PCIe switches, Ethernet PHYs, and FPGA clock trees-while maintaining 0.7 ps RMS phase jitter and PCIe Gen 4 compliance.

Does the SI5338M-B05695-GM support PCIe Gen 4 timing requirements?

Yes, the SI5338M-B05695-GM meets PCIe Gen 4 Common Clock jitter specifications with 0.15–0.45 ps RMS (10 kHz–50 MHz) when configured per Skyworks' recommended settings. Its MultiSynth™ architecture, low-noise PLL, and optimized output drivers ensure compliance with PCI-SIG Base Specification 4.0, making SI5338M-B05695-GM suitable for Gen 4 root complexes and endpoint timing.

How many output formats does the SI5338M-B05695-GM support per channel?

The SI5338M-B05695-GM supports six output signal formats-LVPECL, LVDS, HCSL, CMOS, SSTL, and HSTL-with independent configuration per output channel. Each output driver accepts its own VDDO supply (1.5/1.8/2.5/3.3 V), allowing SI5338M-B05695-GM to drive mixed-voltage interfaces (e.g., 1.8 V LVDS for FPGA transceivers and 3.3 V CMOS for legacy controllers) simultaneously.

Can the SI5338M-B05695-GM operate in clock buffer (PLL bypass) mode?

Yes, the SI5338M-B05695-GM supports clock buffer mode with additive phase jitter as low as 0.165 ps RMS (12 kHz–20 MHz). In this mode, the device passes the input clock directly to outputs with minimal delay (<4 ns propagation), preserving input jitter characteristics-ideal for applications requiring deterministic latency or ultra-low-additive jitter in fanout distribution.

What programming tools are compatible with the SI5338M-B05695-GM?

Skyworks ClockBuilder Pro is the official GUI-based configuration tool for SI5338M-B05695-GM, enabling full register setup, jitter simulation, and one-click .hex file generation. The SI5338M-B05695-GM communicates via standard I²C/SMBus (100/400 kHz), supporting in-system programming during development and field updates without requiring dedicated hardware programmers.