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Home > Products > Integrated Circuits (ICs) > Clock/Timing > Application Specific Clock/Timing

Skyworks Solutions Inc. SI5338M-B05701-GM

Name: SI5338M-B05701-GM
Brand: Skyworks Solutions Inc.
SKU: SI5338M-B05701-GM
Price: 2.40 USD
Availability: InStock
Rating: 5 (2 reviews)

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Part No.:: SI5338M-B05701-GM

Manufacturer:: Skyworks Solutions Inc.

Category:: Application Specific Clock/Timing

Package:: 24-VFQFN Exposed Pad

Datasheet:: SI5338M-B05701-GM.pdf

Description:: I2C CONTROL, 4-OUTPUT, ANY FREQU

Quantity:: RFQ Add To RFQ list

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Product details

Overview

SI5338M-B05701-GM from Skyworks Solutions is an I²C-programmable quad clock generator IC with four independently configurable differential or single-ended outputs, 0.7 ps RMS typical phase jitter, PCIe Gen 1–4 Common Clock and Gen 3 SRNS compliance, and operation across –40 to +85 °C. It replaces up to four crystal oscillators in high-speed serial interface timing applications such as PCIe root complexes and FPGA-based compute platforms.

For engineers reviewing the SI5338M-B05701-GM datasheet, SI5338M-B05701-GM pinout, SI5338M-B05701-GM application, or SI5338M-B05701-GM equivalent, key selection criteria include its MultiSynth™-based any-frequency synthesis (0.16–710 MHz per output), independent output voltage support (1.5/1.8/2.5/3.3 V), spread-spectrum capability (0.5–5.0% down-spread), and 24-QFN package compatibility with space-constrained PCB layouts.

Technical Context

The SI5338M-B05701-GM implements a two-stage PLL architecture: a high-stability input stage with programmable R-divider and a fractional-N MultiSynth™ synthesis stage per output path. Each of the four output drivers supports independent format selection (LVPECL/LVDS/HCSL/CMOS/SSTL/HSTL) and voltage rail (VDDO0–VDDO3).

It accepts six input sources - dual differential (IN1/IN2, IN5/IN6), dual single-ended (IN3/IN4), and external crystal (8–30 MHz) - with loss-of-signal detection and configurable PLL loop bandwidth (1.6 MHz typical). Output skew is ≤100 ps between integer-related frequencies using identical driver formats.

Key Specifications

Parameter	Value and Actual Design Meaning
Output count & type	4 independent outputs; configurable as differential (LVPECL/LVDS/HCSL/CML) or single-ended (CMOS/SSTL/HSTL)
Frequency range per output	0.16–710 MHz (LVPECL/LVDS); 0.16–250 MHz (HCSL); 0.16–200 MHz (CMOS); 0.16–350 MHz (SSTL/HSTL)
Phase jitter (RMS)	0.7 ps typical (12 kHz–20 MHz); compliant with PCIe Gen 3 SRNS and Gen 4 Common Clock specs
Input reference options	External crystal (8–30 MHz), CMOS (5–200 MHz), SSTL/HSTL (5–350 MHz), differential (5–710 MHz)
Supply & power	Core: 1.8/2.5/3.3 V (±10%); output buffers: 1.4–3.63 V; core current typ. 45 mA at 100 MHz on all outputs
Operating temperature	–40 to +85 °C; qualified for industrial and telecom line card environments
Package	24-pin QFN, 4 × 4 mm, 0.5 mm pitch; RoHS-compliant, lead-free

Pinout & Package

The SI5338M-B05701-GM uses a 24-pin QFN package (4 × 4 mm, 0.5 mm pitch) with exposed thermal pad. Pin assignments are fixed per the Si5338 family and validated for this variant.

Pin/Terminal	Circuit Role	Design Meaning
IN1, IN2	Differential input pair #1	Accepts 5–710 MHz AC-coupled differential clock; internal 100 Ω termination enabled
CLK0A, CLK0B	Differential output pair #0	Configurable LVPECL/LVDS/HCSL/CML; independent VDDO0 supply (1.5–3.3 V)
VDDO0–VDDO3	Output buffer supply rails	Each powers one output pair; enables mixed-voltage clock distribution (e.g., 1.8 V FPGA + 3.3 V PHY)
SCL, SDA	I²C/SMBus interface	Standard 100/400 kHz operation; supports in-system programming without reset
INTR	Interrupt output	Open-drain status flag for loss-of-lock, loss-of-signal, or configuration error
RSVD_GND	Reserved ground terminal	Internal no-connect; must be tied to GND per layout guidelines to maintain thermal and EMI performance

Key Features

Feature	Design Value
MultiSynth™ synthesis	Enables true zero-ppm frequency accuracy on all four outputs simultaneously, eliminating need for multiple crystals
Independent phase adjustment	±45 ns range in <20 ps steps per output - critical for SerDes lane deskew and deterministic latency alignment
Glitchless frequency tuning	1 ppm increment/decrement via PINC/FDEC pins or I²C; no output interruption during dynamic reconfiguration
Spread-spectrum clocking	Programmable 0.5–5.0% down-spread at 33–63 kHz on any output - reduces EMI peak emissions in dense PCBs
PCIe Gen 4 compliance	Meets 0.15–0.45 ps RMS jitter requirement under Common Clock architecture with 2–5 MHz PLL bandwidth
Flexible input handling	Supports crystal, CMOS, SSTL, HSTL, and differential references - simplifies migration from legacy clock trees

Applications

PCIe Gen 4 Root Complex Timing	FPGA-Based Compute Acceleration
Use Scenario: High-bandwidth data center accelerator card requiring synchronized 100 MHz reference clocks for CPU, GPU, and NVMe controllers. IC Role / Device Role / Timing Role: Quad-output clock generator providing PCIe Gen 4 Common Clock (100 MHz) and auxiliary clocks (125 MHz, 156.25 MHz, 312.5 MHz) with sub-0.5 ps RMS jitter. Use Value: Eliminates four discrete oscillators; ensures deterministic inter-lane skew <100 ps and meets Intel CLKJIT-4.0 validation requirements.	Use Scenario: AI inference platform using Xilinx Versal FPGA with multi-gigabit transceivers and DDR4 memory subsystems. IC Role / Device Role / Timing Role: Configurable clock source delivering 156.25 MHz GTY reference, 300 MHz DDR4 clock, 250 MHz logic clock, and 100 MHz system management bus clock. Use Value: Single-chip solution supports mixed-voltage outputs (1.8 V GTY, 1.2 V DDR4, 3.3 V SMBus) and eliminates board-level clock tree complexity.
Ethernet Switch Line Card	Broadcast Video Timing Distribution
Use Scenario: 10G/25G Ethernet switch ASIC requiring low-jitter clocks for SERDES lanes and packet processing engines. IC Role / Device Role / Timing Role: Generates 156.25 MHz (10G), 257.8125 MHz (25G), 250 MHz (switch fabric), and 100 MHz (management) with independent HCSL/LVDS formats. Use Value: Meets IEEE 802.3bj jitter mask for 25G KR; enables per-port clock enable/disable via OEB pin for power-aware port scaling.	Use Scenario: SMPTE ST 2082-1 (12G-SDI) video router distributing genlock, frame sync, and pixel clocks across 32 channels. IC Role / Device Role / Timing Role: Provides 74.25 MHz (HD), 148.5 MHz (3G), 297 MHz (6G), and 594 MHz (12G) outputs with <±10 ps phase offset control per channel. Use Value: Enables precise inter-channel deskew for multi-link video transport; supports SMPTE 2059-2 PTP slave timing via external 1PPS input on IN3.

PCIe Gen 4 Root Complex Timing

FPGA-Based Compute Acceleration

Use Scenario: High-bandwidth data center accelerator card requiring synchronized 100 MHz reference clocks for CPU, GPU, and NVMe controllers.

IC Role / Device Role / Timing Role: Quad-output clock generator providing PCIe Gen 4 Common Clock (100 MHz) and auxiliary clocks (125 MHz, 156.25 MHz, 312.5 MHz) with sub-0.5 ps RMS jitter.

Use Value: Eliminates four discrete oscillators; ensures deterministic inter-lane skew <100 ps and meets Intel CLKJIT-4.0 validation requirements.

Use Scenario: AI inference platform using Xilinx Versal FPGA with multi-gigabit transceivers and DDR4 memory subsystems.

IC Role / Device Role / Timing Role: Configurable clock source delivering 156.25 MHz GTY reference, 300 MHz DDR4 clock, 250 MHz logic clock, and 100 MHz system management bus clock.

Use Value: Single-chip solution supports mixed-voltage outputs (1.8 V GTY, 1.2 V DDR4, 3.3 V SMBus) and eliminates board-level clock tree complexity.

Ethernet Switch Line Card

Broadcast Video Timing Distribution

Use Scenario: 10G/25G Ethernet switch ASIC requiring low-jitter clocks for SERDES lanes and packet processing engines.

IC Role / Device Role / Timing Role: Generates 156.25 MHz (10G), 257.8125 MHz (25G), 250 MHz (switch fabric), and 100 MHz (management) with independent HCSL/LVDS formats.

Use Value: Meets IEEE 802.3bj jitter mask for 25G KR; enables per-port clock enable/disable via OEB pin for power-aware port scaling.

Use Scenario: SMPTE ST 2082-1 (12G-SDI) video router distributing genlock, frame sync, and pixel clocks across 32 channels.

IC Role / Device Role / Timing Role: Provides 74.25 MHz (HD), 148.5 MHz (3G), 297 MHz (6G), and 594 MHz (12G) outputs with <±10 ps phase offset control per channel.

Use Value: Enables precise inter-channel deskew for multi-link video transport; supports SMPTE 2059-2 PTP slave timing via external 1PPS input on IN3.

Equivalent & Alternatives

The following parts are listed as comparable options for similar quad-output programmable clock generator applications.

Alternative Part	Technical Difference	Application Difference	Selection Advice
Si5332A-D05701-GM	Higher integration: 8 outputs, integrated EEPROM, lower jitter (0.35 ps RMS), but larger 32-QFN package	Required for designs needing >4 outputs or factory pre-programming; not drop-in compatible due to pin count and footprint	Select when scalability beyond 4 outputs or zero-configuration startup is required; SI5338M-B05701-GM remains optimal for cost-sensitive 4-output systems.
ICS8430I-01T	Fixed-frequency quad LVDS generator (no I²C programming); 1.2 ps RMS jitter; 3.3 V only; 24-TSSOP package	Suitable only for static clock trees; lacks frequency agility, spread spectrum, or voltage flexibility of SI5338M-B05701-GM	Choose only if design uses unchanging frequencies and prioritizes lowest BOM cost over configurability or jitter margin.

Compared with Si5332A-D05701-GM and ICS8430I-01T, the SI5338M-B05701-GM uniquely balances programmability, jitter performance, and compact 24-QFN packaging - making it the preferred choice for PCIe Gen 4, FPGA, and broadcast video systems requiring field-reconfigurable timing with minimal board area.

Availability

SI5338M-B05701-GM is available at Aetrix Electronics and suitable for PCIe Gen 4 root complexes, FPGA-based compute accelerators, and broadcast video timing distribution requiring stable component supply, long-term lifecycle assurance, and full traceability.

Supply support for SI5338M-B05701-GM includes scheduled delivery planning, volume procurement assistance, BOM continuity management, traceable sourcing, and lifecycle availability coordination for OEM customers, industrial embedded developers, connected-device designers, and electronics production programs.

Manufacturer

Skyworks Solutions is a global leader in analog semiconductors, specializing in RF, timing, and precision analog solutions for infrastructure, automotive, and industrial markets.

The Si5338 product line delivers high-performance, software-programmable clock generation for high-speed serial interfaces - designed specifically to replace multiple discrete oscillators while meeting stringent jitter and reliability requirements in data center, telecom, and broadcast equipment.

FAQ

What is the maximum output frequency supported by SI5338M-B05701-GM in LVPECL mode?

The SI5338M-B05701-GM supports up to 710 MHz in LVPECL mode when configured with appropriate VDDO supply (2.5 V or 3.3 V) and load conditions. This capability enables direct clocking of high-speed SerDes lanes in PCIe Gen 4 and 10G/25G Ethernet applications without external frequency multiplication.

Does SI5338M-B05701-GM support PCIe Gen 4 Separate Reference No Spread (SRNS) mode?

Yes, the SI5338M-B05701-GM is explicitly validated for PCIe Gen 4 SRNS operation with 0.11–0.32 ps RMS jitter (typical) when configured with PLL bandwidth of 2–5 MHz and CDR set to 10 MHz. This meets PCI-SIG specification requirements for endpoint timing compliance.

Can SI5338M-B05701-GM generate different output voltages simultaneously?

Yes - SI5338M-B05701-GM provides four independent VDDO supply pins (VDDO0–VDDO3), each configurable from 1.5 V to 3.3 V. This allows simultaneous LVDS (1.8 V), HCSL (1.8 V), CMOS (3.3 V), and SSTL (2.5 V) outputs on a single device, supporting heterogeneous SoC/FPGA interface requirements.

How is SI5338M-B05701-GM programmed in-system?

The SI5338M-B05701-GM is programmed via its I²C/SMBus-compatible interface (SCL/SDA pins) using Skyworks' ClockBuilder Pro software. Configuration can be performed post-soldering without device removal, enabling field firmware updates and design iteration without hardware changes to the SI5338M-B05701-GM implementation.

What is the thermal resistance (θJA) of SI5338M-B05701-GM in still air?

The SI5338M-B05701-GM has a junction-to-ambient thermal resistance (θJA) of 37 °C/W under still-air conditions. This value assumes proper PCB layout with thermal vias under the exposed pad and adequate copper pour, enabling reliable operation at full load across the –40 to +85 °C industrial temperature range.

SI5338M-B05701-GM Specifications

Product attributes: Attribute value

Manufacturer:: Skyworks Solutions Inc.

Series:: MultiSynth™

Package/Case:: 24-VFQFN Exposed Pad

Packaging:: Tray

Product Status:: Active

Programmable:: Not Verified

PLL:: -

Main Purpose:: -

Input:: -

Output:: -

Number of Circuits:: -

Ratio - Input:Output:: -

Differential - Input:Output:: -

Frequency - Max:: -

Voltage - Supply:: -

Operating Temperature:: -

Mounting Type:: Surface Mount

Grade:: -

Qualification:: -

Supplier Device Package:: 24-QFN (4x4)

SI5338M-B05701-GM FAQ

1.How can I place an order for SI5338M-B05701-GM through Aetrix?

Please submit a Request for Quotation (RFQ) for SI5338M-B05701-GM on Aetrix. Our sales agent will provide a competitive quotation and guide you through the order confirmation once you accept the terms.

2.Are the price and stock information for SI5338M-B05701-GM reliable?

The price and inventory of SI5338M-B05701-GM are updated periodically and may fluctuate due to market conditions. Stock and pricing data are typically refreshed every 24 hours. Quotation validity for SI5338M-B05701-GM is usually 5 days.

3.What payment methods are accepted for SI5338M-B05701-GM?

We accept Wire Transfer, PayPal, Credit Card, Western Union, MoneyGram, and Escrow for SI5338M-B05701-GM transactions.

Note: Certain payment methods may incur a processing fee.

4.How is shipping managed for SI5338M-B05701-GM?

SI5338M-B05701-GM orders can be shipped via leading logistics carriers, including DHL, UPS, FedEx, TNT, or Registered Mail.

Once your SI5338M-B05701-GM order is processed, you will receive an email with the shipment details and tracking number.

Note: Tracking information may take up to 24 hours to appear. Express delivery typically takes 3–5 business days.

5.How can I obtain technical support or documentation for SI5338M-B05701-GM?

For technical support, including SI5338M-B05701-GM datasheets, pinout diagrams, or application guidance, please contact our engineering support team. They can provide detailed documentation and assistance for your SI5338M-B05701-GM requirements.

6.How does Aetrix verify that SI5338M-B05701-GM is sourced from the original manufacturer or authorized distributors?

All SI5338M-B05701-GM products on Aetrix are procured from qualified distributors and authorized channels. Our dedicated quality assurance team conducts strict verification, including traceability checks and, if necessary, third-party testing. This ensures that SI5338M-B05701-GM meets industry standards.

7.What is the process for return or replacement of SI5338M-B05701-GM?

All SI5338M-B05701-GM units undergo pre-shipment inspection (PSI). If there is an issue with SI5338M-B05701-GM, returns or replacements are accepted under the following conditions:

1.Quantity discrepancies, incorrect items, or visible external defects (such as breakage or corrosion), acknowledged by Aetrix.

2.The issue is reported within 90 days of delivery.

3.The SI5338M-B05701-GM part is unused and in its original packaging.

Return procedure for SI5338M-B05701-GM:

1.Submit a request within 90 days.

2.Obtain a Return Material Authorization (RMA) from Aetrix.

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