Skyworks Solutions Inc. SI5338M-B05719-GM
- Part No.:
- SI5338M-B05719-GM
- Manufacturer:
- Skyworks Solutions Inc.
- Category:
- Application Specific Clock/Timing
- Package:
- 24-VFQFN Exposed Pad
- Datasheet:
-
SI5338M-B05719-GM.pdf
- Description:
- I2C CONTROL, 4-OUTPUT, ANY FREQU
- Quantity:
- Payment:

- Shipping:

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Product details
Overview
SI5338M-B05719-GM from Skyworks Solutions is a quad-output, I²C-programmable clock generator with MultiSynth™ frequency synthesis. It delivers four independent, any-frequency outputs (0.16–710 MHz) with 0.7 ps RMS typical phase jitter, PCIe Gen 1–4 Common Clock and Gen 3 SRNS compliance, and support for LVPECL/LVDS/HCSL/CMOS/SSTL/HSTL output formats. It serves as a drop-in replacement for up to four crystal oscillators in high-speed serial interface timing.
For engineers reviewing the SI5338M-B05719-GM datasheet, SI5338M-B05719-GM pinout, SI5338M-B05719-GM application, or SI5338M-B05719-GM equivalent, key selection criteria include its 24-QFN package, 4-output flexibility with per-driver voltage control (1.5–3.3 V), independent phase/frequency adjustment (±45 ns / 1 ppm steps), and PCIe/10GbE/Ethernet switch timing validation.
Technical Context
The SI5338M-B05719-GM implements a two-stage PLL architecture: a high-stability input stage with programmable R-divider followed by four independent MultiSynth™ fractional-N synthesizers (M0–M3), each feeding a configurable output driver. Its synthesis resolution is 1 ppb, enabling true zero-ppm accuracy across all outputs when operating in integer mode.
It supports six input types - differential (5–710 MHz), CMOS (5–200 MHz), SSTL/HSTL (5–350 MHz), and external crystal (8–30 MHz) - with loss-of-signal and loss-of-lock detection. Output drivers are independently configurable for format, voltage, spread spectrum (0.5–5.0% at 33–63 kHz), and enable control via OEB pins.
Key Specifications
| Parameter | Value and Actual Design Meaning |
|---|---|
| Output count & type | 4 differential outputs (CLK0A/B through CLK3A/B); supports up to 8 single-ended or mixed configurations |
| Frequency range | 0.16–710 MHz per output; 2× frequencies >350 MHz limited to Fvco/4 and Fvco/6 simultaneously |
| Phase jitter (RMS) | 0.7 ps typical (12 kHz–20 MHz), validated for PCIe Gen 3 SRNS and GbE applications |
| Supply voltages | Core: 1.8/2.5/3.3 V; Output buffers: independently selectable 1.5/1.8/2.5/3.3 V per driver |
| Input reference | External crystal (8–30 MHz), CMOS (5–200 MHz), SSTL/HSTL (5–350 MHz), or differential (5–710 MHz) |
| Interface & control | I²C/SMBus-compatible serial interface; pin-controlled frequency/phase increment/decrement (667 ns update) |
| Operating temperature | –40 °C to +85 °C ambient, qualified for industrial and telecom line card environments |
Pinout & Package
SI5338M-B05719-GM is housed in a 4 × 4 mm, 24-pin QFN package with exposed thermal pad. Pin assignments follow the standard Si5338 top-view layout: IN1/IN2 (differential ref 1), IN3/IN4 (single-ended ref), IN5/IN6 (differential ref 2), CLK0A–CLK3B (four differential output pairs), VDDO0–VDDO3 (independent output supply pins), VDD (core supply), SCL/SDA/INTR (I²C interface and interrupt), and RSVD_GND (reserved ground).
| Pin/Terminal | Circuit Role | Design Meaning |
|---|---|---|
| CLK0A / CLK0B | Differential output pair 0 | LVPECL/LVDS/HCSL/CML/CMOS-configurable; driven by MultiSynth M0; VDDO0 supplies output buffer |
| CLK1A / CLK1B | Differential output pair 1 | Independent of CLK0; driven by MultiSynth M1; VDDO1 sets output voltage level |
| CLK2A / CLK2B | Differential output pair 2 | Driven by MultiSynth M2; supports HCSL up to 250 MHz or LVDS up to 710 MHz |
| CLK3A / CLK3B | Differential output pair 3 | Driven by MultiSynth M3; enables independent phase offset <20 ps step resolution |
| IN1 / IN2 | Differential reference input 1 | Accepts 5–710 MHz; internal 100 Ω termination; slew rate >0.3 V/ns recommended for low jitter |
| IN3 / IN4 | Single-ended reference inputs | CMOS/SSTL/HSTL compatible; 5–350 MHz range; VIH = 0.7×VDD, VIL = 0.3×VDD |
| VDDO0–VDDO3 | Output buffer supply rails | Each powers one output pair; allows mixed-voltage operation (e.g., 1.8 V LVDS + 3.3 V CMOS) |
| SCL / SDA | I²C serial interface | Standard SMBus-compatible bus; supports ClockBuilder Pro programming and runtime reconfiguration |
| INTR | Interrupt output | Open-drain status indicator for loss-of-lock, loss-of-signal, or PLL unlock events |
Key Features
| Feature | Design Value |
|---|---|
| MultiSynth™ synthesis | Four independent fractional-N synthesizers enabling simultaneous, unrelated output frequencies with 1 ppb resolution |
| PCIe Gen 3 SRNS compliance | 0.11–0.32 ps RMS jitter under Gen 3 Separate Reference No Spread conditions, meeting JEDEC JESD204B timing budgets |
| Per-output voltage control | Each of four output drivers powered by dedicated VDDOx rail (1.5/1.8/2.5/3.3 V), eliminating level-shifting components |
| Glitchless frequency tuning | Pin-controlled frequency increment/decrement in 1 ppm steps without output interruption or phase discontinuity |
| Programmable initial phase offset | ±45 ns range with <20 ps step accuracy per output, enabling deterministic inter-output skew alignment |
| Spread spectrum capability | Configurable on any output: 0.5–5.0% down-spread at 33–63 kHz modulation rate, reducing EMI in dense PCB layouts |
Applications
| Ethernet Switch Timing | PCIe Gen 4 Clocking |
|---|---|
Use Scenario: High-density 10GbE/25GbE switch fabric requiring synchronous clocking across multiple SerDes lanes and management processors. IC Role / Device Role / Timing Role: Primary clock source generating 156.25 MHz (10GbE), 312.5 MHz (25GbE), and 100 MHz (management CPU) from a single 25 MHz crystal reference. Use Value: Eliminates four discrete oscillators; reduces board area by 60% and jitter accumulation across domains via common PLL core. | Use Scenario: Server motherboard with dual x16 PCIe Gen 4 slots, requiring compliant common-clock architecture with tight jitter budget. IC Role / Device Role / Timing Role: Generates 100 MHz PCIe reference clocks with <0.45 ps RMS jitter (Gen 4 spec), plus auxiliary clocks for BMC and platform controller hub. Use Value: Meets PCIe Gen 4 Common Clock jitter mask without external jitter cleaners; supports dynamic frequency scaling via I²C. |
| Broadcast Video Sync | FPGA Processor Clocking |
Use Scenario: 4K/8K video encoder with SMPTE 2082 (12G-SDI) and HDMI 2.1 interfaces needing precise frame-sync and pixel-clock generation. IC Role / Device Role / Timing Role: Produces 74.25 MHz (HD), 148.5 MHz (3G-SDI), 297 MHz (12G-SDI), and 540 MHz (HDMI 2.1 TMDS) from one 27 MHz crystal. Use Value: Enables zero-ppm frequency accuracy across all video standards; eliminates manual oscillator selection and inventory complexity. | Use Scenario: Adaptive compute platform using Xilinx Versal ACAP with multiple clock domains: PL logic, AI engines, DDR4 memory, and PCIe subsystem. IC Role / Device Role / Timing Role: Supplies 300 MHz (PL), 500 MHz (AI Engine), 1200 MHz (DDR4 PHY), and 250 MHz (PCIe) clocks with independent phase alignment. Use Value: Reduces FPGA pin count and external clock tree components; simplifies timing closure via deterministic inter-clock skew control. |
Equivalent & Alternatives
The following parts are listed as comparable options for similar quad-output programmable clock generator applications.
| Alternative Part | Technical Difference | Application Difference | Selection Advice |
|---|---|---|---|
| Si5332A-D05719-GM | Higher integration: includes integrated crystal; lower jitter (0.35 ps RMS); supports up to 10 outputs | Targeted at space-constrained designs where crystal placement is problematic; requires different layout and power sequencing | Select for new designs prioritizing jitter margin and BOM reduction; not pin-compatible with SI5338M-B05719-GM |
| ICS853S012AKLFT | Fixed-function 4-output LVDS clock generator; no I²C programming; max 700 MHz output; 1.2 ps RMS jitter | Limited to pre-defined frequency combinations; no spread spectrum or phase adjustment; simpler bring-up but inflexible | Choose for cost-sensitive, high-volume applications with static clock trees and no need for field reconfiguration |
Compared with Si5332A-D05719-GM and ICS853S012AKLFT, SI5338M-B05719-GM offers the broadest frequency flexibility and field-programmability in a mature, widely supported 24-QFN footprint-ideal for prototyping, multi-platform reuse, and systems requiring post-silicon clock tuning.
Availability
SI5338M-B05719-GM is available at Aetrix Electronics and suitable for Ethernet switch/router, PCIe Gen 1–4 add-in cards, broadcast video timing, and FPGA-based processor clocking requiring stable component supply and long-term industrial availability.
Supply support for SI5338M-B05719-GM includes scheduled delivery planning, volume procurement assistance, BOM continuity management, traceable sourcing, and lifecycle availability coordination for OEM customers, industrial embedded developers, connected-device designers, and electronics production programs.
Manufacturer
Skyworks Solutions is a global leader in analog and mixed-signal semiconductors, specializing in RF, timing, and connectivity solutions for infrastructure, automotive, and mobile markets.
The Si5338 product line was designed specifically for high-performance, multi-protocol clock generation in datacenter, telecom, and broadcast equipment-emphasizing low jitter, flexible output configuration, and seamless integration with high-speed serial interfaces.
FAQ
What is the maximum output frequency supported by SI5338M-B05719-GM in LVPECL format?
The SI5338M-B05719-GM supports LVPECL outputs up to 710 MHz, as confirmed in Table 6 of the datasheet. This applies when using the VCO frequency range (Fvco) and appropriate MultiSynth divider settings. Note that only two unique frequencies above 350 MHz can be generated simultaneously-specifically Fvco/4 and Fvco/6-due to internal synthesis constraints.
Does SI5338M-B05719-GM support PCIe Gen 4 Common Clock compliance?
Yes, SI5338M-B05719-GM meets PCIe Gen 4 Common Clock requirements with 0.15–0.45 ps RMS jitter (10 kHz–50 MHz), verified per PCI Express Base Specification 4.0 rev. 0.5. The device achieves this using a PLL bandwidth of 2–4 MHz and CDR = 10 MHz, and it is explicitly listed in the Features section as PCIe Gen 1/2/3/4 Common Clock compliant.
Can SI5338M-B05719-GM generate four completely independent output frequencies?
Yes, SI5338M-B05719-GM uses four independent MultiSynth™ fractional-N synthesizers (M0–M3), allowing truly unrelated output frequencies from 0.16 MHz to 710 MHz. Each output is programmable via I²C with zero-ppm precision in integer mode, and synthesis resolution is 1 ppb-even in fractional mode-enabling arbitrary frequency combinations without shared dividers.
What input reference options are supported by SI5338M-B05719-GM?
SI5338M-B05719-GM accepts six input reference types: differential (5–710 MHz on IN1/IN2 or IN5/IN6), CMOS (5–200 MHz on IN3/IN4), SSTL/HSTL (5–350 MHz on IN3/IN4), and external crystal (8–30 MHz). All inputs support loss-of-signal detection, and the device includes internal load capacitance tuning for crystals (11–13 pF supported, 17–19 pF recommended).
Is SI5338M-B05719-GM pin-compatible with other Si5338 variants?
Yes, SI5338M-B05719-GM shares the same 24-QFN package and pinout as all standard Si5338 devices (e.g., Si5338A, Si5338B, Si5338C). The "M" suffix denotes a specific factory-programmed configuration (B05719), but mechanical and electrical pin compatibility-including power, I²C, interrupt, and clock I/O-is fully maintained across the Si5338 family.
SI5338M-B05719-GM Specifications
- Product attributes
- Attribute value
- Manufacturer:
- Skyworks Solutions Inc.
- Series:
- MultiSynth™
- Package/Case:
- 24-VFQFN Exposed Pad
- Packaging:
- Tray
- Product Status:
- Active
- Programmable:
- Not Verified
- PLL:
- -
- Main Purpose:
- -
- Input:
- -
- Output:
- -
- Number of Circuits:
- -
- Ratio - Input:Output:
- -
- Differential - Input:Output:
- -
- Frequency - Max:
- -
- Voltage - Supply:
- -
- Operating Temperature:
- -
- Mounting Type:
- Surface Mount
- Grade:
- -
- Qualification:
- -
- Supplier Device Package:
- 24-QFN (4x4)
SI5338M-B05719-GM FAQ
1.How can I place an order for SI5338M-B05719-GM through Aetrix?
Please submit a Request for Quotation (RFQ) for SI5338M-B05719-GM on Aetrix. Our sales agent will provide a competitive quotation and guide you through the order confirmation once you accept the terms.
2.Are the price and stock information for SI5338M-B05719-GM reliable?
The price and inventory of SI5338M-B05719-GM are updated periodically and may fluctuate due to market conditions. Stock and pricing data are typically refreshed every 24 hours. Quotation validity for SI5338M-B05719-GM is usually 5 days.
3.What payment methods are accepted for SI5338M-B05719-GM?
We accept Wire Transfer, PayPal, Credit Card, Western Union, MoneyGram, and Escrow for SI5338M-B05719-GM transactions.
Note: Certain payment methods may incur a processing fee.
4.How is shipping managed for SI5338M-B05719-GM?
SI5338M-B05719-GM orders can be shipped via leading logistics carriers, including DHL, UPS, FedEx, TNT, or Registered Mail.
Once your SI5338M-B05719-GM order is processed, you will receive an email with the shipment details and tracking number.
Note: Tracking information may take up to 24 hours to appear. Express delivery typically takes 3–5 business days.
5.How can I obtain technical support or documentation for SI5338M-B05719-GM?
For technical support, including SI5338M-B05719-GM datasheets, pinout diagrams, or application guidance, please contact our engineering support team. They can provide detailed documentation and assistance for your SI5338M-B05719-GM requirements.
6.How does Aetrix verify that SI5338M-B05719-GM is sourced from the original manufacturer or authorized distributors?
All SI5338M-B05719-GM products on Aetrix are procured from qualified distributors and authorized channels. Our dedicated quality assurance team conducts strict verification, including traceability checks and, if necessary, third-party testing. This ensures that SI5338M-B05719-GM meets industry standards.
7.What is the process for return or replacement of SI5338M-B05719-GM?
All SI5338M-B05719-GM units undergo pre-shipment inspection (PSI). If there is an issue with SI5338M-B05719-GM, returns or replacements are accepted under the following conditions:
1.Quantity discrepancies, incorrect items, or visible external defects (such as breakage or corrosion), acknowledged by Aetrix.
2.The issue is reported within 90 days of delivery.
3.The SI5338M-B05719-GM part is unused and in its original packaging.
Return procedure for SI5338M-B05719-GM:
1.Submit a request within 90 days.
2.Obtain a Return Material Authorization (RMA) from Aetrix.
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