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Home > Products > Integrated Circuits (ICs) > Clock/Timing > Application Specific Clock/Timing

Skyworks Solutions Inc. SI5338M-B05735-GMR

Name: SI5338M-B05735-GMR
Brand: Skyworks Solutions Inc.
SKU: SI5338M-B05735-GMR
Price: 2.40 USD
Availability: InStock
Rating: 5 (2 reviews)

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Part No.:: SI5338M-B05735-GMR

Manufacturer:: Skyworks Solutions Inc.

Category:: Application Specific Clock/Timing

Package:: 24-VFQFN Exposed Pad

Datasheet:: SI5338M-B05735-GMR.pdf

Description:: I2C CONTROL, 4-OUTPUT, ANY FREQU

Quantity:: RFQ Add To RFQ list

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Product details

Overview

SI5338M-B05735-GMR from Skyworks Solutions is an I²C-programmable quad clock generator with four independently configurable differential outputs, 0.7 ps RMS typical phase jitter, PCIe Gen 1–4 Common Clock and Gen 3 SRNS compliance, and support for LVPECL/LVDS/HCSL/CMOS/SSTL/HSTL output formats across 0.16–710 MHz. It replaces up to four crystal oscillators in high-speed serial interface timing applications such as PCIe root complexes and FPGA clock trees.

For engineers reviewing the SI5338M-B05735-GMR datasheet, SI5338M-B05735-GMR pinout, SI5338M-B05735-GMR application, or SI5338M-B05735-GMR equivalent, key selection criteria include its MultiSynth™ fractional-N synthesis architecture, independent per-output voltage (1.5/1.8/2.5/3.3 V), ±20 ps phase step resolution, and 24-QFN package with 4×4 mm footprint.

Technical Context

The SI5338M-B05735-GMR implements a two-stage synthesis architecture: a high-stability PLL (1.6 MHz loop bandwidth) locks to one of six input sources (crystal, CMOS, SSTL/HSTL, or differential), followed by four independent MultiSynth™ fractional-N dividers enabling any-frequency generation on each output. Each output driver supports format- and voltage-selectable termination with programmable slew rate control.

It features loss-of-lock and loss-of-signal detection, independent frequency increment/decrement (1 ppm steps), and phase adjustment (<20 ps steps) via I²C or hardware pins. External feedback mode enables zero-delay operation, while spread spectrum modulation (0.5–5.0% spread, 33–63 kHz rate) is configurable per output.

Key Specifications

Parameter	Value and Actual Design Meaning
Output Count	Four independent differential clock outputs (CLK0A/B through CLK3A/B)
Phase Jitter (RMS)	0.7 ps typical over 12 kHz–20 MHz - meets PCIe Gen 4 common clock jitter requirements
Frequency Range	0.16–710 MHz per output - covers PCIe 100/125 MHz, Ethernet 125/156.25 MHz, and Fibre Channel 212.5/266.7 MHz
Input Flexibility	Supports 8–30 MHz crystal, 5–200 MHz CMOS, 5–350 MHz SSTL/HSTL, or 5–710 MHz differential reference
Supply Voltages	Core: 1.8/2.5/3.3 V; Output buffers: independently configurable 1.5/1.8/2.5/3.3 V per driver
Package	24-pin QFN, 4 × 4 mm, 0.5 mm pitch - compatible with standard reflow profiles and high-density PCB layouts
Operating Temp	–40 °C to +85 °C - qualified for industrial and telecom line card environments

Pinout & Package

SI5338M-B05735-GMR uses a 24-pin QFN package (4 × 4 mm, 0.5 mm pitch) with exposed thermal pad. Pin assignments are fixed per the Si5338 family and validated in Rev. 1.6 datasheet Figure 1 (Top View).

Pin/Terminal	Circuit Role	Design Meaning
IN1/IN2, IN5/IN6	Differential clock inputs	Accept 5–710 MHz AC-coupled differential references; require external 100 Ω termination
IN3/IN4	Single-ended clock inputs	Support 5–200 MHz CMOS-level signals; internal 20 kΩ pull-up/pull-down selectable via register
CLK0A/CLK0B – CLK3A/CLK3B	Differential clock outputs	Four independent pairs; each configurable for LVPECL/LVDS/HCSL/CML/SSTL/HSTL with per-driver VDDO
VDDO0–VDDO3	Output buffer supplies	Independent 1.5/1.8/2.5/3.3 V rails per output pair - enable mixed-voltage system interfacing
SCL/SDA	I²C configuration interface	Standard SMBus-compatible 100/400 kHz operation; supports ClockBuilder Pro programming
INTR	Interrupt output	Open-drain status signal indicating loss-of-lock, loss-of-signal, or PLL unlock events

Key Features

Feature	Design Value
MultiSynth™ synthesis	Four independent fractional-N synthesizers deliver true zero-ppm accuracy on all outputs without external VCXOs
PCIe Gen 4 compliance	0.15–0.45 ps RMS jitter in Common Clock mode satisfies PCIe Base Spec 4.0 rev. 0.5 requirements
Per-output voltage control	Each of four output drivers supports independent 1.5/1.8/2.5/3.3 V supply - eliminates level-shifter ICs in multi-rail systems
Hardware frequency tuning	Pin-controlled frequency increment/decrement (1 ppm steps) enables real-time glitchless adjustments without I²C traffic
Programmable phase offset	±45 ns initial phase shift per output with <20 ps step resolution - critical for skew-sensitive SerDes alignment
Spread spectrum support	Configurable SSC on any output (0.5–5.0% spread, 33–63 kHz rate) reduces EMI peak emissions in dense PCB layouts

Applications

PCIe Root Complex Timing	Ethernet Switch Synchronization
Use Scenario: Providing synchronized 100 MHz reference clocks to multiple PCIe endpoints and switches in a server backplane. IC Role / Device Role / Timing Role: Quad-output clock generator delivering four independent, low-jitter PCIe-compliant clocks with matched propagation delay. Use Value: Eliminates four discrete oscillators while maintaining sub-33.6 ps pk-pk total jitter required for PCIe 2.1 Common Clock compliance.	Use Scenario: Generating 125 MHz and 156.25 MHz clocks for 1 GbE and 10 GbE PHYs in a multi-port switch ASIC. IC Role / Device Role / Timing Role: Any-frequency synthesizer producing exact IEEE 802.3 compliant frequencies from a single 25 MHz crystal. Use Value: Achieves 0.7 ps RMS random jitter at 125 MHz - 2.6× lower than maximum allowed for 10GbE KR jitter budget.
FPGA Clock Tree Management	Broadcast Video Frame Sync
Use Scenario: Supplying multiple clock domains (e.g., 100 MHz AXI, 200 MHz DDR, 300 MHz transceiver) to a Xilinx Versal FPGA. IC Role / Device Role / Timing Role: Programmable quad clock source with independent voltage and format per output to match FPGA bank requirements. Use Value: Reduces BOM count by replacing three separate clock ICs while enabling dynamic frequency scaling via I²C during runtime.	Use Scenario: Generating SMPTE ST 2059-2 compliant 27 MHz, 74.25 MHz, and 148.5 MHz video reference clocks for SDI transmitter/receiver chains. IC Role / Device Role / Timing Role: Low-phase-noise clock generator supporting jitter-sensitive broadcast timing standards. Use Value: Delivers 0.7 ps RMS jitter at 148.5 MHz - meets SMPTE ST 2059-2 Class A requirement (≤1.0 ps RMS).

PCIe Root Complex Timing

Ethernet Switch Synchronization

Use Scenario: Providing synchronized 100 MHz reference clocks to multiple PCIe endpoints and switches in a server backplane.

IC Role / Device Role / Timing Role: Quad-output clock generator delivering four independent, low-jitter PCIe-compliant clocks with matched propagation delay.

Use Value: Eliminates four discrete oscillators while maintaining sub-33.6 ps pk-pk total jitter required for PCIe 2.1 Common Clock compliance.

Use Scenario: Generating 125 MHz and 156.25 MHz clocks for 1 GbE and 10 GbE PHYs in a multi-port switch ASIC.

IC Role / Device Role / Timing Role: Any-frequency synthesizer producing exact IEEE 802.3 compliant frequencies from a single 25 MHz crystal.

Use Value: Achieves 0.7 ps RMS random jitter at 125 MHz - 2.6× lower than maximum allowed for 10GbE KR jitter budget.

FPGA Clock Tree Management

Broadcast Video Frame Sync

Use Scenario: Supplying multiple clock domains (e.g., 100 MHz AXI, 200 MHz DDR, 300 MHz transceiver) to a Xilinx Versal FPGA.

IC Role / Device Role / Timing Role: Programmable quad clock source with independent voltage and format per output to match FPGA bank requirements.

Use Value: Reduces BOM count by replacing three separate clock ICs while enabling dynamic frequency scaling via I²C during runtime.

Use Scenario: Generating SMPTE ST 2059-2 compliant 27 MHz, 74.25 MHz, and 148.5 MHz video reference clocks for SDI transmitter/receiver chains.

IC Role / Device Role / Timing Role: Low-phase-noise clock generator supporting jitter-sensitive broadcast timing standards.

Use Value: Delivers 0.7 ps RMS jitter at 148.5 MHz - meets SMPTE ST 2059-2 Class A requirement (≤1.0 ps RMS).

Equivalent & Alternatives

The following parts are listed as comparable options for similar quad clock generator applications.

Alternative Part	Technical Difference	Application Difference	Selection Advice
Si5332A-D05735-GM	Higher integration: includes integrated crystal, smaller 3×3 mm QFN, but limited to 3 outputs and no HCSL support	Targeted at space-constrained client platforms; lacks PCIe Gen 4 SRNS compliance and dual-differential input capability	Select when board area is critical and only three clocks are needed; not suitable for PCIe Gen 4 or legacy HCSL-based designs
ICS853S01AGI-01LFT	Fixed-function 4-output LVDS clock fanout buffer; no frequency synthesis, no I²C programmability, 1.2 ps RMS jitter	Only supports fanout from single input; cannot translate frequencies or generate arbitrary outputs	Choose only for simple clock distribution where input frequency matches all required outputs and synthesis is unnecessary

Compared with Si5332A-D05735-GM and ICS853S01AGI-01LFT, the SI5338M-B05735-GMR uniquely combines full any-frequency synthesis, PCIe Gen 4 compliance, and four independent differential outputs in a production-proven 24-QFN package - making it the only option for complex, multi-standard timing architectures requiring field-programmable flexibility.

Availability

SI5338M-B05735-GMR is available at Aetrix Electronics and suitable for PCIe Gen 4 server motherboards, 10GbE switch fabric designs, and broadcast video equipment requiring stable component supply, long-term lifecycle assurance, and traceable sourcing.

Supply support for SI5338M-B05735-GMR includes scheduled delivery planning, volume procurement assistance, BOM continuity management, traceable sourcing, and lifecycle availability coordination for OEM customers, industrial embedded developers, connected-device designers, and electronics production programs.

Manufacturer

Skyworks Solutions is a global leader in analog semiconductors, specializing in RF, timing, and precision analog solutions for infrastructure, automotive, and mobile markets.

The Si5338 product line delivers programmable, low-jitter clock generation for high-speed serial interfaces including PCIe, Ethernet, Fibre Channel, and broadcast video - designed to replace multiple fixed-frequency oscillators with a single configurable IC.

FAQ

What is the primary function of the SI5338M-B05735-GMR?

The SI5338M-B05735-GMR is an I²C-programmable quad clock generator that synthesizes four independent, low-jitter output frequencies from a single reference input. It uses Skyworks' MultiSynth™ technology to achieve true zero-ppm accuracy on each output, supporting PCIe Gen 1–4, Ethernet, and broadcast video timing standards. Its role is to replace up to four discrete crystal oscillators in high-performance digital systems.

Does the SI5338M-B05735-GMR support PCIe Gen 4 timing requirements?

Yes, the SI5338M-B05735-GMR meets PCIe Gen 4 Common Clock jitter specifications with 0.15–0.45 ps RMS jitter (10 kHz–50 MHz) when configured per AN562 guidelines. It is explicitly certified for PCIe Gen 4 Common Clock and Gen 3 SRNS modes, and its 1.6 MHz PLL bandwidth and optimized MultiSynth™ architecture ensure compliance under worst-case PVT conditions.

Can the SI5338M-B05735-GMR generate HCSL outputs?

Yes, the SI5338M-B05735-GMR supports HCSL output format on all four differential output pairs (CLK0A/B through CLK3A/B) with frequency coverage from 0.16 to 250 MHz. Each HCSL output is independently configurable with dedicated VDDO supply (1.5/1.8/2.5/3.3 V) and includes internal 22 Ω series termination per leg, matching standard HCSL receiver impedance requirements.

What package type and footprint does the SI5338M-B05735-GMR use?

The SI5338M-B05735-GMR uses a 24-pin QFN package measuring 4 × 4 mm with 0.5 mm pitch and an exposed thermal pad. This footprint is identical across the Si5338 family and documented in Skyworks' Package Outline document (Section 9, Rev. 1.6). It supports standard reflow profiles and provides low-inductance grounding for optimal jitter performance.

How is the SI5338M-B05735-GMR programmed and configured?

The SI5338M-B05735-GMR is programmed via its I²C/SMBus-compatible interface (SCL/SDA pins) using Skyworks' ClockBuilder Pro software, which generates custom configuration files and registers settings. Hardware pin control (PINC/FDEC/OEB) also enables real-time frequency/phase adjustments without host processor intervention. All settings are stored in on-chip OTP memory for power-on initialization.

SI5338M-B05735-GMR Specifications

Product attributes: Attribute value

Manufacturer:: Skyworks Solutions Inc.

Series:: MultiSynth™

Package/Case:: 24-VFQFN Exposed Pad

Packaging:: Tape & Reel (TR)

Product Status:: Active

Programmable:: Not Verified

PLL:: -

Main Purpose:: -

Input:: -

Output:: -

Number of Circuits:: -

Ratio - Input:Output:: -

Differential - Input:Output:: -

Frequency - Max:: -

Voltage - Supply:: -

Operating Temperature:: -

Mounting Type:: Surface Mount

Grade:: -

Qualification:: -

Supplier Device Package:: 24-QFN (4x4)

SI5338M-B05735-GMR FAQ

1.How can I place an order for SI5338M-B05735-GMR through Aetrix?

Please submit a Request for Quotation (RFQ) for SI5338M-B05735-GMR on Aetrix. Our sales agent will provide a competitive quotation and guide you through the order confirmation once you accept the terms.

2.Are the price and stock information for SI5338M-B05735-GMR reliable?

The price and inventory of SI5338M-B05735-GMR are updated periodically and may fluctuate due to market conditions. Stock and pricing data are typically refreshed every 24 hours. Quotation validity for SI5338M-B05735-GMR is usually 5 days.

3.What payment methods are accepted for SI5338M-B05735-GMR?

We accept Wire Transfer, PayPal, Credit Card, Western Union, MoneyGram, and Escrow for SI5338M-B05735-GMR transactions.

Note: Certain payment methods may incur a processing fee.

4.How is shipping managed for SI5338M-B05735-GMR?

SI5338M-B05735-GMR orders can be shipped via leading logistics carriers, including DHL, UPS, FedEx, TNT, or Registered Mail.

Once your SI5338M-B05735-GMR order is processed, you will receive an email with the shipment details and tracking number.

Note: Tracking information may take up to 24 hours to appear. Express delivery typically takes 3–5 business days.

5.How can I obtain technical support or documentation for SI5338M-B05735-GMR?

For technical support, including SI5338M-B05735-GMR datasheets, pinout diagrams, or application guidance, please contact our engineering support team. They can provide detailed documentation and assistance for your SI5338M-B05735-GMR requirements.

6.How does Aetrix verify that SI5338M-B05735-GMR is sourced from the original manufacturer or authorized distributors?

All SI5338M-B05735-GMR products on Aetrix are procured from qualified distributors and authorized channels. Our dedicated quality assurance team conducts strict verification, including traceability checks and, if necessary, third-party testing. This ensures that SI5338M-B05735-GMR meets industry standards.

7.What is the process for return or replacement of SI5338M-B05735-GMR?

All SI5338M-B05735-GMR units undergo pre-shipment inspection (PSI). If there is an issue with SI5338M-B05735-GMR, returns or replacements are accepted under the following conditions:

1.Quantity discrepancies, incorrect items, or visible external defects (such as breakage or corrosion), acknowledged by Aetrix.

2.The issue is reported within 90 days of delivery.

3.The SI5338M-B05735-GMR part is unused and in its original packaging.

Return procedure for SI5338M-B05735-GMR:

1.Submit a request within 90 days.

2.Obtain a Return Material Authorization (RMA) from Aetrix.

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