Skyworks Solutions Inc. SI5338M-B05844-GM

Overview

SI5338M-B05844-GM from Skyworks Solutions is a quad-output, I²C-programmable clock generator with MultiSynth™ frequency synthesis. It delivers four independent, any-frequency differential or single-ended clocks (up to 710 MHz LVPECL/LVDS), 0.7 ps RMS typical phase jitter, PCIe Gen 1–4 and SRNS compliance, and operates from 1.8/2.5/3.3 V core supply in a 4×4 mm 24-QFN package for high-density timing applications.

For engineers reviewing the SI5338M-B05844-GM datasheet, SI5338M-B05844-GM pinout, SI5338M-B05844-GM application, or SI5338M-B05844-GM equivalent, key selection considerations include its four independently configurable output drivers, spread-spectrum capability (0.5–5.0% down-spread), ±20 ps phase step resolution, and support for external crystal (8–30 MHz), CMOS (5–200 MHz), or differential (5–710 MHz) reference inputs.

Technical Context

The SI5338M-B05844-GM implements a two-stage PLL architecture: a high-stability integer-N PLL (Stage 1) locks to the input reference, followed by four independent MultiSynth™ fractional-N synthesizers (Stage 2) generating each output. Each output path includes programmable divider chains (R/M/N/P), independent voltage control (1.5–3.3 V), and selectable signal formats (LVPECL/LVDS/HCSL/CMOS/SSTL/HSTL).

It supports both free-running synthesis and zero-delay buffer mode via external feedback. Critical real-time features include loss-of-lock and loss-of-signal alarms, glitchless frequency increment/decrement in 1 ppm steps, and programmable initial phase offset (±45 ns) with <20 ps step accuracy-enabling precise inter-clock alignment in multi-FPGA or multi-ASIC systems.

Key Specifications

Pinout & Package

SI5338M-B05844-GM is housed in a 24-lead, 4 × 4 mm QFN package with wettable flank leads and an exposed thermal pad (pin 24). The package supports reflow soldering per JEDEC J-STD-020 (peak 260 °C) and provides low thermal resistance (θ_JA = 37 °C/W).

Key Features

Applications

Equivalent & Alternatives

The following parts are listed as comparable options for similar quad-output clock generator applications.

Compared with Si5332A-D06899-GM, SI5338M-B05844-GM offers lower cost, smaller footprint, and simpler configuration for PCIe Gen 4 and 10G Ethernet, while ICS85411AGI-01LF serves only static distribution-making SI5338M-B05844-GM the optimal balance of flexibility, performance, and integration for mid-tier timing systems.

Availability

SI5338M-B05844-GM is available at Aetrix Electronics and suitable for PCIe Gen 4 server backplanes, 10/25 GbE switch timing, broadcast video synchronization, and FPGA-based test equipment requiring stable component supply, long-term lifecycle support, and guaranteed traceable sourcing.

Supply support for SI5338M-B05844-GM includes scheduled delivery planning, volume procurement assistance, BOM continuity management, traceable sourcing, and lifecycle availability coordination for OEM customers, industrial embedded developers, connected-device designers, and electronics production programs.

Manufacturer

Skyworks Solutions is a global leader in analog and mixed-signal semiconductors, specializing in RF, mobile, infrastructure, and timing solutions with over 30 years of RF and clocking expertise.

The Si5338 product line was designed specifically for high-performance, multi-protocol timing in datacenter, networking, and broadcast systems-delivering programmable any-frequency synthesis with enterprise-grade jitter performance and robust configurability.

FAQ

What is the maximum differential input frequency supported by the SI5338M-B05844-GM?

The SI5338M-B05844-GM supports differential input frequencies up to 710 MHz on pins IN1/IN2 and IN5/IN6. This capability enables direct use of high-speed SerDes reference clocks (e.g., 622.08 MHz OC-12, 709.5 MHz 100G CAUI) without prescaling. Input slew rate must exceed 0.3 V/ns for optimal jitter performance, and external 100 Ω termination is required per differential pair.

Does the SI5338M-B05844-GM support PCIe Gen 4 Common Clock compliance?

Yes, the SI5338M-B05844-GM meets PCIe Gen 4 Common Clock jitter requirements with 0.15–0.45 ps RMS (1.5 MHz–50 MHz band) when configured per Skyworks AN562 guidelines. Validation uses the Skyworks PCIe Clock Jitter Tool and Intel Clock Jitter Tool v1.6.4, measuring all outputs at 100 MHz HCSL format with PLL bandwidth set to 2–4 MHz and CDR at 10 MHz.

Can the SI5338M-B05844-GM generate four different output frequencies simultaneously?

Yes, the SI5338M-B05844-GM synthesizes four independent frequencies simultaneously using its four MultiSynth™ engines. Each output (CLK0–CLK3) can be set to any frequency within its supported range (e.g., 100 MHz, 125 MHz, 156.25 MHz, 312.5 MHz), with integer or fractional-N synthesis, and zero ppm error-enabling full replacement of up to four discrete crystal oscillators.

What output voltage levels does the SI5338M-B05844-GM support per channel?

The SI5338M-B05844-GM supports independent output buffer supply voltages (VDDO0–VDDO3) from 1.4 V to 3.63 V per channel. This allows mixing LVDS (2.5 V), HCSL (1.8 V), and CMOS (3.3 V) outputs on the same device, enabling direct interface to heterogeneous logic families (e.g., FPGA banks at different I/O voltages) without level-shifting components.

How is the SI5338M-B05844-GM programmed, and is configuration persistent?

The SI5338M-B05844-GM is programmed via I²C/SMBus interface using Skyworks' ClockBuilder Pro software, which generates custom configuration files. Configuration is stored in one-time-programmable (OTP) non-volatile memory, so the device powers up with user-defined settings without host intervention. Factory pre-programmed units like SI5338M-B05844-GM boot in <2 ms with valid clocks.