Skyworks Solutions Inc. SI5338M-B05847-GM
- Part No.:
- SI5338M-B05847-GM
- Manufacturer:
- Skyworks Solutions Inc.
- Category:
- Application Specific Clock/Timing
- Package:
- 24-VFQFN Exposed Pad
- Datasheet:
-
SI5338M-B05847-GM.pdf
- Description:
- I2C CONTROL, 4-OUTPUT, ANY FREQU
- Quantity:
- Payment:

- Shipping:

Inventory:4,430
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Product details
Overview
SI5338M-B05847-GM from Skyworks Solutions is an I²C-programmable quad clock generator with four independently configurable differential outputs, 0.7 ps RMS typical phase jitter, PCIe Gen 1–4 and SRNS compliance, and operation across –40 to +85 °C. It replaces up to four crystal oscillators in Ethernet switch/router, PCIe, and FPGA clocking systems.
For engineers reviewing the SI5338M-B05847-GM datasheet, SI5338M-B05847-GM pinout, SI5338M-B05847-GM application, or SI5338M-B05847-GM equivalent, key selection criteria include its MultiSynth™ any-frequency synthesis (0.16–710 MHz per output), independent output voltage support (1.5/1.8/2.5/3.3 V), spread-spectrum capability (0.5–5.0% down-spread), and 24-QFN package compatibility with high-density PCB layouts.
Technical Context
The SI5338M-B05847-GM implements a two-stage PLL architecture: a high-stability reference stage (with crystal or external clock input) followed by four independent MultiSynth™ fractional-N synthesis blocks. Each output path includes programmable phase offset (<20 ps step resolution), frequency increment/decrement (1 ppm steps), and spread-spectrum modulation (33–63 kHz rate, 0.5–5.0% deviation).
It supports flexible input references-8–30 MHz crystal, 5–200 MHz CMOS, 5–350 MHz SSTL/HSTL, or 5–710 MHz differential-and delivers LVPECL/LVDS/HCSL/CMOS/SSTL/HSTL outputs with independent VDDO per driver. The device operates from a single 1.8/2.5/3.3 V core supply and integrates OTP NVM for factory or field programming via I²C/SMBus.
Key Specifications
| Parameter | Value and Actual Design Meaning |
|---|---|
| Phase Jitter (RMS) | 0.7 ps typ (12 kHz–20 MHz); meets PCIe Gen 3 SRNS & Gen 4 common clock specs |
| Output Frequency Range | 0.16–710 MHz per channel; supports integer/fractional synthesis with 1 ppb resolution |
| Input Reference Support | Crystal (8–30 MHz), CMOS (5–200 MHz), SSTL/HSTL (5–350 MHz), differential (5–710 MHz) |
| Output Formats | LVPECL, LVDS, HCSL, CMOS, SSTL, HSTL - each output independently selectable |
| Supply Voltages | Core: 1.8/2.5/3.3 V ±10%; Output buffers: 1.4–3.63 V per VDDOx rail |
| Operating Temperature | –40 to +85 °C; qualified for industrial and telecom line card environments |
| Package | 24-pin QFN, 4 × 4 mm, 0.5 mm pitch; RoHS-compliant, moisture-sensitive level 3 |
Pinout & Package
SI5338M-B05847-GM uses a 24-lead QFN package (4 × 4 mm, 0.5 mm pitch) with exposed thermal pad. Pin assignments are fixed per the Si5338 family and validated for this variant.
| Pin/Terminal | Circuit Role | Design Meaning |
|---|---|---|
| IN1, IN2, IN5, IN6 | Differential clock inputs | Accept 5–710 MHz AC-coupled differential clocks; require external 100 Ω termination |
| IN3, IN4 | Single-ended clock inputs | Support 5–200 MHz CMOS; VIH = 0.7×VDD, VIL = 0.3×VDD |
| CLK0A/CLK0B to CLK3A/CLK3B | Differential output pairs | Four independent LVPECL/LVDS/HCSL/CML outputs; each with dedicated VDDOx supply |
| VDDO0–VDDO3 | Output buffer supplies | Independent 1.4–3.63 V rails per output pair; enable mixed-voltage system interfacing |
| SCL, SDA | I²C interface | Standard SMBus-compatible serial bus (up to 400 kHz); supports in-system programming |
| INTR | Interrupt output | Open-drain status signal indicating loss-of-lock or loss-of-signal events |
Key Features
| Feature | Design Value |
|---|---|
| MultiSynth™ Any-Frequency Synthesis | Four independent outputs, each programmable from 0.16 to 710 MHz with zero ppm error in integer mode |
| PCIe Gen 1–4 & SRNS Compliance | Validated RMS jitter ≤0.32 ps (Gen 3 SRNS) and ≤0.45 ps (Gen 4 common clock) per PCIe Base Spec 4.0 |
| Independent Phase Adjustment | Programmable initial offset (±45 ns range) and fine-tuning (≤20 ps step resolution) per output |
| Configurable Spread Spectrum | Per-output SSC: 5–350 MHz frequency range, 0.5–5.0% spread, 33–63 kHz modulation rate |
| Low-Power Core Operation | 45 mA typical core current at 100 MHz on all outputs and 25 MHz reference; supports 1.8 V core supply |
Applications
| Ethernet Switch/Router Timing | PCIe Gen 1–4 Clocking |
|---|---|
Use Scenario: High-port-count 1/10 GbE switches requiring low-jitter, multi-frequency clock distribution for SERDES lanes and management processors. IC Role / Device Role / Timing Role: Primary clock generator providing synchronized 125 MHz, 156.25 MHz, and 312.5 MHz outputs with <0.7 ps RMS jitter. Use Value: Enables deterministic packet latency and full compliance with IEEE 802.3an (10GBASE-KR) and IEEE 802.3by (25GBASE-KR) jitter budgets. | Use Scenario: Server motherboard or add-in card needing Gen 3/4 common clock or SRNS reference for CPU, GPU, and NVMe controllers. IC Role / Device Role / Timing Role: PCIe timing hub delivering 100 MHz differential clocks with Gen 4 SRNS-compliant jitter (≤0.32 ps RMS). Use Value: Eliminates need for multiple discrete oscillators while meeting Intel's PCIe CEM 4.0 jitter mask requirements. |
| FPGA & Processor Clocking | Broadcast Video/Audio Timing |
Use Scenario: Heterogeneous SoC/FPGA platforms requiring multiple asynchronous clocks (e.g., 100 MHz AXI, 200 MHz DDR, 400 MHz transceiver refclk). IC Role / Device Role / Timing Role: Configurable quad-output synthesizer generating independent frequencies with programmable phase alignment. Use Value: Reduces BOM count and layout complexity versus discrete oscillator + buffer solutions; enables dynamic frequency scaling via I²C. | Use Scenario: SMPTE ST 2082 (12G-SDI) or AES67 audio-over-IP equipment demanding ultra-low-jitter 27 MHz, 74.25 MHz, and 148.5 MHz references. IC Role / Device Role / Timing Role: Broadcast-grade clock source with sub-1 ps RMS jitter and <100 ps output-to-output skew. Use Value: Ensures frame-accurate synchronization across multi-channel video processing pipelines and avoids lip-sync errors in audio/video systems. |
Equivalent & Alternatives
The following parts are listed as comparable options for similar quad clock generator applications.
| Alternative Part | Technical Difference | Application Difference | Selection Advice |
|---|---|---|---|
| Si5338A-B05847-GM | Same pinout and register map; differs only in factory-programmed configuration (A vs M variant) | Pre-programmed for different default output frequencies and formats; requires reprogramming for identical behavior | Select SI5338M-B05847-GM when factory-configured for specific multi-protocol timing (e.g., PCIe + Ethernet + FPGA) is required out-of-box |
| LMK04832RHAT | Two PLLs, eight outputs, higher power (90 mA typ), supports JESD204B deterministic latency | Targeted at RF/data converter timing; lacks integrated crystal oscillator support and has larger 48-QFN footprint | Choose LMK04832RHAT only when JESD204B subclass 1 synchronization or >4 outputs are mandatory |
Compared with Si5338A-B05847-GM, the SI5338M-B05847-GM offers identical hardware but ships with a distinct factory OTP image optimized for mixed-interface systems; versus LMK04832RHAT, it provides lower power, smaller footprint, and crystal integration at the cost of JESD204B features and output count.
Availability
SI5338M-B05847-GM is available at Aetrix Electronics and suitable for Ethernet switch/router, PCIe Gen 4 add-in cards, and broadcast video timing applications requiring stable component supply, long-term lifecycle support, and traceable sourcing.
Supply support for SI5338M-B05847-GM includes scheduled delivery planning, volume procurement assistance, BOM continuity management, traceable sourcing, and lifecycle availability coordination for OEM customers, industrial embedded developers, connected-device designers, and electronics production programs.
Manufacturer
Skyworks Solutions is a global semiconductor company specializing in analog and mixed-signal connectivity solutions for infrastructure, automotive, and mobile markets.
The Si5338 product line delivers programmable, low-jitter clock generation for high-speed serial interfaces-including PCIe, Ethernet, and broadcast video-enabling flexible, space-efficient timing architectures in density-constrained systems.
FAQ
What is the primary function of the SI5338M-B05847-GM in a system design?
The SI5338M-B05847-GM serves as a fully programmable quad-output clock generator that synthesizes up to four independent, low-jitter frequencies from a single reference. Its MultiSynth™ architecture enables precise, zero-ppm frequency accuracy across diverse output formats (LVDS, LVPECL, HCSL, etc.), making it ideal for replacing multiple discrete oscillators in PCIe, Ethernet, and FPGA-based systems. SI5338M-B05847-GM eliminates timing bottlenecks while supporting dynamic reconfiguration via I²C.
Does the SI5338M-B05847-GM support PCIe Gen 4 timing requirements?
Yes, the SI5338M-B05847-GM meets PCIe Gen 4 common clock jitter specifications with ≤0.45 ps RMS (12 kHz–20 MHz) when configured per Skyworks' validated settings. It is explicitly listed in the datasheet as PCIe Gen 1/2/3/4 Common Clock and Gen 3 SRNS compliant. SI5338M-B05847-GM achieves this using its high-performance PLL architecture, low-noise VCO, and optimized loop bandwidth (2–5 MHz), verified with the Skyworks PCIe Clock Jitter Tool.
Can the SI5338M-B05847-GM operate without an external crystal?
Yes, the SI5338M-B05847-GM supports multiple reference sources: external crystal (8–30 MHz), CMOS (5–200 MHz), SSTL/HSTL (5–350 MHz), or differential clock (5–710 MHz). It does not require a crystal; an external clock applied to IN3/IN4 or IN1/IN2 suffices. However, SI5338M-B05847-GM includes on-chip crystal load capacitance (11–13 pF) and drive circuitry, enabling direct crystal connection when preferred for system simplicity or cost reduction.
How many independent output voltage supplies does the SI5338M-B05847-GM support?
The SI5338M-B05847-GM provides four independent output buffer supply rails: VDDO0, VDDO1, VDDO2, and VDDO3. Each can be set between 1.4 V and 3.63 V, allowing simultaneous LVDS (2.5 V), HCSL (1.8 V), and CMOS (3.3 V) outputs on different channels. This eliminates level-shifting components and simplifies interfacing with mixed-voltage FPGAs, ASICs, and SerDes PHYs. SI5338M-B05847-GM maintains full specification compliance across all supported VDDO combinations.
Is ClockBuilder Pro software required to configure the SI5338M-B05847-GM?
No, ClockBuilder Pro is optional but strongly recommended for efficient configuration. SI5338M-B05847-GM supports full I²C/SMBus register-level programming per its documented register map. However, ClockBuilder Pro automates complex tasks-including jitter optimization, spread-spectrum setup, and cross-output skew calibration-and generates production-ready configuration files. Skyworks provides ClockBuilder Pro free of charge at skyworksinc.com/clockbuilder-pro, and SI5338M-B05847-GM factory OTP images are created using this tool.
SI5338M-B05847-GM Specifications
- Product attributes
- Attribute value
- Manufacturer:
- Skyworks Solutions Inc.
- Series:
- MultiSynth™
- Package/Case:
- 24-VFQFN Exposed Pad
- Packaging:
- Tray
- Product Status:
- Active
- Programmable:
- Not Verified
- PLL:
- -
- Main Purpose:
- -
- Input:
- -
- Output:
- -
- Number of Circuits:
- -
- Ratio - Input:Output:
- -
- Differential - Input:Output:
- -
- Frequency - Max:
- -
- Voltage - Supply:
- -
- Operating Temperature:
- -
- Mounting Type:
- Surface Mount
- Grade:
- -
- Qualification:
- -
- Supplier Device Package:
- 24-QFN (4x4)
SI5338M-B05847-GM FAQ
1.How can I place an order for SI5338M-B05847-GM through Aetrix?
Please submit a Request for Quotation (RFQ) for SI5338M-B05847-GM on Aetrix. Our sales agent will provide a competitive quotation and guide you through the order confirmation once you accept the terms.
2.Are the price and stock information for SI5338M-B05847-GM reliable?
The price and inventory of SI5338M-B05847-GM are updated periodically and may fluctuate due to market conditions. Stock and pricing data are typically refreshed every 24 hours. Quotation validity for SI5338M-B05847-GM is usually 5 days.
3.What payment methods are accepted for SI5338M-B05847-GM?
We accept Wire Transfer, PayPal, Credit Card, Western Union, MoneyGram, and Escrow for SI5338M-B05847-GM transactions.
Note: Certain payment methods may incur a processing fee.
4.How is shipping managed for SI5338M-B05847-GM?
SI5338M-B05847-GM orders can be shipped via leading logistics carriers, including DHL, UPS, FedEx, TNT, or Registered Mail.
Once your SI5338M-B05847-GM order is processed, you will receive an email with the shipment details and tracking number.
Note: Tracking information may take up to 24 hours to appear. Express delivery typically takes 3–5 business days.
5.How can I obtain technical support or documentation for SI5338M-B05847-GM?
For technical support, including SI5338M-B05847-GM datasheets, pinout diagrams, or application guidance, please contact our engineering support team. They can provide detailed documentation and assistance for your SI5338M-B05847-GM requirements.
6.How does Aetrix verify that SI5338M-B05847-GM is sourced from the original manufacturer or authorized distributors?
All SI5338M-B05847-GM products on Aetrix are procured from qualified distributors and authorized channels. Our dedicated quality assurance team conducts strict verification, including traceability checks and, if necessary, third-party testing. This ensures that SI5338M-B05847-GM meets industry standards.
7.What is the process for return or replacement of SI5338M-B05847-GM?
All SI5338M-B05847-GM units undergo pre-shipment inspection (PSI). If there is an issue with SI5338M-B05847-GM, returns or replacements are accepted under the following conditions:
1.Quantity discrepancies, incorrect items, or visible external defects (such as breakage or corrosion), acknowledged by Aetrix.
2.The issue is reported within 90 days of delivery.
3.The SI5338M-B05847-GM part is unused and in its original packaging.
Return procedure for SI5338M-B05847-GM:
1.Submit a request within 90 days.
2.Obtain a Return Material Authorization (RMA) from Aetrix.
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