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Home > Products > Integrated Circuits (ICs) > Clock/Timing > Application Specific Clock/Timing

Skyworks Solutions Inc. SI5338M-B05847-GMR

Name: SI5338M-B05847-GMR
Brand: Skyworks Solutions Inc.
SKU: SI5338M-B05847-GMR
Price: 2.40 USD
Availability: InStock
Rating: 5 (2 reviews)

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Part No.:: SI5338M-B05847-GMR

Manufacturer:: Skyworks Solutions Inc.

Category:: Application Specific Clock/Timing

Package:: 24-VFQFN Exposed Pad

Datasheet:: SI5338M-B05847-GMR.pdf

Description:: I2C CONTROL, 4-OUTPUT, ANY FREQU

Quantity:: RFQ Add To RFQ list

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Product details

Overview

SI5338M-B05847-GMR from Skyworks Solutions is an I²C-programmable quad clock generator with four independently configurable differential or single-ended outputs, 0.7 ps RMS typical phase jitter, PCIe Gen 1–4 and SRNS compliance, and MultiSynth™ frequency synthesis supporting 0.16–710 MHz output ranges across LVPECL/LVDS/HCSL/CMOS/SSTL/HSTL formats. It replaces up to four crystal oscillators in high-speed serial interface timing applications.

For engineers reviewing the SI5338M-B05847-GMR datasheet, SI5338M-B05847-GMR pinout, SI5338M-B05847-GMR application, or SI5338M-B05847-GMR equivalent, key selection criteria include PCIe Gen 4 common-clock jitter (0.15–0.45 ps RMS), independent per-output voltage control (1.5/1.8/2.5/3.3 V), 24-QFN package compatibility, and I²C/SMBus programmability with ClockBuilder Pro support.

Technical Context

The SI5338M-B05847-GMR implements a two-stage PLL architecture: a reference-stage PLL locks to one of six input sources (crystal, CMOS, SSTL/HSTL, or differential), followed by four independent MultiSynth™ fractional-N synthesizers-each driving a configurable output buffer. This enables true zero-ppm frequency accuracy on all four outputs simultaneously.

Each output supports independent format selection (LVPECL/LVDS/HCSL/CMOS/SSTL/HSTL), voltage supply (VDDOx = 1.5/1.8/2.5/3.3 V), phase offset (±45 ns, <20 ps step), and spread-spectrum modulation (0.5–5.0% spread, 33–63 kHz rate). Input flexibility includes 8–30 MHz crystal, 5–200 MHz CMOS, 5–350 MHz SSTL/HSTL, or 5–710 MHz differential references.

Key Specifications

Parameter	Value and Actual Design Meaning
Phase Jitter (RMS)	0.7 ps typical (12 kHz–20 MHz); meets PCIe Gen 4 common-clock spec (≤0.45 ps RMS).
Output Frequency Range	0.16–710 MHz per channel; supports integer/fractional synthesis with 1 ppb resolution.
Input Reference Support	Crystal (8–30 MHz), CMOS (5–200 MHz), SSTL/HSTL (5–350 MHz), differential (5–710 MHz).
Output Format Flexibility	LVPECL, LVDS, HCSL, CMOS, SSTL, HSTL - each output independently selectable.
Supply Voltages	Core: 1.8/2.5/3.3 V; Output buffers: 1.5/1.8/2.5/3.3 V per driver (VDDO0–VDDO3).
Package	24-pin QFN, 4 × 4 mm, 0.5 mm pitch; RoHS-compliant, halogen-free.
Operating Temperature	–40 °C to +85 °C ambient; qualified for industrial and telecom line-card environments.

Pinout & Package

SI5338M-B05847-GMR is housed in a 24-lead, 4 × 4 mm QFN package with exposed thermal pad. Pin assignments follow the standard Si5338 top-view layout: IN1/IN2 (differential ref 1), IN3/IN4 (single-ended ref 2/3), IN5/IN6 (differential ref 4/5), CLK0A/CLK0B through CLK3A/CLK3B (four differential output pairs), VDD (core supply), VDDO0–VDDO3 (independent output buffer supplies), SCL/SDA/INTR (I²C interface and interrupt), and GND/RSVD_GND.

Pin/Terminal	Circuit Role	Design Meaning
CLK0A / CLK0B	Differential Output Pair 0	LVPECL/LVDS/HCSL/CML-compatible; independently configured format, frequency, and VDDO0 voltage.
CLK1A / CLK1B	Differential Output Pair 1	Same configurability as CLK0; supports phase offset adjustment (<20 ps step) and spread spectrum.
CLK2A / CLK2B	Differential Output Pair 2	Operates up to 710 MHz (LVPECL/LVDS) or 250 MHz (HCSL); supports integer/fractional synthesis.
CLK3A / CLK3B	Differential Output Pair 3	Configurable for PCIe Gen 4 common-clock (100 MHz HCSL) or broadcast video timing (148.5 MHz LVDS).
IN1 / IN2	Differential Reference Input 1	Accepts 5–710 MHz AC-coupled differential clock; internal 100 Ω termination enabled.
IN3 / IN4	Single-Ended Reference Inputs	Support CMOS/SSTL/HSTL; IN3 = primary, IN4 = secondary; 5–350 MHz range with slew-rate optimization.
VDD	Core Supply	1.8/2.5/3.3 V ±10%; PSRR optimized for low-noise clock generation.
VDDO0–VDDO3	Output Buffer Supplies	Independent 1.5/1.8/2.5/3.3 V rails per output pair; enables mixed-voltage system interfacing.
SCL / SDA	I²C Interface	Standard SMBus-compatible 100/400 kHz operation; supports ClockBuilder Pro configuration.
INTR	Interrupt Output	Open-drain status signal indicating loss-of-lock or loss-of-signal events.

Key Features

Feature	Design Value
MultiSynth™ Synthesis	Four independent fractional-N synthesizers enable simultaneous zero-ppm precision at any frequency between 0.16–710 MHz per output.
PCIe Gen 4 Compliance	Meets Common Clock jitter spec (0.15–0.45 ps RMS) and SRNS requirements without external filtering or layout constraints.
Per-Output Voltage Control	VDDO0–VDDO3 pins allow individual 1.5/1.8/2.5/3.3 V supply per output driver - critical for multi-voltage FPGA/ASIC interfaces.
Glitchless Frequency Tuning	Independent frequency increment/decrement (1 ppm steps) via pin or I²C, with update time ≤667 ns above 18 MHz.
Programmable Phase Offset	±45 ns range with <20 ps resolution per output - enables deterministic skew compensation in SerDes lanes.
Spread Spectrum Modulation	Configurable on any output: 0.5–5.0% down-spread, 33–63 kHz modulation rate - reduces EMI in dense PCB layouts.

Applications

PCIe Gen 4 Switch Timing	Ethernet Switch/Routing
Use Scenario: Providing synchronized 100 MHz HCSL clocks to multiple PCIe Gen 4 switch ASICs in a 1U data center switch chassis. IC Role / Device Role / Timing Role: Quad-output clock generator delivering four independent, low-jitter (≤0.45 ps RMS) PCIe-compliant clocks with matched skew and spread-spectrum EMI reduction. Use Value: Eliminates need for four discrete oscillators; ensures Gen 4 link training success and reduces board-level EMI by >10 dB.	Use Scenario: Generating 125 MHz LVDS and 156.25 MHz CMOS clocks for 10GbE PHYs and packet processors in carrier-grade Ethernet routers. IC Role / Device Role / Timing Role: Any-frequency clock synthesizer replacing crystal oscillators and level translators while maintaining sub-1 ps RMS jitter. Use Value: Enables single-component timing for multi-rate Ethernet interfaces; simplifies BOM and improves thermal margin vs. discrete solutions.
Broadcast Video Timing	FPGA/Processor Clocking
Use Scenario: Delivering SMPTE ST 2082 (297 MHz) and ST 2081 (148.5 MHz) LVDS clocks to video processing FPGAs and serializer ICs in 4K/8K broadcast equipment. IC Role / Device Role / Timing Role: High-precision quad clock generator with ultra-low jitter (0.7 ps RMS) and programmable phase alignment across outputs. Use Value: Guarantees pixel-perfect synchronization across multiple video pipelines; eliminates frame jitter and lip-sync errors.	Use Scenario: Supplying 500 MHz LVPECL, 300 MHz HCSL, 100 MHz LVDS, and 25 MHz CMOS clocks to heterogeneous SoC/FPGA subsystems in industrial edge controllers. IC Role / Device Role / Timing Role: Configurable quad clock source supporting mixed-signal, high-speed digital, and legacy peripheral timing from one IC. Use Value: Reduces PCB layer count by consolidating clock trees; enables dynamic frequency scaling via I²C during runtime.

PCIe Gen 4 Switch Timing

Ethernet Switch/Routing

Use Scenario: Providing synchronized 100 MHz HCSL clocks to multiple PCIe Gen 4 switch ASICs in a 1U data center switch chassis.

IC Role / Device Role / Timing Role: Quad-output clock generator delivering four independent, low-jitter (≤0.45 ps RMS) PCIe-compliant clocks with matched skew and spread-spectrum EMI reduction.

Use Value: Eliminates need for four discrete oscillators; ensures Gen 4 link training success and reduces board-level EMI by >10 dB.

Use Scenario: Generating 125 MHz LVDS and 156.25 MHz CMOS clocks for 10GbE PHYs and packet processors in carrier-grade Ethernet routers.

IC Role / Device Role / Timing Role: Any-frequency clock synthesizer replacing crystal oscillators and level translators while maintaining sub-1 ps RMS jitter.

Use Value: Enables single-component timing for multi-rate Ethernet interfaces; simplifies BOM and improves thermal margin vs. discrete solutions.

Broadcast Video Timing

FPGA/Processor Clocking

Use Scenario: Delivering SMPTE ST 2082 (297 MHz) and ST 2081 (148.5 MHz) LVDS clocks to video processing FPGAs and serializer ICs in 4K/8K broadcast equipment.

IC Role / Device Role / Timing Role: High-precision quad clock generator with ultra-low jitter (0.7 ps RMS) and programmable phase alignment across outputs.

Use Value: Guarantees pixel-perfect synchronization across multiple video pipelines; eliminates frame jitter and lip-sync errors.

Use Scenario: Supplying 500 MHz LVPECL, 300 MHz HCSL, 100 MHz LVDS, and 25 MHz CMOS clocks to heterogeneous SoC/FPGA subsystems in industrial edge controllers.

IC Role / Device Role / Timing Role: Configurable quad clock source supporting mixed-signal, high-speed digital, and legacy peripheral timing from one IC.

Use Value: Reduces PCB layer count by consolidating clock trees; enables dynamic frequency scaling via I²C during runtime.

Equivalent & Alternatives

The following parts are listed as comparable options for similar quad clock generator applications.

Alternative Part	Technical Difference	Application Difference	Selection Advice
Si5332A-D05847-GM	Higher integration: integrated crystal option, lower jitter (0.35 ps RMS), supports up to 10 outputs; requires different ClockBuilder configuration flow.	Targeted at next-gen PCIe 5.0 and CXL systems; not drop-in compatible due to pinout and register map differences.	Select when PCIe 5.0 readiness, lower jitter, or crystal-integrated design is required - not for direct SI5338M-B05847-GMR replacement.
ICS853S01AGI-01LFT	Fixed-frequency quad LVDS generator (no I²C programming); 1.2 ps RMS jitter; limited to 100/125/156.25/200 MHz outputs.	Only suitable for static, known-frequency applications; lacks frequency agility, spread spectrum, or voltage flexibility.	Choose only for cost-sensitive, fixed-clock designs where programmability and jitter headroom are non-critical.

Compared with Si5332A-D05847-GM and ICS853S01AGI-01LFT, SI5338M-B05847-GMR uniquely balances PCIe Gen 4 compliance, full I²C programmability, and industrial temperature operation in a compact 24-QFN - making it optimal for field-upgradable, multi-standard timing in deployed infrastructure gear.

Availability

SI5338M-B05847-GMR is available at Aetrix Electronics and suitable for PCIe Gen 4 switch timing, broadcast video synchronization, and FPGA/processor clocking requiring stable component supply, long-term lifecycle assurance, and traceable sourcing.

Supply support for SI5338M-B05847-GMR includes scheduled delivery planning, volume procurement assistance, BOM continuity management, traceable sourcing, and lifecycle availability coordination for OEM customers, industrial embedded developers, connected-device designers, and electronics production programs.

Manufacturer

Skyworks Solutions is a global leader in analog and mixed-signal semiconductors, specializing in RF, timing, and connectivity solutions for infrastructure, automotive, and mobile markets.

The Si5338 product line was designed specifically for high-performance, software-configurable clock generation in multi-standard serial interface systems - targeting PCIe, Ethernet, Fibre Channel, and broadcast video timing where jitter, flexibility, and footprint matter.

FAQ

What is the maximum output frequency supported by SI5338M-B05847-GMR in LVPECL mode?

The SI5338M-B05847-GMR supports up to 710 MHz in LVPECL mode on any of its four differential output pairs (CLK0A/B through CLK3A/B), provided the VCO frequency remains within specification and only two unique frequencies above 350 MHz are active simultaneously (Fvco/4 and Fvco/6). This capability is confirmed in Table 6 of the official Skyworks datasheet Rev. 1.6.

Does SI5338M-B05847-GMR support PCIe Gen 4 Common Clock compliance out of the box?

Yes, SI5338M-B05847-GMR is explicitly validated for PCIe Gen 4 Common Clock compliance with 0.15–0.45 ps RMS jitter (Table 12), meeting the PCI-SIG Base Specification 4.0 rev. 0.5 requirements. No external components or layout modifications are needed - compliance is achieved using standard HCSL 100 MHz output configuration and recommended PLL bandwidth settings.

Can SI5338M-B05847-GMR generate different output voltages on each channel?

Yes, SI5338M-B05847-GMR provides independent output buffer supplies (VDDO0, VDDO1, VDDO2, VDDO3), allowing each of the four output drivers to operate at 1.5 V, 1.8 V, 2.5 V, or 3.3 V - enabling direct interfacing with mixed-voltage FPGAs, ASICs, and SerDes blocks without external level shifters.

Is ClockBuilder Pro software required to configure SI5338M-B05847-GMR?

No, ClockBuilder Pro is optional but strongly recommended for SI5338M-B05847-GMR configuration. The device supports full I²C/SMBus register access for custom firmware implementation; however, ClockBuilder Pro provides validated GUI-based setup, PCIe jitter optimization presets, and automatic constraint checking - significantly reducing bring-up time and risk of misconfiguration.

What is the thermal resistance (θJA) of SI5338M-B05847-GMR in still air?

The SI5338M-B05847-GMR has a junction-to-ambient thermal resistance (θJA) of 37 °C/W under still-air conditions, as specified in Table 4 of the Skyworks datasheet Rev. 1.6. This value assumes proper PCB land pattern per JEDEC MS-012 and use of the exposed thermal pad connected to a solid ground plane for optimal heat dissipation.

SI5338M-B05847-GMR Specifications

Product attributes: Attribute value

Manufacturer:: Skyworks Solutions Inc.

Series:: MultiSynth™

Package/Case:: 24-VFQFN Exposed Pad

Packaging:: Tape & Reel (TR)

Product Status:: Active

Programmable:: Not Verified

PLL:: -

Main Purpose:: -

Input:: -

Output:: -

Number of Circuits:: -

Ratio - Input:Output:: -

Differential - Input:Output:: -

Frequency - Max:: -

Voltage - Supply:: -

Operating Temperature:: -

Mounting Type:: Surface Mount

Grade:: -

Qualification:: -

Supplier Device Package:: 24-QFN (4x4)

SI5338M-B05847-GMR FAQ

1.How can I place an order for SI5338M-B05847-GMR through Aetrix?

Please submit a Request for Quotation (RFQ) for SI5338M-B05847-GMR on Aetrix. Our sales agent will provide a competitive quotation and guide you through the order confirmation once you accept the terms.

2.Are the price and stock information for SI5338M-B05847-GMR reliable?

The price and inventory of SI5338M-B05847-GMR are updated periodically and may fluctuate due to market conditions. Stock and pricing data are typically refreshed every 24 hours. Quotation validity for SI5338M-B05847-GMR is usually 5 days.

3.What payment methods are accepted for SI5338M-B05847-GMR?

We accept Wire Transfer, PayPal, Credit Card, Western Union, MoneyGram, and Escrow for SI5338M-B05847-GMR transactions.

Note: Certain payment methods may incur a processing fee.

4.How is shipping managed for SI5338M-B05847-GMR?

SI5338M-B05847-GMR orders can be shipped via leading logistics carriers, including DHL, UPS, FedEx, TNT, or Registered Mail.

Once your SI5338M-B05847-GMR order is processed, you will receive an email with the shipment details and tracking number.

Note: Tracking information may take up to 24 hours to appear. Express delivery typically takes 3–5 business days.

5.How can I obtain technical support or documentation for SI5338M-B05847-GMR?

For technical support, including SI5338M-B05847-GMR datasheets, pinout diagrams, or application guidance, please contact our engineering support team. They can provide detailed documentation and assistance for your SI5338M-B05847-GMR requirements.

6.How does Aetrix verify that SI5338M-B05847-GMR is sourced from the original manufacturer or authorized distributors?

All SI5338M-B05847-GMR products on Aetrix are procured from qualified distributors and authorized channels. Our dedicated quality assurance team conducts strict verification, including traceability checks and, if necessary, third-party testing. This ensures that SI5338M-B05847-GMR meets industry standards.

7.What is the process for return or replacement of SI5338M-B05847-GMR?

All SI5338M-B05847-GMR units undergo pre-shipment inspection (PSI). If there is an issue with SI5338M-B05847-GMR, returns or replacements are accepted under the following conditions:

1.Quantity discrepancies, incorrect items, or visible external defects (such as breakage or corrosion), acknowledged by Aetrix.

2.The issue is reported within 90 days of delivery.

3.The SI5338M-B05847-GMR part is unused and in its original packaging.

Return procedure for SI5338M-B05847-GMR:

1.Submit a request within 90 days.

2.Obtain a Return Material Authorization (RMA) from Aetrix.

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