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Home > Products > Integrated Circuits (ICs) > Clock/Timing > Application Specific Clock/Timing

Skyworks Solutions Inc. SI5338M-B05848-GMR

Name: SI5338M-B05848-GMR
Brand: Skyworks Solutions Inc.
SKU: SI5338M-B05848-GMR
Price: 2.40 USD
Availability: InStock
Rating: 5 (2 reviews)

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Part No.:: SI5338M-B05848-GMR

Manufacturer:: Skyworks Solutions Inc.

Category:: Application Specific Clock/Timing

Package:: 24-VFQFN Exposed Pad

Datasheet:: SI5338M-B05848-GMR.pdf

Description:: I2C CONTROL, 4-OUTPUT, ANY FREQU

Quantity:: RFQ Add To RFQ list

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Product details

Overview

SI5338M-B05848-GMR from Skyworks Solutions is an I²C-programmable quad clock generator with four independently configurable differential or single-ended outputs, 0.7 ps RMS typical phase jitter, PCIe Gen 1–4 Common Clock and Gen 3 SRNS compliance, and operation from 1.8/2.5/3.3 V core supply in a 4 × 4 mm 24-QFN package. It replaces up to four crystal oscillators in high-speed serial interface timing applications.

For engineers reviewing the SI5338M-B05848-GMR datasheet, SI5338M-B05848-GMR pinout, SI5338M-B05848-GMR application, or SI5338M-B05848-GMR equivalent, key selection criteria include PCIe Gen 4 jitter compliance (0.15–0.45 ps RMS), independent output voltage per driver (1.5/1.8/2.5/3.3 V), MultiSynth™ fractional synthesis resolution (1 ppb), spread-spectrum control (0.5–5.0% deviation), and loss-of-lock/loss-of-signal alarm support.

Technical Context

The SI5338M-B05848-GMR implements a two-stage PLL architecture: a high-stability integer-N PLL (Stage 1) locks to one of six input references (crystal, CMOS, SSTL/HSTL, or differential), followed by four independent MultiSynth™ fractional-N synthesis blocks (Stage 2) generating output clocks with zero-ppm accuracy. Each output supports programmable format (LVPECL/LVDS/HCSL/CMOS/SSTL/HSTL) and voltage (1.5–3.3 V).

It features pin-controlled or I²C-driven frequency/phase increment/decrement (20 ps step accuracy, ±45 ns range), external feedback mode for zero-delay operation, and configurable spread-spectrum modulation (33–63 kHz rate, 0.5–5.0% spread) on any output. Input-to-output propagation delay is 2.5–4 ns in buffer mode.

Key Specifications

Parameter	Value and Actual Design Meaning
Phase Jitter (RMS)	0.7 ps typ (12 kHz–20 MHz); meets PCIe Gen 4 common clock jitter spec (0.15–0.45 ps RMS)
Output Count & Type	4 differential outputs (CLK0A/B–CLK3A/B); supports up to 8 single-ended or mixed configurations
Frequency Range	0.16–710 MHz per output; LVPECL/LVDS up to 710 MHz, HCSL up to 250 MHz, CMOS up to 200 MHz
Synthesis Resolution	1 ppb; enables true zero-ppm frequency accuracy across all outputs
Supply Voltages	Core: 1.8/2.5/3.3 V (±10%); Output buffers: 1.4–3.63 V, independently configurable per driver
Operating Temp	–40 °C to +85 °C; qualified for industrial embedded and telecom line card environments
Package	24-pin QFN, 4 × 4 mm, 0.5 mm pitch; RoHS-compliant, halogen-free

Pinout & Package

SI5338M-B05848-GMR uses a 24-lead QFN package (4 × 4 mm, 0.5 mm pitch) with exposed thermal pad. Pin assignments are fixed per Si5338 family: IN1/IN2 (differential ref 1), IN3/IN4 (single-ended ref), IN5/IN6 (differential ref 2/3), CLK0A–CLK3B (four differential output pairs), VDD (core supply), VDDO0–VDDO3 (independent output buffer supplies), SCL/SDA/INTR (I²C interface and interrupt), and GND/RSVD_GND.

Pin/Terminal	Circuit Role	Design Meaning
IN1, IN2	Differential reference input 1	Accepts 5–710 MHz AC-coupled differential clock; internal 100 Ω termination
IN3, IN4	Single-ended reference inputs	Support 5–200 MHz CMOS, 5–350 MHz SSTL/HSTL; 20 kΩ pull-up/down configurable
IN5, IN6	Differential reference inputs 2 & 3	Same specs as IN1/IN2; enables multi-reference redundancy or translation
CLK0A, CLK0B – CLK3A, CLK3B	Differential output pairs	Four independent drivers; each configurable for LVPECL/LVDS/HCSL/CML/SSTL/HSTL
VDDO0 – VDDO3	Output buffer supply rails	Independent 1.4–3.63 V supplies per output pair; enables mixed-voltage system interfacing
SCL, SDA	I²C serial interface	SMBus-compatible; supports standard/fast-mode (100/400 kHz) and clock stretching
INTR	Interrupt output	Open-drain status flag for loss-of-lock (LOL) and loss-of-signal (LOS) events

Key Features

Feature	Design Value
MultiSynth™ synthesis	Four independent fractional-N synthesizers enabling any-frequency generation (0.16–710 MHz) with 1 ppb resolution and zero ppm error
PCIe Gen 4 compliance	Meets PCIe Base Spec 4.0 common clock jitter requirement (0.15–0.45 ps RMS) without external filtering
Programmable spread spectrum	Configurable on any output: 0.5–5.0% spread, 33–63 kHz modulation rate - reduces EMI in dense PCB layouts
Glitchless frequency tuning	Pin- or I²C-controlled frequency increment/decrement in 1 ppm steps with <667 ns update time above 18 MHz
Phase adjustment	Independent per-output phase offset (–45 to +45 ns) with <20 ps step accuracy for skew compensation
Zero-delay mode	External feedback path enables synchronous clock distribution with minimal latency and deterministic skew

Applications

PCIe Gen 4 Switch Timing	Ethernet Switch/Routing
Use Scenario: Providing synchronized 100 MHz reference clocks to multiple PCIe Gen 4 switch ICs in a data center fabric. IC Role / Device Role / Timing Role: Quad clock generator delivering four low-jitter (0.15–0.45 ps RMS) HCSL outputs compliant with PCIe Gen 4 Common Clock architecture. Use Value: Eliminates need for four discrete oscillators; ensures inter-lane skew <100 ps and meets Intel Clock Jitter Tool validation requirements.	Use Scenario: Driving 1 GbE and 10 GbE PHYs and MACs in carrier-grade Ethernet switches with shared and independent clock domains. IC Role / Device Role / Timing Role: Configurable buffer and level translator supporting mixed CMOS (25/125 MHz), LVDS (156.25 MHz), and HSTL (312.5 MHz) outputs from a single 25 MHz crystal. Use Value: Reduces BOM count and layout area; enables dynamic frequency switching during link training without glitching.
Broadcast Video Timing	FPGA/Processor Clocking
Use Scenario: Generating SMPTE ST 2082 (12G-SDI) 297 MHz, AES11 48 kHz audio word clock, and genlock reference from one device in broadcast video equipment. IC Role / Device Role / Timing Role: Any-frequency clock converter synthesizing non-integer-related frequencies (297 MHz, 48 kHz, 10 MHz) simultaneously with <0.7 ps RMS jitter. Use Value: Replaces multiple crystals and fanout buffers; maintains frame sync integrity across video/audio subsystems.	Use Scenario: Supplying core, DDR, and peripheral clocks to Xilinx Versal or Intel Agilex FPGAs in adaptive compute platforms. IC Role / Device Role / Timing Role: Programmable clock generator delivering 500 MHz LVDS (core), 1333 MHz HSTL (DDR4), and 100 MHz CMOS (peripherals) from a 25 MHz reference. Use Value: Enables full FPGA configuration via ClockBuilder Pro; supports dynamic voltage/frequency scaling (DVFS) via I²C.

PCIe Gen 4 Switch Timing

Ethernet Switch/Routing

Use Scenario: Providing synchronized 100 MHz reference clocks to multiple PCIe Gen 4 switch ICs in a data center fabric.

IC Role / Device Role / Timing Role: Quad clock generator delivering four low-jitter (0.15–0.45 ps RMS) HCSL outputs compliant with PCIe Gen 4 Common Clock architecture.

Use Value: Eliminates need for four discrete oscillators; ensures inter-lane skew <100 ps and meets Intel Clock Jitter Tool validation requirements.

Use Scenario: Driving 1 GbE and 10 GbE PHYs and MACs in carrier-grade Ethernet switches with shared and independent clock domains.

IC Role / Device Role / Timing Role: Configurable buffer and level translator supporting mixed CMOS (25/125 MHz), LVDS (156.25 MHz), and HSTL (312.5 MHz) outputs from a single 25 MHz crystal.

Use Value: Reduces BOM count and layout area; enables dynamic frequency switching during link training without glitching.

Broadcast Video Timing

FPGA/Processor Clocking

Use Scenario: Generating SMPTE ST 2082 (12G-SDI) 297 MHz, AES11 48 kHz audio word clock, and genlock reference from one device in broadcast video equipment.

IC Role / Device Role / Timing Role: Any-frequency clock converter synthesizing non-integer-related frequencies (297 MHz, 48 kHz, 10 MHz) simultaneously with <0.7 ps RMS jitter.

Use Value: Replaces multiple crystals and fanout buffers; maintains frame sync integrity across video/audio subsystems.

Use Scenario: Supplying core, DDR, and peripheral clocks to Xilinx Versal or Intel Agilex FPGAs in adaptive compute platforms.

IC Role / Device Role / Timing Role: Programmable clock generator delivering 500 MHz LVDS (core), 1333 MHz HSTL (DDR4), and 100 MHz CMOS (peripherals) from a 25 MHz reference.

Use Value: Enables full FPGA configuration via ClockBuilder Pro; supports dynamic voltage/frequency scaling (DVFS) via I²C.

Equivalent & Alternatives

The following parts are listed as comparable options for similar quad clock generator applications.

Alternative Part	Technical Difference	Application Difference	Selection Advice
Si5332A-D05848-GM	Higher integration: 8 outputs, integrated EEPROM, lower jitter (0.35 ps RMS), supports JESD204B deterministic latency	Targeted at JESD204B SerDes, radar, and 5G wireless infrastructure requiring sub-ps jitter and deterministic phase alignment	Select when >4 outputs, deterministic latency, or <0.4 ps jitter is required; not drop-in compatible due to different pinout and register map
ICS853S01AGI-01LFT	Fixed-function 4-output LVDS clock generator; no I²C programming; 1.2 ps RMS jitter; 0.1–700 MHz range	Cost-sensitive, high-volume applications where frequency flexibility is not needed (e.g., legacy PCIe Gen 2/3 systems)	Select for simplified design and lower unit cost where field reprogramming and multi-standard compliance are unnecessary

Compared with Si5332A-D05848-GM and ICS853S01AGI-01LFT, SI5338M-B05848-GMR uniquely balances programmability, PCIe Gen 4 compliance, and industrial temperature operation in a compact 24-QFN footprint-making it optimal for mid-tier networking and FPGA-based embedded systems requiring field-upgradable timing.

Availability

SI5338M-B05848-GMR is available at Aetrix Electronics and suitable for PCIe Gen 4 switch timing, Ethernet switch/routing, and broadcast video timing requiring stable component supply, long-term lifecycle support, and traceable sourcing.

Supply support for SI5338M-B05848-GMR includes scheduled delivery planning, volume procurement assistance, BOM continuity management, traceable sourcing, and lifecycle availability coordination for OEM customers, industrial embedded developers, connected-device designers, and electronics production programs.

Manufacturer

Skyworks Solutions is a global leader in analog and mixed-signal semiconductors, specializing in RF, timing, and connectivity solutions for infrastructure, automotive, and mobile markets.

The Si5338 product line delivers highly configurable, low-jitter clock generation for high-speed serial interfaces-including PCIe, Ethernet, Fibre Channel, and broadcast video-enabling system-level timing consolidation and jitter reduction.

FAQ

What is the maximum output frequency supported by SI5338M-B05848-GMR in LVPECL mode?

The SI5338M-B05848-GMR supports up to 710 MHz in LVPECL output mode, as specified in Table 6 of the datasheet. This capability enables direct clocking of high-speed SerDes lanes in PCIe Gen 4 and 10G Ethernet applications without external frequency multiplication. Operation above 350 MHz is limited to two unique frequencies simultaneously (Fvco/4 and Fvco/6) due to VCO constraints.

Does SI5338M-B05848-GMR support PCIe Gen 4 Separate Reference No Spread (SRNS) mode?

Yes, SI5338M-B05848-GMR is compliant with PCIe Gen 4 SRNS requirements, achieving 0.11–0.32 ps RMS jitter under specified conditions (PLL BW 2–4 MHz, CDR = 10 MHz). This is validated per PCI Express Base Specification 4.0 rev. 0.5 and confirmed using the Skyworks PCIe Clock Jitter Tool.

Can SI5338M-B05848-GMR generate four completely independent output frequencies?

Yes, SI5338M-B05848-GMR uses four independent MultiSynth™ fractional-N synthesizers, allowing any combination of four frequencies between 0.16–710 MHz (depending on format) with zero ppm precision. Each output is fully decoupled in frequency, phase, and format-enabling true multi-domain clocking from a single device.

What reference inputs does SI5338M-B05848-GMR accept?

SI5338M-B05848-GMR accepts six reference inputs: two differential pairs (IN1/IN2, IN5/IN6) supporting 5–710 MHz; two single-ended pins (IN3, IN4) supporting CMOS (5–200 MHz), SSTL/HSTL (5–350 MHz); and an internal crystal oscillator supporting 8–30 MHz crystals. All inputs are selectable via register configuration.

Is ClockBuilder Pro software required to configure SI5338M-B05848-GMR?

No, ClockBuilder Pro is optional but strongly recommended for SI5338M-B05848-GMR configuration. The device can be programmed directly via I²C using custom firmware; however, ClockBuilder Pro provides GUI-based frequency planning, jitter optimization, register file generation, and hardware validation-significantly reducing development time and risk of misconfiguration.

SI5338M-B05848-GMR Specifications

Product attributes: Attribute value

Manufacturer:: Skyworks Solutions Inc.

Series:: MultiSynth™

Package/Case:: 24-VFQFN Exposed Pad

Packaging:: Tape & Reel (TR)

Product Status:: Active

Programmable:: Not Verified

PLL:: -

Main Purpose:: -

Input:: -

Output:: -

Number of Circuits:: -

Ratio - Input:Output:: -

Differential - Input:Output:: -

Frequency - Max:: -

Voltage - Supply:: -

Operating Temperature:: -

Mounting Type:: Surface Mount

Grade:: -

Qualification:: -

Supplier Device Package:: 24-QFN (4x4)

SI5338M-B05848-GMR FAQ

1.How can I place an order for SI5338M-B05848-GMR through Aetrix?

Please submit a Request for Quotation (RFQ) for SI5338M-B05848-GMR on Aetrix. Our sales agent will provide a competitive quotation and guide you through the order confirmation once you accept the terms.

2.Are the price and stock information for SI5338M-B05848-GMR reliable?

The price and inventory of SI5338M-B05848-GMR are updated periodically and may fluctuate due to market conditions. Stock and pricing data are typically refreshed every 24 hours. Quotation validity for SI5338M-B05848-GMR is usually 5 days.

3.What payment methods are accepted for SI5338M-B05848-GMR?

We accept Wire Transfer, PayPal, Credit Card, Western Union, MoneyGram, and Escrow for SI5338M-B05848-GMR transactions.

Note: Certain payment methods may incur a processing fee.

4.How is shipping managed for SI5338M-B05848-GMR?

SI5338M-B05848-GMR orders can be shipped via leading logistics carriers, including DHL, UPS, FedEx, TNT, or Registered Mail.

Once your SI5338M-B05848-GMR order is processed, you will receive an email with the shipment details and tracking number.

Note: Tracking information may take up to 24 hours to appear. Express delivery typically takes 3–5 business days.

5.How can I obtain technical support or documentation for SI5338M-B05848-GMR?

For technical support, including SI5338M-B05848-GMR datasheets, pinout diagrams, or application guidance, please contact our engineering support team. They can provide detailed documentation and assistance for your SI5338M-B05848-GMR requirements.

6.How does Aetrix verify that SI5338M-B05848-GMR is sourced from the original manufacturer or authorized distributors?

All SI5338M-B05848-GMR products on Aetrix are procured from qualified distributors and authorized channels. Our dedicated quality assurance team conducts strict verification, including traceability checks and, if necessary, third-party testing. This ensures that SI5338M-B05848-GMR meets industry standards.

7.What is the process for return or replacement of SI5338M-B05848-GMR?

All SI5338M-B05848-GMR units undergo pre-shipment inspection (PSI). If there is an issue with SI5338M-B05848-GMR, returns or replacements are accepted under the following conditions:

1.Quantity discrepancies, incorrect items, or visible external defects (such as breakage or corrosion), acknowledged by Aetrix.

2.The issue is reported within 90 days of delivery.

3.The SI5338M-B05848-GMR part is unused and in its original packaging.

Return procedure for SI5338M-B05848-GMR:

1.Submit a request within 90 days.

2.Obtain a Return Material Authorization (RMA) from Aetrix.

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