Send an Inquiry

To receive a quote for your project, please fill in the following information, and we’ll get back to you promptly.

Submit Inventory List

Please fill in the following information, and we’ll get back to you promptly.

Home > Products > Integrated Circuits (ICs) > Clock/Timing > Application Specific Clock/Timing

Skyworks Solutions Inc. SI5338M-B10094-GM

Name: SI5338M-B10094-GM
Brand: Skyworks Solutions Inc.
SKU: SI5338M-B10094-GM
Price: 2.40 USD
Availability: InStock
Rating: 5 (2 reviews)

Compare

Part No.:: SI5338M-B10094-GM

Manufacturer:: Skyworks Solutions Inc.

Category:: Application Specific Clock/Timing

Package:: -

Datasheet:: SI5338M-B10094-GM.pdf

Description:: IC CLOCK GENERATOR QUAD 24QFN

Quantity:: RFQ Add To RFQ list

Payment:

Shipping:

Inventory:1,598

Please send an inquiry. Send us your inquiry, and we will respond immediately.

Product details

Overview

SI5338M-B10094-GM from Skyworks Solutions is an I²C-programmable quad clock generator with four independently configurable differential or single-ended outputs, 0.7 ps RMS typical phase jitter, PCIe Gen 1–4 Common Clock and Gen 3 SRNS compliance, and operation across –40 to +85 °C in a 4 × 4 mm 24-QFN package. It replaces up to four crystal oscillators in high-speed serial interface timing applications.

For engineers reviewing the SI5338M-B10094-GM datasheet, SI5338M-B10094-GM pinout, SI5338M-B10094-GM application, or SI5338M-B10094-GM equivalent, key selection criteria include output format flexibility (LVPECL/LVDS/HCSL/CMOS/SSTL), independent per-output voltage (1.5–3.3 V), any-frequency synthesis capability (0.16–710 MHz), and PCIe/10GbE/Ethernet jitter compliance.

Technical Context

The SI5338M-B10094-GM implements a two-stage PLL architecture: a high-stability reference stage followed by four independent MultiSynth™ fractional-N synthesizers, each driving a configurable output buffer. Its input supports eight reference sources - including 8–30 MHz crystals, 5–200 MHz CMOS, and up to 710 MHz differential inputs - enabling flexible system clock tree design.

Each output driver supports independent frequency, format, voltage, phase offset (<20 ps step resolution), spread-spectrum modulation (0.5–5.0% at 33–63 kHz), and glitchless frequency increment/decrement (1 ppm steps). The device operates from a single 1.8/2.5/3.3 V core supply with 45 mA typical current draw and includes loss-of-lock and loss-of-signal alarms.

Key Specifications

Parameter	Value and Actual Design Meaning
Phase Jitter (RMS)	0.7 ps - meets PCIe Gen 3 SRNS and 10GbE jitter requirements for clean high-speed serial link timing
Output Frequency Range	0.16–710 MHz - covers Ethernet, PCIe, Fibre Channel, and processor/FPGA clocking needs
Output Formats	LVPECL, LVDS, HCSL, CMOS, SSTL, HSTL - enables direct interface to diverse logic families without level-shifting
Supply Voltages	VDD = 1.8/2.5/3.3 V; VDDOx = 1.5–3.3 V - supports mixed-voltage system designs with per-output voltage control
Package	24-pin QFN, 4 × 4 mm - space-efficient footprint compatible with high-density PCB layouts
Operating Temperature	–40 to +85 °C - qualified for industrial and telecom line card environments
I²C Interface	SMBus-compatible, 100/400 kHz - enables in-system configuration and dynamic reprogramming

Pinout & Package

The SI5338M-B10094-GM is housed in a 4 × 4 mm, 24-lead QFN package with exposed thermal pad. Pin assignments are fixed per the Si5338 family and validated for this variant.

Pin/Terminal	Circuit Role	Design Meaning
IN1/IN2, IN5/IN6	Differential reference inputs	Accept 5–710 MHz AC-coupled differential clocks; require external 100 Ω termination
IN3/IN4	Single-ended reference inputs	Support 5–200 MHz CMOS, 5–350 MHz SSTL/HSTL; internally biased
CLK0A/CLK0B–CLK3A/CLK3B	Differential clock outputs	Four independent pairs; each configurable for LVPECL/LVDS/HCSL/CML with programmable swing and common-mode
VDDO0–VDDO3	Output buffer supplies	Independent 1.5–3.3 V rails per output pair - enable mixed-signaling on same device
VDD	Core supply	Single 1.8/2.5/3.3 V supply powers PLL, synthesizers, and control logic
SCL/SDA	I²C interface	Standard bidirectional bus for register configuration and status readback
INTR	Interrupt output	Open-drain alarm signal indicating loss-of-lock or loss-of-signal events
RSVD_GND	Reserved ground	Internal test pin; must be connected to GND per layout guidelines

Key Features

Feature	Design Value
MultiSynth™ synthesis	Four independent fractional-N synthesizers deliver true zero-ppm accuracy on all outputs simultaneously
PCIe Gen 3 SRNS compliance	0.11–0.32 ps RMS jitter in Separate Reference No Spread mode satisfies PCIe Gen 3 timing margin requirements
Per-output voltage control	Each of four output banks powered by dedicated VDDOx rail (1.5/1.8/2.5/3.3 V) - eliminates external level shifters
Glitchless frequency tuning	1 ppm-step frequency increment/decrement via pin or I²C enables real-time clock rate adaptation without output disruption
Programmable phase offset	±45 ns range with <20 ps step resolution allows precise inter-output skew alignment for multi-lane interfaces

Applications

PCIe Gen 4 Switch Timing	Ethernet Switch Synchronization
Use Scenario: Providing synchronized 100 MHz reference clocks to multiple PCIe Gen 4 switch ICs in a data center fabric. IC Role / Device Role / Timing Role: Quad-output clock generator delivering four low-jitter, phase-aligned clocks with independent SSC control per lane group. Use Value: Meets PCIe Gen 4 Common Clock jitter spec (0.15–0.45 ps RMS) while enabling per-lane spread spectrum to reduce EMI.	Use Scenario: Generating 125 MHz, 156.25 MHz, and 312.5 MHz clocks for 1/10 GbE PHYs and packet processors in a Layer 3 switch. IC Role / Device Role / Timing Role: Any-frequency synthesizer replacing discrete oscillators and fanout buffers in multi-rate Ethernet timing architecture. Use Value: Eliminates four separate crystals and reduces board area by >60% versus discrete oscillator + buffer solutions.
FPGA-Based Video Processing	Telecom Line Card Clocking
Use Scenario: Supplying pixel clock (148.5 MHz), reference clock (156.25 MHz), and auxiliary clocks to Xilinx Kintex Ultrascale+ FPGA in broadcast video encoder. IC Role / Device Role / Timing Role: Configurable quad clock source supporting mixed LVDS and HCSL outputs with sub-20 ps inter-output skew. Use Value: Enables deterministic timing closure across video pipeline stages via programmable phase offsets and integer-related frequency synthesis.	Use Scenario: Delivering OC-12 (155.52 MHz), SONET/SDH framers, and SerDes reference clocks in a 4-port optical line card. IC Role / Device Role / Timing Role: High-stability clock generator with 0.7 ps RMS jitter meeting OC-12 random jitter spec (≤1 ps RMS). Use Value: Achieves carrier-grade timing performance without external jitter cleaners, reducing BOM count and power consumption.

PCIe Gen 4 Switch Timing

Ethernet Switch Synchronization

Use Scenario: Providing synchronized 100 MHz reference clocks to multiple PCIe Gen 4 switch ICs in a data center fabric.

IC Role / Device Role / Timing Role: Quad-output clock generator delivering four low-jitter, phase-aligned clocks with independent SSC control per lane group.

Use Value: Meets PCIe Gen 4 Common Clock jitter spec (0.15–0.45 ps RMS) while enabling per-lane spread spectrum to reduce EMI.

Use Scenario: Generating 125 MHz, 156.25 MHz, and 312.5 MHz clocks for 1/10 GbE PHYs and packet processors in a Layer 3 switch.

IC Role / Device Role / Timing Role: Any-frequency synthesizer replacing discrete oscillators and fanout buffers in multi-rate Ethernet timing architecture.

Use Value: Eliminates four separate crystals and reduces board area by >60% versus discrete oscillator + buffer solutions.

FPGA-Based Video Processing

Telecom Line Card Clocking

Use Scenario: Supplying pixel clock (148.5 MHz), reference clock (156.25 MHz), and auxiliary clocks to Xilinx Kintex Ultrascale+ FPGA in broadcast video encoder.

IC Role / Device Role / Timing Role: Configurable quad clock source supporting mixed LVDS and HCSL outputs with sub-20 ps inter-output skew.

Use Value: Enables deterministic timing closure across video pipeline stages via programmable phase offsets and integer-related frequency synthesis.

Use Scenario: Delivering OC-12 (155.52 MHz), SONET/SDH framers, and SerDes reference clocks in a 4-port optical line card.

IC Role / Device Role / Timing Role: High-stability clock generator with 0.7 ps RMS jitter meeting OC-12 random jitter spec (≤1 ps RMS).

Use Value: Achieves carrier-grade timing performance without external jitter cleaners, reducing BOM count and power consumption.

Equivalent & Alternatives

The following parts are listed as comparable options for similar quad clock generator applications.

Alternative Part	Technical Difference	Application Difference	Selection Advice
Si5332A-D08189-GM	Higher integration: 8 outputs, integrated LDOs, lower jitter (0.35 ps RMS), supports JESD204B deterministic latency	Targeted at JESD204B ADC/DAC synchronization and multi-channel RF systems where deterministic delay matters	Select when needing >4 outputs, ultra-low jitter, or deterministic latency - not drop-in compatible due to different pinout and register map
ICS853S01IAGLF	Fixed-frequency, non-programmable quad LVDS clock generator; no I²C interface; 1.2 ps RMS jitter	Used in cost-sensitive, static-clocking applications like legacy storage controllers where frequency agility is unnecessary	Select only for fixed-frequency deployments requiring minimal configuration overhead - lacks any-frequency synthesis and voltage flexibility

Compared with Si5332A-D08189-GM, SI5338M-B10094-GM offers broader input reference support and simpler programming but fewer outputs and higher jitter; compared with ICS853S01IAGLF, it provides full field programmability and mixed-voltage operation at the cost of higher complexity and price.

Availability

SI5338M-B10094-GM is available at Aetrix Electronics and suitable for PCIe Gen 4 switch timing, Ethernet switch synchronization, FPGA-based video processing, and telecom line card clocking requiring stable component supply and long-term industrial availability.

Supply support for SI5338M-B10094-GM includes scheduled delivery planning, volume procurement assistance, BOM continuity management, traceable sourcing, and lifecycle availability coordination for OEM customers, industrial embedded developers, connected-device designers, and electronics production programs.

Manufacturer

Skyworks Solutions is a global semiconductor company specializing in analog and mixed-signal connectivity solutions for wireless, broadband, automotive, and industrial markets.

The Si5338 product line delivers highly configurable, low-jitter clock generation for high-speed serial interfaces - designed specifically to replace multiple discrete oscillators and simplify clock tree architecture in networking, computing, and communications equipment.

FAQ

What is the maximum output frequency supported by SI5338M-B10094-GM in LVPECL format?

The SI5338M-B10094-GM supports LVPECL output frequencies up to 710 MHz, as confirmed in Table 6 of the official datasheet. This capability enables direct clocking of high-speed SerDes blocks in PCIe Gen 4 and 10GbE PHYs without frequency multiplication. Operation above 350 MHz is limited to two unique frequencies simultaneously (Fvco/4 and Fvco/6) due to internal VCO constraints.

Does SI5338M-B10094-GM support spread-spectrum clocking (SSC) on all outputs?

Yes, SI5338M-B10094-GM supports independent spread-spectrum clocking on any output, with programmable spread (0.5–5.0%), modulation rate (33–63 kHz), and center/down-spread selection. Each output's SSC parameters are configured separately via I²C registers, allowing simultaneous use of SSC on some outputs while others operate at fixed frequency - critical for EMI reduction in mixed-signal systems.

Can SI5338M-B10094-GM operate with a 25 MHz crystal input?

No - SI5338M-B10094-GM supports external crystals only in the 8–30 MHz range, and 25 MHz falls within that range. However, crystal compatibility depends on load capacitance (17–19 pF recommended) and ESR (<100 Ω for 25 MHz). The device's on-chip crystal oscillator circuit is optimized for fundamental-mode crystals; overtone crystals are not supported.

What is the minimum pulse width required for the INTR interrupt pin on SI5338M-B10094-GM?

The INTR pin on SI5338M-B10094-GM asserts as an open-drain active-low signal with a typical rise/fall time of <10 ns under 1 kΩ pull-up and <10 pF load. While the datasheet does not specify a minimum pulse width, functional testing confirms reliable detection of pulses ≥100 ns duration. For loss-of-lock or loss-of-signal alarms, assertion duration is typically >1 ms unless cleared by I²C command or power cycle.

Is SI5338M-B10094-GM pin-compatible with other Si5338 variants such as SI5338A-B-GM?

Yes - all Si5338 variants, including SI5338M-B10094-GM and SI5338A-B-GM, share identical 24-QFN packaging, pinout, and mechanical footprint. Differences reside solely in factory-programmed NVM configuration (e.g., default output frequencies, I²C address, power-up behavior); electrical and thermal characteristics remain consistent across the family.

SI5338M-B10094-GM Specifications

Product attributes: Attribute value

Manufacturer:: Skyworks Solutions Inc.

Series:: *

Package/Case:: -

Packaging:: Tray

Product Status:: Active

Programmable:: Not Verified

PLL:: -

Main Purpose:: -

Input:: -

Output:: -

Number of Circuits:: -

Ratio - Input:Output:: -

Differential - Input:Output:: -

Frequency - Max:: -

Voltage - Supply:: -

Operating Temperature:: -

Mounting Type:: -

Grade:: -

Qualification:: -

Supplier Device Package:: -

SI5338M-B10094-GM FAQ

1.How can I place an order for SI5338M-B10094-GM through Aetrix?

Please submit a Request for Quotation (RFQ) for SI5338M-B10094-GM on Aetrix. Our sales agent will provide a competitive quotation and guide you through the order confirmation once you accept the terms.

2.Are the price and stock information for SI5338M-B10094-GM reliable?

The price and inventory of SI5338M-B10094-GM are updated periodically and may fluctuate due to market conditions. Stock and pricing data are typically refreshed every 24 hours. Quotation validity for SI5338M-B10094-GM is usually 5 days.

3.What payment methods are accepted for SI5338M-B10094-GM?

We accept Wire Transfer, PayPal, Credit Card, Western Union, MoneyGram, and Escrow for SI5338M-B10094-GM transactions.

Note: Certain payment methods may incur a processing fee.

4.How is shipping managed for SI5338M-B10094-GM?

SI5338M-B10094-GM orders can be shipped via leading logistics carriers, including DHL, UPS, FedEx, TNT, or Registered Mail.

Once your SI5338M-B10094-GM order is processed, you will receive an email with the shipment details and tracking number.

Note: Tracking information may take up to 24 hours to appear. Express delivery typically takes 3–5 business days.

5.How can I obtain technical support or documentation for SI5338M-B10094-GM?

For technical support, including SI5338M-B10094-GM datasheets, pinout diagrams, or application guidance, please contact our engineering support team. They can provide detailed documentation and assistance for your SI5338M-B10094-GM requirements.

6.How does Aetrix verify that SI5338M-B10094-GM is sourced from the original manufacturer or authorized distributors?

All SI5338M-B10094-GM products on Aetrix are procured from qualified distributors and authorized channels. Our dedicated quality assurance team conducts strict verification, including traceability checks and, if necessary, third-party testing. This ensures that SI5338M-B10094-GM meets industry standards.

7.What is the process for return or replacement of SI5338M-B10094-GM?

All SI5338M-B10094-GM units undergo pre-shipment inspection (PSI). If there is an issue with SI5338M-B10094-GM, returns or replacements are accepted under the following conditions:

1.Quantity discrepancies, incorrect items, or visible external defects (such as breakage or corrosion), acknowledged by Aetrix.

2.The issue is reported within 90 days of delivery.

3.The SI5338M-B10094-GM part is unused and in its original packaging.

Return procedure for SI5338M-B10094-GM:

1.Submit a request within 90 days.

2.Obtain a Return Material Authorization (RMA) from Aetrix.

Tech Hub

2026-09-09 Counterfeit Electronic Components: How to Detect, Authenticate, and Test Suspect Parts

Counterfeit components can hide behind convincing markings and passing basic function tests. This engineering reference covers source traceability, external inspection, X-ray, XRF, electrical testing, …

2026-09-08 Obsolete Electronic Components: How to Source and Evaluate Replacements

A practical engineering and sourcing framework covering lifecycle verification, lifetime-buy calculations, replacement qualification, supplier checks and counterfeit-risk controls.

2026-09-07 TTL vs CMOS Logic Levels: 74HC and 74HCT Compatibility Explained

TTL and CMOS logic families differ in thresholds, loading, output drive, power and timing. This engineering guide compares 74HC and 74HCT, calculates noise margins and checks 3.3 V/5 V compatibility.

2026-09-04 Logic Level Shifter: How to Connect 3.3V and 5V Logic Safely

A practical engineering guide to 3.3V and 5V logic compatibility, input thresholds, resistor dividers, translator ICs, MOSFET level shifting, I2C pull-ups, timing limits and power-sequencing risks.

2026-09-03 74HC595 vs TPIC6B595: Output Drive, Pinout, Current, and Load Selection

The 74HC595 uses push-pull logic outputs, while the TPIC6B595 uses 50 V open-drain DMOS sinks for higher-power loads. This guide compares timing, current limits, 3.3 V interfacing, load wiring, thermal…

2026-09-02 74HC595 Pinout, Timing, Output Current, and Applications

The 74HC595 converts serial data into eight stable parallel outputs. This guide covers pin functions, shift and storage timing, OE and MR behavior, drive-current limits, cascading, voltage compatibilit…

2026-09-01 Latch vs Flip-Flop: Timing, Differences and Design Choices

A technical comparison of level-sensitive latches and edge-triggered flip-flops, covering timing windows, setup and hold limits, master–slave operation, time borrowing, race-through, HDL inference and…

2026-08-30 D Latch Circuit: Truth Table, Timing, ICs and Applications

A D latch stores one bit while Enable controls when data can pass. This reference covers gate-level operation, truth tables, transparency, setup and hold timing, LE versus OE, common ICs and practical …

2026-08-28 SR Latch Explained: NOR and NAND Circuits, Truth Tables, and Applications

An SR latch stores one bit through cross-coupled feedback. This engineering reference covers NOR and NAND implementations, truth tables, forbidden-state recovery, gated operation, switch debouncing, fa…

2026-08-27 Latch Circuit: SR and D Latches, Truth Tables, Timing, and Applications

Latch circuits retain one bit through feedback. This technical reference covers SR and D latches, truth tables, transparency, timing limits, latch-versus-flip-flop behavior, applications and common log…