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Home > Products > Integrated Circuits (ICs) > Clock/Timing > Application Specific Clock/Timing

Skyworks Solutions Inc. SI5338M-B10094-GMR

Name: SI5338M-B10094-GMR
Brand: Skyworks Solutions Inc.
SKU: SI5338M-B10094-GMR
Price: 2.40 USD
Availability: InStock
Rating: 5 (2 reviews)

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Part No.:: SI5338M-B10094-GMR

Manufacturer:: Skyworks Solutions Inc.

Category:: Application Specific Clock/Timing

Package:: -

Datasheet:: SI5338M-B10094-GMR.pdf

Description:: IC CLOCK GENERATOR QUAD 24QFN

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Product details

Overview

SI5338M-B10094-GMR from Skyworks Solutions is an I²C-programmable quad clock generator with four independently configurable differential or single-ended outputs, 0.7 ps RMS typical phase jitter, PCIe Gen 1–4 Common Clock and Gen 3 SRNS compliance, and operation from 1.8/2.5/3.3 V core supply in a 4 × 4 mm 24-QFN package. It replaces up to four crystal oscillators in high-speed serial interface timing applications.

For engineers reviewing the SI5338M-B10094-GMR datasheet, SI5338M-B10094-GMR pinout, SI5338M-B10094-GMR application, or SI5338M-B10094-GMR equivalent, key selection criteria include PCIe Gen 4 jitter compliance (0.15–0.45 ps RMS), independent output voltage per driver (1.5/1.8/2.5/3.3 V), MultiSynth™ frequency synthesis resolution (1 ppb), spread-spectrum control (0.5–5.0% spread, 33–63 kHz modulation), and loss-of-lock/loss-of-signal alarm support.

Technical Context

The SI5338M-B10094-GMR implements a two-stage PLL architecture: Stage 1 uses a VCO with programmable N-divider for reference-to-VCO frequency translation; Stage 2 employs four independent MultiSynth™ fractional-N synthesizers, each with M- and P-dividers, enabling integer or fractional output synthesis from the VCO. This supports true zero-ppm accuracy on all four outputs.

Input flexibility includes external crystal (8–30 MHz), CMOS (5–200 MHz), SSTL/HSTL (5–350 MHz), or differential (5–710 MHz) references. Output drivers support LVPECL/LVDS/HCSL/CMOS/SSTL/HSTL formats across 0.16–710 MHz, with independent voltage selection (1.5/1.8/2.5/3.3 V) and per-output phase/frequency increment/decrement (±45 ns / ±20 ps step).

Key Specifications

Parameter	Value and Actual Design Meaning
Phase Jitter (RMS)	0.7 ps typical (12 kHz–20 MHz); meets PCIe Gen 4 common clock spec (≤0.45 ps RMS)
Output Count & Type	4 independent outputs; configurable as differential (LVPECL/LVDS/HCSL/CML) or single-ended (CMOS/SSTL/HSTL)
Frequency Range	0.16–710 MHz per output; supports Fvco/4 and Fvco/6 for >350 MHz outputs
Supply Voltages	Core: 1.8/2.5/3.3 V (±10%); output buffers: 1.4–3.63 V, independently selectable per driver
Package	24-pin QFN, 4 × 4 mm, 0.5 mm pitch, exposed thermal pad
Operating Temp	–40 °C to +85 °C ambient; suitable for industrial and telecom line card environments
I²C Interface	SMBus-compatible, 100 kHz/400 kHz modes; enables full register configuration and status monitoring

Pinout & Package

SI5338M-B10094-GMR is housed in a 24-lead QFN package (4 × 4 mm, 0.5 mm pitch) with exposed thermal pad. Pin functions are validated per Skyworks Si5338 datasheet Rev. 1.6, pages 33–37.

Pin/Terminal	Circuit Role	Design Meaning
IN1, IN2, IN5, IN6	Differential input pairs	Accept 5–710 MHz AC-coupled differential clocks; require external 100 Ω termination
IN3, IN4	Single-ended inputs	Support 5–200 MHz CMOS, 5–350 MHz SSTL/HSTL; VIH = 0.7×VDD, VIL = 0.3×VDD
CLK0A–CLK3B	Differential output pairs	Four independent output drivers; each pair configurable for LVPECL/LVDS/HCSL/CML
VDDO0–VDDO3	Output buffer supplies	Independent 1.4–3.63 V supplies per output bank; set output logic level and drive strength
VDD	Core supply	1.8/2.5/3.3 V ±10%; powers PLL, MultiSynth, and control logic
SCL, SDA	I²C interface	SMBus-compatible serial bus; supports configuration, status readback, and alarm reporting
INTR	Interrupt output	Open-drain active-low signal indicating loss-of-lock or loss-of-signal events
RSVD_GND	Reserved ground	Internal no-connect; must be connected to GND per layout guidelines

Key Features

Feature	Design Value
MultiSynth™ synthesis	Four independent fractional-N synthesizers enable any-frequency generation (0.16–710 MHz) with 1 ppb resolution and true zero-ppm accuracy
PCIe Gen 4 compliance	0.15–0.45 ps RMS jitter in common clock mode satisfies PCI Express Base Spec 4.0 rev. 0.5 requirements
Per-output spread spectrum	Configurable SSC on any output: 5–350 MHz frequency range, 0.5–5.0% spread depth, 33–63 kHz modulation rate
Glitchless frequency tuning	Independent frequency increment/decrement pins enable 1 ppm-step adjustments without output interruption
Programmable phase offset	±45 ns initial phase adjustment per output with <20 ps step resolution for skew management
Alarm monitoring	Dedicated INTR pin reports loss-of-lock and loss-of-signal conditions with configurable debounce

Applications

PCIe Gen 4 Server Backplane	Ethernet Switch Timing
Use Scenario: High-density server motherboard requiring synchronized 100 MHz reference clocks for multiple PCIe Gen 4 slots and CPU interconnects. IC Role / Device Role / Timing Role: Quad clock generator providing four low-jitter, independently configured 100 MHz HCSL outputs compliant with PCIe Gen 4 Common Clock specification. Use Value: Eliminates four discrete oscillators; reduces board area by >60% and ensures sub-0.45 ps RMS jitter across all slots for Gen 4 link training stability.	Use Scenario: 10 GbE/25 GbE switch ASIC requiring multiple synchronous clocks (156.25 MHz, 312.5 MHz, 625 MHz) with tight skew control. IC Role / Device Role / Timing Role: Any-frequency clock synthesizer generating three distinct frequencies from a single 25 MHz crystal reference, with programmable phase alignment. Use Value: Enables deterministic inter-clock skew (<100 ps) between SerDes lanes and PHY interfaces, critical for multi-lane Ethernet lane deskew.
Broadcast Video Master Clock	FPGA-Based Telecom Line Card
Use Scenario: SMPTE ST 2082/ST 2081 video router needing precise 27 MHz, 74.25 MHz, and 148.5 MHz clocks with <±50 ps phase tolerance. IC Role / Device Role / Timing Role: Programmable quad clock source delivering three video-standard frequencies plus spare output for auxiliary timing, all derived from one crystal. Use Value: Achieves <20 ps phase step resolution and ±45 ns programmable offset, ensuring frame-accurate synchronization across SDI transmitters and receivers.	Use Scenario: OTN/CPRI line card with FPGA, DSP, and optical transceivers requiring isolated 125 MHz, 155.52 MHz, and 622.08 MHz clocks with different voltage levels. IC Role / Device Role / Timing Role: Multi-voltage clock generator supplying LVDS (1.8 V), HCSL (1.5 V), and CMOS (3.3 V) outputs simultaneously from one device. Use Value: Reduces BOM count by consolidating three separate clock ICs; eliminates inter-device skew and simplifies power domain isolation.

PCIe Gen 4 Server Backplane

Ethernet Switch Timing

Use Scenario: High-density server motherboard requiring synchronized 100 MHz reference clocks for multiple PCIe Gen 4 slots and CPU interconnects.

IC Role / Device Role / Timing Role: Quad clock generator providing four low-jitter, independently configured 100 MHz HCSL outputs compliant with PCIe Gen 4 Common Clock specification.

Use Value: Eliminates four discrete oscillators; reduces board area by >60% and ensures sub-0.45 ps RMS jitter across all slots for Gen 4 link training stability.

Use Scenario: 10 GbE/25 GbE switch ASIC requiring multiple synchronous clocks (156.25 MHz, 312.5 MHz, 625 MHz) with tight skew control.

IC Role / Device Role / Timing Role: Any-frequency clock synthesizer generating three distinct frequencies from a single 25 MHz crystal reference, with programmable phase alignment.

Use Value: Enables deterministic inter-clock skew (<100 ps) between SerDes lanes and PHY interfaces, critical for multi-lane Ethernet lane deskew.

Broadcast Video Master Clock

FPGA-Based Telecom Line Card

Use Scenario: SMPTE ST 2082/ST 2081 video router needing precise 27 MHz, 74.25 MHz, and 148.5 MHz clocks with <±50 ps phase tolerance.

IC Role / Device Role / Timing Role: Programmable quad clock source delivering three video-standard frequencies plus spare output for auxiliary timing, all derived from one crystal.

Use Value: Achieves <20 ps phase step resolution and ±45 ns programmable offset, ensuring frame-accurate synchronization across SDI transmitters and receivers.

Use Scenario: OTN/CPRI line card with FPGA, DSP, and optical transceivers requiring isolated 125 MHz, 155.52 MHz, and 622.08 MHz clocks with different voltage levels.

IC Role / Device Role / Timing Role: Multi-voltage clock generator supplying LVDS (1.8 V), HCSL (1.5 V), and CMOS (3.3 V) outputs simultaneously from one device.

Use Value: Reduces BOM count by consolidating three separate clock ICs; eliminates inter-device skew and simplifies power domain isolation.

Equivalent & Alternatives

The following parts are listed as comparable options for similar quad clock generator applications.

Alternative Part	Technical Difference	Application Difference	Selection Advice
Si5332A-D08189-GM	Higher integration: 8 outputs, integrated EEPROM, lower jitter (0.35 ps RMS), supports JESD204B deterministic latency	Targeted at JESD204B-compliant data converters and multi-ASIC systems requiring >4 outputs	Select when >4 outputs or deterministic latency is required; not pin-compatible
ICS853S01AGI-01LFT	Fixed-function 4-output LVDS clock fanout buffer; no frequency synthesis, no I²C programming, 1.2 ps RMS jitter	Limited to fanout-only applications with fixed input-to-output ratios; no spread spectrum or phase control	Select only for simple clock distribution where synthesis and programmability are unnecessary

Compared with Si5332A-D08189-GM and ICS853S01AGI-01LFT, the SI5338M-B10094-GMR uniquely balances programmable any-frequency synthesis, PCIe Gen 4 compliance, and compact 24-QFN packaging - making it optimal for space-constrained, multi-protocol systems requiring field-upgradable timing configurations.

Availability

SI5338M-B10094-GMR is available at Aetrix Electronics and suitable for PCIe Gen 4 server backplanes, Ethernet switching infrastructure, and broadcast video timing systems requiring stable component supply, long-term lifecycle support, and traceable sourcing.

Supply support for SI5338M-B10094-GMR includes scheduled delivery planning, volume procurement assistance, BOM continuity management, traceable sourcing, and lifecycle availability coordination for OEM customers, industrial embedded developers, connected-device designers, and electronics production programs.

Manufacturer

Skyworks Solutions is a global semiconductor company specializing in analog and mixed-signal connectivity solutions for wireless, broadband, automotive, and industrial markets.

The Si5338 product line delivers programmable, low-jitter clock generation for high-speed serial interfaces including PCIe, Ethernet, Fibre Channel, and broadcast video - designed to replace multiple fixed-frequency oscillators with a single configurable device.

FAQ

What is the maximum output frequency supported by the SI5338M-B10094-GMR?

The SI5338M-B10094-GMR supports up to 710 MHz on LVPECL/LVDS/CML outputs, 350 MHz on SSTL/HSTL, 250 MHz on HCSL, and 200 MHz on CMOS. However, only two unique frequencies above 350 MHz can be generated simultaneously (Fvco/4 and Fvco/6), as defined by the VCO operating range and MultiSynth™ architecture in the SI5338M-B10094-GMR datasheet.

Does the SI5338M-B10094-GMR support PCIe Gen 4 Separate Reference No Spread (SRNS) mode?

Yes, the SI5338M-B10094-GMR is compliant with PCIe Gen 3 SRNS and Gen 4 Common Clock specifications. Its measured RMS jitter is 0.11–0.32 ps in Gen 3 SRNS mode and 0.15–0.45 ps in Gen 4 Common Clock mode (PLL BW 2–5 MHz, CDR = 10 MHz), satisfying PCI Express Base Specification 4.0 rev. 0.5 requirements for the SI5338M-B10094-GMR.

How many independent supply voltages can be applied to the SI5338M-B10094-GMR output drivers?

The SI5338M-B10094-GMR supports four independent output buffer supply voltages (VDDO0–VDDO3), each configurable from 1.4 V to 3.63 V. This allows simultaneous LVDS (1.8 V), HCSL (1.5 V), CMOS (3.3 V), and SSTL (2.5 V) outputs - a capability confirmed in Table 6 and Section 3.4 of the SI5338M-B10094-GMR datasheet.

Can the SI5338M-B10094-GMR generate spread-spectrum clocking on individual outputs?

Yes, the SI5338M-B10094-GMR supports independent spread-spectrum clocking (SSC) on any output: frequency range 5–350 MHz, spread depth 0.5–5.0%, and modulation rate 33–63 kHz. This is implemented via dedicated registers per output and verified in Table 5 and Section 3.10.6 of the SI5338M-B10094-GMR datasheet.

What is the function of the INTR pin on the SI5338M-B10094-GMR?

The INTR pin on the SI5338M-B10094-GMR is an open-drain interrupt output that asserts low to indicate loss-of-lock (LOL) or loss-of-signal (LOS) events. Its behavior is configurable via register settings, and it supports debounced status reporting - as specified in Table 7 and Section 3.6 of the SI5338M-B10094-GMR datasheet.

SI5338M-B10094-GMR Specifications

Product attributes: Attribute value

Manufacturer:: Skyworks Solutions Inc.

Series:: *

Package/Case:: -

Packaging:: Tape & Reel (TR)

Product Status:: Active

Programmable:: Not Verified

PLL:: -

Main Purpose:: -

Input:: -

Output:: -

Number of Circuits:: -

Ratio - Input:Output:: -

Differential - Input:Output:: -

Frequency - Max:: -

Voltage - Supply:: -

Operating Temperature:: -

Mounting Type:: -

Grade:: -

Qualification:: -

Supplier Device Package:: -

SI5338M-B10094-GMR FAQ

1.How can I place an order for SI5338M-B10094-GMR through Aetrix?

Please submit a Request for Quotation (RFQ) for SI5338M-B10094-GMR on Aetrix. Our sales agent will provide a competitive quotation and guide you through the order confirmation once you accept the terms.

2.Are the price and stock information for SI5338M-B10094-GMR reliable?

The price and inventory of SI5338M-B10094-GMR are updated periodically and may fluctuate due to market conditions. Stock and pricing data are typically refreshed every 24 hours. Quotation validity for SI5338M-B10094-GMR is usually 5 days.

3.What payment methods are accepted for SI5338M-B10094-GMR?

We accept Wire Transfer, PayPal, Credit Card, Western Union, MoneyGram, and Escrow for SI5338M-B10094-GMR transactions.

Note: Certain payment methods may incur a processing fee.

4.How is shipping managed for SI5338M-B10094-GMR?

SI5338M-B10094-GMR orders can be shipped via leading logistics carriers, including DHL, UPS, FedEx, TNT, or Registered Mail.

Once your SI5338M-B10094-GMR order is processed, you will receive an email with the shipment details and tracking number.

Note: Tracking information may take up to 24 hours to appear. Express delivery typically takes 3–5 business days.

5.How can I obtain technical support or documentation for SI5338M-B10094-GMR?

For technical support, including SI5338M-B10094-GMR datasheets, pinout diagrams, or application guidance, please contact our engineering support team. They can provide detailed documentation and assistance for your SI5338M-B10094-GMR requirements.

6.How does Aetrix verify that SI5338M-B10094-GMR is sourced from the original manufacturer or authorized distributors?

All SI5338M-B10094-GMR products on Aetrix are procured from qualified distributors and authorized channels. Our dedicated quality assurance team conducts strict verification, including traceability checks and, if necessary, third-party testing. This ensures that SI5338M-B10094-GMR meets industry standards.

7.What is the process for return or replacement of SI5338M-B10094-GMR?

All SI5338M-B10094-GMR units undergo pre-shipment inspection (PSI). If there is an issue with SI5338M-B10094-GMR, returns or replacements are accepted under the following conditions:

1.Quantity discrepancies, incorrect items, or visible external defects (such as breakage or corrosion), acknowledged by Aetrix.

2.The issue is reported within 90 days of delivery.

3.The SI5338M-B10094-GMR part is unused and in its original packaging.

Return procedure for SI5338M-B10094-GMR:

1.Submit a request within 90 days.

2.Obtain a Return Material Authorization (RMA) from Aetrix.

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