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Home > Products > Integrated Circuits (ICs) > Clock/Timing > Application Specific Clock/Timing

Skyworks Solutions Inc. SI5338M-B10099-GM

Name: SI5338M-B10099-GM
Brand: Skyworks Solutions Inc.
SKU: SI5338M-B10099-GM
Price: 2.40 USD
Availability: InStock
Rating: 5 (2 reviews)

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Part No.:: SI5338M-B10099-GM

Manufacturer:: Skyworks Solutions Inc.

Category:: Application Specific Clock/Timing

Package:: -

Datasheet:: SI5338M-B10099-GM.pdf

Description:: IC CLOCK GENERATOR QUAD 24QFN

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Product details

Overview

SI5338M-B10099-GM from Skyworks Solutions is an I²C-programmable quad clock generator with four independently configurable differential or single-ended outputs, 0.7 ps RMS typical phase jitter, PCIe Gen 1–4 Common Clock and Gen 3 SRNS compliance, and operation across –40 to +85 °C in a 4 × 4 mm 24-QFN package. It replaces up to four crystal oscillators in FPGA, processor, and Ethernet switch timing systems.

For engineers reviewing the SI5338M-B10099-GM datasheet, SI5338M-B10099-GM pinout, SI5338M-B10099-GM application, or SI5338M-B10099-GM equivalent, key selection criteria include its MultiSynth™-based any-frequency synthesis (0.16–710 MHz per output), independent output voltage control (1.5/1.8/2.5/3.3 V), spread-spectrum capability (0.5–5.0% at 33–63 kHz), and I²C/SMBus programmability with ClockBuilder Pro support.

Technical Context

The SI5338M-B10099-GM integrates a high-stability PLL-based synthesis stage followed by four independent MultiSynth™ fractional-N dividers, enabling true zero-ppm frequency accuracy on all outputs. Its architecture supports both free-running clock generation and synchronous frequency translation modes using up to six input references (differential, CMOS, SSTL/HSTL).

Each output driver features independent format selection (LVPECL/LVDS/HCSL/CMOS/SSTL/HSTL), programmable initial phase offset (±45 ns), and glitchless frequency increment/decrement (1 ppm steps). The device implements loss-of-lock and loss-of-signal alarms, external feedback for zero-delay mode, and configurable spread spectrum on any output.

Key Specifications

Parameter	Value and Actual Design Meaning
Phase Jitter (RMS)	0.7 ps typical (12 kHz–20 MHz); meets PCIe Gen 3 SRNS & Gen 4 common clock jitter requirements
Output Frequency Range	0.16–710 MHz per channel; supports LVPECL/LVDS up to 710 MHz, HCSL up to 250 MHz, CMOS up to 200 MHz
Input Reference Support	External crystal (8–30 MHz), CMOS (5–200 MHz), SSTL/HSTL (5–350 MHz), differential (5–710 MHz)
Supply Voltages	Core: 1.8/2.5/3.3 V ±10%; output buffers: independently configurable 1.5/1.8/2.5/3.3 V
Package	24-pin QFN, 4 × 4 mm, 0.5 mm pitch; RoHS-compliant, moisture sensitivity level 3
Operating Temperature	–40 to +85 °C ambient; validated for industrial and telecom line card environments
Power Consumption	45 mA typical core current at 100 MHz on all outputs with 25 MHz reference

Pinout & Package

SI5338M-B10099-GM uses a 24-pin QFN package (4 × 4 mm, 0.5 mm pitch) with exposed thermal pad. Pin functions are defined per Skyworks Rev. 1.6 datasheet, with dedicated inputs (IN1–IN6), four differential output pairs (CLK0A/B through CLK3A/B), three output supply rails (VDDO0–VDDO3), core supply (VDD), I²C interface (SCL/SDA), interrupt (INTR), and reserved ground (RSVD_GND).

Pin/Terminal	Circuit Role	Design Meaning
IN1, IN2	Differential input pair	Accepts 5–710 MHz AC-coupled differential clocks; requires external 100 Ω termination
IN3, IN4	Single-ended input pair	Supports 5–200 MHz CMOS-level clocks; VIH = 0.7×VDD, VIL = 0.3×VDD
CLK0A, CLK0B	Differential output pair	Configurable as LVPECL/LVDS/HCSL/CML/SSTL; independent voltage (VDDO0) and format
CLK1A, CLK1B	Differential output pair	Same configurability as CLK0; supports independent frequency, phase, and SSC settings
VDDO0–VDDO3	Output buffer supply rails	Each powers one output pair; enables mixed-voltage operation (e.g., 1.8 V LVDS + 3.3 V CMOS)
SCL, SDA	I²C serial interface	Standard-mode (100 kHz) and fast-mode (400 kHz) compatible; SMBus Level 2 compliant
INTR	Interrupt output	Open-drain active-low signal indicating loss-of-lock or loss-of-signal events

Key Features

Feature	Design Value
MultiSynth™ synthesis	Enables independent, any-frequency generation (0.16–710 MHz) on all four outputs with 0 ppm precision
PCIe Gen 1–4 compliance	Fully satisfies PCIe Gen 3 SRNS and Gen 4 common clock jitter specs (≤0.45 ps RMS) without external filtering
Independent output control	Per-output format, voltage, phase offset (±45 ns), frequency step (1 ppm), and spread-spectrum enablement
Flexible reference inputs	Supports six input types: crystal (8–30 MHz), CMOS, SSTL, HSTL, and two differential pairs (5–710 MHz)
Low-power operation	45 mA typical core current; <12 mA in buffer-only mode; optimized PSRR across 1.8/2.5/3.3 V supplies

Applications

PCIe Gen 4 Switch Timing	Ethernet Switch/Routing
Use Scenario: High-speed 16-lane PCIe Gen 4 switch IC requiring synchronized, low-jitter reference clocks for SerDes lanes and management logic. IC Role / Device Role / Timing Role: Primary clock generator providing four independent 100 MHz HCSL clocks with <0.45 ps RMS jitter and SRNS compliance. Use Value: Eliminates need for multiple discrete oscillators while meeting PCIe Gen 4 jitter mask requirements under varying load and temperature conditions.	Use Scenario: 10 GbE/25 GbE line card with multi-port switching ASIC and packet processor needing scalable, reconfigurable clock trees. IC Role / Device Role / Timing Role: Quad-output timing source delivering 156.25 MHz LVDS for PHY interfaces and 125 MHz CMOS for control logic. Use Value: Enables dynamic frequency scaling and phase alignment across ports via I²C during link training and power-state transitions.
Broadcast Video Timing	FPGA-Based Compute Acceleration
Use Scenario: SMPTE ST 2082-1 (12G-SDI) video processing system requiring precise 74.25 MHz and 148.5 MHz pixel clocks with sub-20 ps phase step resolution. IC Role / Device Role / Timing Role: Master clock synthesizer generating four synchronized video clocks with programmable phase offsets and jitter <1 ps RMS. Use Value: Ensures frame-accurate synchronization across multiple video encoders/decoders without external delay lines or PLLs.	Use Scenario: AI inference accelerator board with Xilinx Versal FPGA and high-bandwidth memory (HBM) requiring multiple domain-specific clocks (e.g., 300 MHz PL, 500 MHz HBM, 100 MHz AXI). IC Role / Device Role / Timing Role: Configurable clock hub providing independent, low-jitter clocks to FPGA fabric, memory controller, and host interface. Use Value: Reduces BOM count and PCB area versus discrete oscillator + buffer solutions while supporting runtime reconfiguration via I²C.

PCIe Gen 4 Switch Timing

Ethernet Switch/Routing

Use Scenario: High-speed 16-lane PCIe Gen 4 switch IC requiring synchronized, low-jitter reference clocks for SerDes lanes and management logic.

IC Role / Device Role / Timing Role: Primary clock generator providing four independent 100 MHz HCSL clocks with <0.45 ps RMS jitter and SRNS compliance.

Use Value: Eliminates need for multiple discrete oscillators while meeting PCIe Gen 4 jitter mask requirements under varying load and temperature conditions.

Use Scenario: 10 GbE/25 GbE line card with multi-port switching ASIC and packet processor needing scalable, reconfigurable clock trees.

IC Role / Device Role / Timing Role: Quad-output timing source delivering 156.25 MHz LVDS for PHY interfaces and 125 MHz CMOS for control logic.

Use Value: Enables dynamic frequency scaling and phase alignment across ports via I²C during link training and power-state transitions.

Broadcast Video Timing

FPGA-Based Compute Acceleration

Use Scenario: SMPTE ST 2082-1 (12G-SDI) video processing system requiring precise 74.25 MHz and 148.5 MHz pixel clocks with sub-20 ps phase step resolution.

IC Role / Device Role / Timing Role: Master clock synthesizer generating four synchronized video clocks with programmable phase offsets and jitter <1 ps RMS.

Use Value: Ensures frame-accurate synchronization across multiple video encoders/decoders without external delay lines or PLLs.

Use Scenario: AI inference accelerator board with Xilinx Versal FPGA and high-bandwidth memory (HBM) requiring multiple domain-specific clocks (e.g., 300 MHz PL, 500 MHz HBM, 100 MHz AXI).

IC Role / Device Role / Timing Role: Configurable clock hub providing independent, low-jitter clocks to FPGA fabric, memory controller, and host interface.

Use Value: Reduces BOM count and PCB area versus discrete oscillator + buffer solutions while supporting runtime reconfiguration via I²C.

Equivalent & Alternatives

The following parts are listed as comparable options for similar quad clock generator applications.

Alternative Part	Technical Difference	Application Difference	Selection Advice
Si5332A-D08189-GM	Higher integration: 8 outputs, integrated EEPROM, lower jitter (0.35 ps RMS), supports JESD204B deterministic latency	Targeted at JESD204B data converter timing and multi-ASIC systems requiring >4 outputs	Select when needing >4 outputs, deterministic latency, or factory pre-programming; not pin-compatible
ICS8430I-01T	Fixed-frequency, non-programmable; 4 LVDS outputs; 1.2 ps RMS jitter; no I²C interface or spread spectrum	Cost-sensitive, static-clocking applications where frequency flexibility is unnecessary	Select only for fixed-frequency deployments with no requirement for field reprogramming or jitter optimization

Compared with Si5332A-D08189-GM and ICS8430I-01T, the SI5338M-B10099-GM offers optimal balance of programmability, jitter performance, and footprint for mid-channel-count systems-enabling full frequency/phase/SSC configuration without sacrificing PCIe Gen 4 compliance or thermal efficiency.

Availability

SI5338M-B10099-GM is available at Aetrix Electronics and suitable for PCIe Gen 4 switch timing, Ethernet routing infrastructure, and broadcast video equipment requiring stable component supply, long-term lifecycle support, and traceable sourcing.

Supply support for SI5338M-B10099-GM includes scheduled delivery planning, volume procurement assistance, BOM continuity management, traceable sourcing, and lifecycle availability coordination for OEM customers, industrial embedded developers, connected-device designers, and electronics production programs.

Manufacturer

Skyworks Solutions is a global leader in analog semiconductors, specializing in RF, mobile, infrastructure, and timing solutions with over 40 years of RF and clocking innovation.

The Si5338 product line was designed for high-performance, software-configurable clock generation in datacenter, telecom, and broadcast systems-emphasizing jitter performance, multi-format flexibility, and ease of system integration via ClockBuilder Pro.

FAQ

What is the maximum output frequency supported by SI5338M-B10099-GM in LVPECL mode?

The SI5338M-B10099-GM supports up to 710 MHz in LVPECL mode per output channel, as specified in Table 6 of the Skyworks Rev. 1.6 datasheet. This capability enables direct clocking of high-speed SerDes lanes in PCIe Gen 4 and 10G/25G Ethernet applications without external frequency multiplication.

Does SI5338M-B10099-GM support PCIe Gen 4 Separate Reference No Spread (SRNS) compliance?

Yes, SI5338M-B10099-GM meets PCIe Gen 4 SRNS requirements with ≤0.32 ps RMS jitter (typical) when configured with PLL bandwidth of 2–4 MHz and CDR = 10 MHz, as verified in Table 12 of the official datasheet. This makes it suitable for root complex and endpoint timing in Gen 4 systems.

Can SI5338M-B10099-GM generate four different frequencies simultaneously?

Yes, SI5338M-B10099-GM uses four independent MultiSynth™ engines to synthesize four distinct output frequencies simultaneously-from 0.16 MHz to 710 MHz-with zero ppm error and independent format/voltage/phase control, as confirmed in the Functional Block Diagram and Section 3.4 of the datasheet.

What package type and dimensions does SI5338M-B10099-GM use?

SI5338M-B10099-GM uses a 24-pin QFN package measuring 4 × 4 mm with 0.5 mm pitch and an exposed thermal pad, per Package Outline document section 9 in the Skyworks Rev. 1.6 datasheet. This compact footprint supports high-density PCB layouts in space-constrained networking and compute modules.

Is ClockBuilder Pro software required to configure SI5338M-B10099-GM?

No, ClockBuilder Pro is optional but strongly recommended for SI5338M-B10099-GM configuration-it provides GUI-based frequency planning, jitter simulation, register mapping, and .c file generation. Direct I²C register writes are possible, but ClockBuilder Pro ensures correct initialization sequences and avoids configuration errors that could impact jitter or lock behavior.

SI5338M-B10099-GM Specifications

Product attributes: Attribute value

Manufacturer:: Skyworks Solutions Inc.

Series:: *

Package/Case:: -

Packaging:: Tray

Product Status:: Active

Programmable:: Not Verified

PLL:: -

Main Purpose:: -

Input:: -

Output:: -

Number of Circuits:: -

Ratio - Input:Output:: -

Differential - Input:Output:: -

Frequency - Max:: -

Voltage - Supply:: -

Operating Temperature:: -

Mounting Type:: -

Grade:: -

Qualification:: -

Supplier Device Package:: -

SI5338M-B10099-GM FAQ

1.How can I place an order for SI5338M-B10099-GM through Aetrix?

Please submit a Request for Quotation (RFQ) for SI5338M-B10099-GM on Aetrix. Our sales agent will provide a competitive quotation and guide you through the order confirmation once you accept the terms.

2.Are the price and stock information for SI5338M-B10099-GM reliable?

The price and inventory of SI5338M-B10099-GM are updated periodically and may fluctuate due to market conditions. Stock and pricing data are typically refreshed every 24 hours. Quotation validity for SI5338M-B10099-GM is usually 5 days.

3.What payment methods are accepted for SI5338M-B10099-GM?

We accept Wire Transfer, PayPal, Credit Card, Western Union, MoneyGram, and Escrow for SI5338M-B10099-GM transactions.

Note: Certain payment methods may incur a processing fee.

4.How is shipping managed for SI5338M-B10099-GM?

SI5338M-B10099-GM orders can be shipped via leading logistics carriers, including DHL, UPS, FedEx, TNT, or Registered Mail.

Once your SI5338M-B10099-GM order is processed, you will receive an email with the shipment details and tracking number.

Note: Tracking information may take up to 24 hours to appear. Express delivery typically takes 3–5 business days.

5.How can I obtain technical support or documentation for SI5338M-B10099-GM?

For technical support, including SI5338M-B10099-GM datasheets, pinout diagrams, or application guidance, please contact our engineering support team. They can provide detailed documentation and assistance for your SI5338M-B10099-GM requirements.

6.How does Aetrix verify that SI5338M-B10099-GM is sourced from the original manufacturer or authorized distributors?

All SI5338M-B10099-GM products on Aetrix are procured from qualified distributors and authorized channels. Our dedicated quality assurance team conducts strict verification, including traceability checks and, if necessary, third-party testing. This ensures that SI5338M-B10099-GM meets industry standards.

7.What is the process for return or replacement of SI5338M-B10099-GM?

All SI5338M-B10099-GM units undergo pre-shipment inspection (PSI). If there is an issue with SI5338M-B10099-GM, returns or replacements are accepted under the following conditions:

1.Quantity discrepancies, incorrect items, or visible external defects (such as breakage or corrosion), acknowledged by Aetrix.

2.The issue is reported within 90 days of delivery.

3.The SI5338M-B10099-GM part is unused and in its original packaging.

Return procedure for SI5338M-B10099-GM:

1.Submit a request within 90 days.

2.Obtain a Return Material Authorization (RMA) from Aetrix.

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