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Home > Products > Integrated Circuits (ICs) > Clock/Timing > Application Specific Clock/Timing

Skyworks Solutions Inc. SI5338M-B10099-GMR

Name: SI5338M-B10099-GMR
Brand: Skyworks Solutions Inc.
SKU: SI5338M-B10099-GMR
Price: 2.40 USD
Availability: InStock
Rating: 5 (2 reviews)

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Part No.:: SI5338M-B10099-GMR

Manufacturer:: Skyworks Solutions Inc.

Category:: Application Specific Clock/Timing

Package:: -

Datasheet:: SI5338M-B10099-GMR.pdf

Description:: IC CLOCK GENERATOR QUAD 24QFN

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Product details

Overview

SI5338M-B10099-GMR from Skyworks Solutions is a quad-output, I²C-programmable clock generator implementing MultiSynth™ frequency synthesis with 0 ppm precision per output. It delivers four independent differential or single-ended clocks (LVPECL/LVDS/HCSL/CMOS/SSTL/HSTL) across 0.16–710 MHz, supports PCIe Gen 1–4 common clock and SRNS compliance, and operates from 1.8/2.5/3.3 V core supply in a 4 × 4 mm 24-QFN package for FPGA, processor, and Ethernet switch timing.

For engineers reviewing the SI5338M-B10099-GMR datasheet, SI5338M-B10099-GMR pinout, SI5338M-B10099-GMR application, or SI5338M-B10099-GMR equivalent, key selection criteria include its 0.7 ps RMS typical phase jitter, independent per-output voltage (1.5–3.3 V), glitchless 1 ppm frequency increment/decrement, <20 ps phase step resolution, and PCIe Gen 4-compliant jitter performance at 100 MHz HCSL.

Technical Context

The SI5338M-B10099-GMR integrates a two-stage PLL architecture: a high-stability reference stage (with crystal or external clock input up to 710 MHz) followed by four independent MultiSynth™ fractional-N synthesizers. Each synthesizer drives a configurable output stage supporting mixed signal formats and voltages.

It features loss-of-lock and loss-of-signal detection, programmable initial phase offset (±45 ns), spread-spectrum control (0.5–5.0% spread, 33–63 kHz modulation), and external feedback mode for zero-delay operation - all managed via I²C/SMBus interface with ClockBuilder Pro configuration software.

Key Specifications

Parameter	Value and Actual Design Meaning
Phase Jitter (RMS)	0.7 ps typical (12 kHz–20 MHz); meets PCIe Gen 3/4 SRNS and GbE jitter requirements
Output Frequency Range	0.16–710 MHz per channel; supports up to two outputs >350 MHz simultaneously (Fvco/4 & Fvco/6)
Input Reference Support	Crystal (8–30 MHz), CMOS (5–200 MHz), SSTL/HSTL (5–350 MHz), differential (5–710 MHz)
Output Format Flexibility	LVPECL, LVDS, HCSL, CML, CMOS, SSTL, HSTL - each output independently configurable
Per-Output Supply Voltage	1.5 V, 1.8 V, 2.5 V, or 3.3 V; enables mixed-voltage system clock distribution without level shifters
Core Supply Current	45 mA typical at 100 MHz on all outputs and 25 MHz refclk; optimized for low-power embedded timing
Operating Temperature	–40 °C to +85 °C; qualified for industrial and telecom line card environments

Pinout & Package

SI5338M-B10099-GMR is housed in a 4 mm × 4 mm, 24-pin QFN package with exposed thermal pad (GND). Pin assignments follow standard Si5338 top-view layout: IN1/IN2 (diff clk 1), IN3/IN4 (SE clk 1/2), IN5/IN6 (diff clk 2/3), CLK0A/CLK0B through CLK3A/CLK3B (four differential outputs), VDDO0–VDDO3 (independent output supply pins), VDD (core supply), SCL/SDA/INTR (I²C interface), and RSVD_GND.

Pin/Terminal	Circuit Role	Design Meaning
CLK0A / CLK0B	Differential Output Pair 0	LVPECL/LVDS/HCSL/CML-capable; independently configured frequency, format, and VDDO0 voltage
CLK1A / CLK1B	Differential Output Pair 1	Same configurability as CLK0; supports integer/fractional synthesis with <20 ps phase step resolution
CLK2A / CLK2B	Differential Output Pair 2	Programmable skew and phase offset relative to other outputs; supports PCIe Gen 4 common clock alignment
CLK3A / CLK3B	Differential Output Pair 3	Configurable for SRNS mode; enables independent spread-spectrum modulation (0.5–5.0%, 33–63 kHz)
VDDO0–VDDO3	Independent Output Buffer Supplies	Each powers one output pair; allows mixed-voltage clocking (e.g., 1.8 V FPGA + 3.3 V PHY)
SCL / SDA	I²C Serial Interface	Standard SMBus-compatible bus; used with ClockBuilder Pro for register-level configuration and NVM programming
INTR	Interrupt Output	Open-drain status flag for loss-of-lock, loss-of-signal, or programmable alarm conditions
IN1 / IN2	Differential Reference Input 1	Accepts 5–710 MHz AC-coupled differential clock; internal 10 kΩ termination and 3.5 pF capacitance

Key Features

Feature	Design Value
MultiSynth™ Synthesis	Four independent fractional-N synthesizers enabling true zero-ppm accuracy on all outputs without external crystals
PCIe Gen 4 Compliance	0.15–0.45 ps RMS jitter in common-clock mode (100 MHz HCSL); validated per PCI Express Base Spec 4.0 rev 0.5
Glitchless Frequency Tuning	1 ppm incremental/decremental steps via PINC/FDEC pins or I²C; no output interruption during adjustment
Programmable Phase Offset	±45 ns range with <20 ps step resolution; enables precise inter-output skew control for SerDes lane alignment
Flexible Spread Spectrum	Configurable on any output: 0.5–5.0% down-spread, 33–63 kHz modulation rate; reduces EMI in dense PCB layouts
External Feedback Mode	Supports zero-delay buffer operation using external clock feedback path; eliminates propagation delay in timing-critical loops

Applications

Processor Clocking	FPGA Timing
Use Scenario: Providing synchronized, low-jitter clocks to multi-core SoCs and companion peripherals in industrial control systems. IC Role / Device Role / Timing Role: Primary clock source generating CPU, DDR, and peripheral clocks with independent voltage and format control. Use Value: Eliminates need for multiple discrete oscillators; enables dynamic frequency scaling with glitchless 1 ppm tuning for power-aware operation.	Use Scenario: Delivering precisely aligned clocks to high-speed transceivers, memory interfaces, and logic fabric in Xilinx/Intel FPGA-based video processing platforms. IC Role / Device Role / Timing Role: Quad-output timing hub with sub-20 ps phase step resolution for SerDes lane deskew and DDR3/4 PHY clocking. Use Value: Meets PCIe Gen 4 SRNS jitter spec (0.11–0.32 ps RMS) and supports HCSL/LVDS outputs directly compatible with FPGA clock inputs.
Ethernet Switch Timing	Telecom Line Card Sync
Use Scenario: Generating 125 MHz, 156.25 MHz, and 312.5 MHz clocks for 1/10 GbE PHYs, packet processors, and switch fabric in enterprise routers. IC Role / Device Role / Timing Role: Any-frequency clock converter translating a 25 MHz crystal reference into multiple Ethernet-standard frequencies. Use Value: Achieves 0.7 ps RMS random jitter (GbE band), satisfying IEEE 802.3 clause 40/49 requirements without external jitter cleaners.	Use Scenario: Distributing synchronized, low-phase-noise clocks across DSPs, ADCs, DACs, and framer ICs in OTN/SONET line cards. IC Role / Device Role / Timing Role: High-stability clock generator supporting OC-12 (155.52 MHz) and synchronous Ethernet (25/125 MHz) with deterministic jitter <10 ps pk-pk. Use Value: Delivers 0.7 ps RMS OC-12 jitter and supports external crystal input (8–30 MHz) with on-chip load capacitance tuning for telecom-grade stability.

Processor Clocking

FPGA Timing

Use Scenario: Providing synchronized, low-jitter clocks to multi-core SoCs and companion peripherals in industrial control systems.

IC Role / Device Role / Timing Role: Primary clock source generating CPU, DDR, and peripheral clocks with independent voltage and format control.

Use Value: Eliminates need for multiple discrete oscillators; enables dynamic frequency scaling with glitchless 1 ppm tuning for power-aware operation.

Use Scenario: Delivering precisely aligned clocks to high-speed transceivers, memory interfaces, and logic fabric in Xilinx/Intel FPGA-based video processing platforms.

IC Role / Device Role / Timing Role: Quad-output timing hub with sub-20 ps phase step resolution for SerDes lane deskew and DDR3/4 PHY clocking.

Use Value: Meets PCIe Gen 4 SRNS jitter spec (0.11–0.32 ps RMS) and supports HCSL/LVDS outputs directly compatible with FPGA clock inputs.

Ethernet Switch Timing

Telecom Line Card Sync

Use Scenario: Generating 125 MHz, 156.25 MHz, and 312.5 MHz clocks for 1/10 GbE PHYs, packet processors, and switch fabric in enterprise routers.

IC Role / Device Role / Timing Role: Any-frequency clock converter translating a 25 MHz crystal reference into multiple Ethernet-standard frequencies.

Use Value: Achieves 0.7 ps RMS random jitter (GbE band), satisfying IEEE 802.3 clause 40/49 requirements without external jitter cleaners.

Use Scenario: Distributing synchronized, low-phase-noise clocks across DSPs, ADCs, DACs, and framer ICs in OTN/SONET line cards.

IC Role / Device Role / Timing Role: High-stability clock generator supporting OC-12 (155.52 MHz) and synchronous Ethernet (25/125 MHz) with deterministic jitter <10 ps pk-pk.

Use Value: Delivers 0.7 ps RMS OC-12 jitter and supports external crystal input (8–30 MHz) with on-chip load capacitance tuning for telecom-grade stability.

Equivalent & Alternatives

The following parts are listed as comparable options for similar quad-output programmable clock generator applications.

Alternative Part	Technical Difference	Application Difference	Selection Advice
Si5332A-D07189-GM	Higher integration: 8 outputs, integrated LDOs, lower jitter (0.35 ps RMS), but larger 5×5 mm 32-QFN package	Better suited for multi-ASIC timing in AI accelerators or high-port switches requiring >4 clocks	Select when needing >4 outputs or ultra-low jitter; avoid if board space or cost sensitivity favors 24-QFN footprint
ICS8430I-01T	Fixed-frequency, non-programmable quad LVDS clock fanout buffer; no synthesis, no I²C, 1.2 ps RMS jitter	Limited to pre-defined frequencies; no spread spectrum or phase adjustment capability	Choose only for simple clock distribution where frequency flexibility and advanced features are unnecessary

Compared with SI5338M-B10099-GMR, the Si5332A offers higher output count and lower jitter at the cost of size and complexity, while the ICS8430I-01T provides simpler, lower-cost buffering without programmability - making SI5338M-B10099-GMR optimal for designs requiring field-configurable, low-jitter, multi-format clock synthesis in compact form factor.

Availability

SI5338M-B10099-GMR is available at Aetrix Electronics and suitable for FPGA timing, PCIe Gen 4 endpoint clocking, and Ethernet switch/router applications requiring stable component supply, long-term lifecycle support, and guaranteed traceable sourcing.

Supply support for SI5338M-B10099-GMR includes scheduled delivery planning, volume procurement assistance, BOM continuity management, traceable sourcing, and lifecycle availability coordination for OEM customers, industrial embedded developers, connected-device designers, and electronics production programs.

Manufacturer

Skyworks Solutions is a global leader in analog and mixed-signal semiconductors, specializing in RF, mobile, infrastructure, and timing solutions with over 30 years of RF and clocking innovation.

The Si5338 product line was designed for high-performance, flexible clock generation in datacenter, networking, and communications equipment - delivering programmable, low-jitter timing with minimal board space and design effort.

FAQ

What is the primary function of the SI5338M-B10099-GMR?

The SI5338M-B10099-GMR is a quad-output, I²C-programmable clock generator that synthesizes any frequency from 0.16 MHz to 710 MHz on each output using Skyworks' MultiSynth™ technology. It replaces multiple fixed-frequency oscillators and supports PCIe Gen 1–4, Ethernet, and telecom timing standards - all within a single 4 × 4 mm QFN package. Its core function is providing precise, flexible, low-jitter clock signals for FPGAs, processors, and high-speed serial interfaces.

Does the SI5338M-B10099-GMR support PCIe Gen 4 timing requirements?

Yes, the SI5338M-B10099-GMR meets PCIe Gen 4 common clock jitter specifications with 0.15–0.45 ps RMS (12 kHz–20 MHz) when configured for 100 MHz HCSL outputs and appropriate PLL bandwidth (2–4 MHz). It is explicitly validated per PCI Express Base Specification 4.0 rev 0.5 and supports both common clock and SRNS modes - confirmed in Skyworks' Rev. 1.6 datasheet Table 12 and functional description section 3.10.

Can the SI5338M-B10099-GMR generate different output formats simultaneously?

Yes, the SI5338M-B10099-GMR supports simultaneous mixed-signal outputs: each of its four differential pairs (CLK0–CLK3) can be independently configured for LVPECL, LVDS, HCSL, CML, CMOS, SSTL, or HSTL. For example, CLK0A/B may drive an FPGA with LVDS, while CLK2A/B supplies a PHY with HCSL - all from the same SI5338M-B10099-GMR device without external level shifters.

How is the SI5338M-B10099-GMR programmed and configured?

The SI5338M-B10099-GMR is programmed via its I²C/SMBus-compatible interface (SCL/SDA pins) using Skyworks' ClockBuilder Pro software. This GUI tool generates custom configuration files, writes them to on-chip OTP NVM, and supports real-time register updates. Configuration includes output frequencies, formats, voltages, spread spectrum, phase offsets, and alarm thresholds - all verified against the device's internal synthesis engine before committing.

What package type and pin count does the SI5338M-B10099-GMR use?

The SI5338M-B10099-GMR uses a 4 mm × 4 mm, 24-pin QFN package with exposed thermal pad (GND). Its pinout includes four differential output pairs (CLK0A/B through CLK3A/B), six dedicated input pins (IN1–IN6), four independent VDDO supply pins (VDDO0–VDDO3), core VDD, I²C interface (SCL/SDA), interrupt output (INTR), and reserved ground (RSVD_GND) - matching the standard Si5338 24-QFN mechanical outline in Skyworks' datasheet Section 9.

SI5338M-B10099-GMR Specifications

Product attributes: Attribute value

Manufacturer:: Skyworks Solutions Inc.

Series:: *

Package/Case:: -

Packaging:: Tape & Reel (TR)

Product Status:: Active

Programmable:: Not Verified

PLL:: -

Main Purpose:: -

Input:: -

Output:: -

Number of Circuits:: -

Ratio - Input:Output:: -

Differential - Input:Output:: -

Frequency - Max:: -

Voltage - Supply:: -

Operating Temperature:: -

Mounting Type:: -

Grade:: -

Qualification:: -

Supplier Device Package:: -

SI5338M-B10099-GMR FAQ

1.How can I place an order for SI5338M-B10099-GMR through Aetrix?

Please submit a Request for Quotation (RFQ) for SI5338M-B10099-GMR on Aetrix. Our sales agent will provide a competitive quotation and guide you through the order confirmation once you accept the terms.

2.Are the price and stock information for SI5338M-B10099-GMR reliable?

The price and inventory of SI5338M-B10099-GMR are updated periodically and may fluctuate due to market conditions. Stock and pricing data are typically refreshed every 24 hours. Quotation validity for SI5338M-B10099-GMR is usually 5 days.

3.What payment methods are accepted for SI5338M-B10099-GMR?

We accept Wire Transfer, PayPal, Credit Card, Western Union, MoneyGram, and Escrow for SI5338M-B10099-GMR transactions.

Note: Certain payment methods may incur a processing fee.

4.How is shipping managed for SI5338M-B10099-GMR?

SI5338M-B10099-GMR orders can be shipped via leading logistics carriers, including DHL, UPS, FedEx, TNT, or Registered Mail.

Once your SI5338M-B10099-GMR order is processed, you will receive an email with the shipment details and tracking number.

Note: Tracking information may take up to 24 hours to appear. Express delivery typically takes 3–5 business days.

5.How can I obtain technical support or documentation for SI5338M-B10099-GMR?

For technical support, including SI5338M-B10099-GMR datasheets, pinout diagrams, or application guidance, please contact our engineering support team. They can provide detailed documentation and assistance for your SI5338M-B10099-GMR requirements.

6.How does Aetrix verify that SI5338M-B10099-GMR is sourced from the original manufacturer or authorized distributors?

All SI5338M-B10099-GMR products on Aetrix are procured from qualified distributors and authorized channels. Our dedicated quality assurance team conducts strict verification, including traceability checks and, if necessary, third-party testing. This ensures that SI5338M-B10099-GMR meets industry standards.

7.What is the process for return or replacement of SI5338M-B10099-GMR?

All SI5338M-B10099-GMR units undergo pre-shipment inspection (PSI). If there is an issue with SI5338M-B10099-GMR, returns or replacements are accepted under the following conditions:

1.Quantity discrepancies, incorrect items, or visible external defects (such as breakage or corrosion), acknowledged by Aetrix.

2.The issue is reported within 90 days of delivery.

3.The SI5338M-B10099-GMR part is unused and in its original packaging.

Return procedure for SI5338M-B10099-GMR:

1.Submit a request within 90 days.

2.Obtain a Return Material Authorization (RMA) from Aetrix.

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