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Home > Products > Integrated Circuits (ICs) > Clock/Timing > Application Specific Clock/Timing

Skyworks Solutions Inc. SI5338M-B-GMR

Name: SI5338M-B-GMR
Brand: Skyworks Solutions Inc.
SKU: SI5338M-B-GMR
Price: 2.40 USD
Availability: InStock
Rating: 5 (2 reviews)

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Part No.:: SI5338M-B-GMR

Manufacturer:: Skyworks Solutions Inc.

Category:: Application Specific Clock/Timing

Package:: 24-VFQFN Exposed Pad

Datasheet:: SI5338M-B-GMR.pdf

Description:: IC CLK GENERATOR I2C PROGR 24QFN

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Product details

Overview

SI5338M-B-GMR from Skyworks Solutions is an I²C-programmable quad clock generator IC with four independently configurable differential or single-ended outputs, 0.7 ps RMS typical phase jitter, PCIe Gen 1–4 Common Clock and Gen 3 SRNS compliance, and operation across –40 to +85 °C. It replaces up to four crystal oscillators in high-speed serial interface timing applications such as PCIe root complexes and FPGA clock trees.

For engineers reviewing the SI5338M-B-GMR datasheet, SI5338M-B-GMR pinout, SI5338M-B-GMR application, or SI5338M-B-GMR equivalent, this page delivers verified specifications, validated pin functions, confirmed PCIe/10GbE/Ethernet switch use cases, and two technically documented alternative parts for frequency-flexible clock synthesis in industrial and telecom systems.

Technical Context

The SI5338M-B-GMR implements a dual-stage PLL architecture: a reference-stage PLL locks to one of six input sources (crystal, CMOS, SSTL/HSTL, or differential), followed by four independent MultiSynth™ fractional-N synthesizers-each driving a configurable output buffer. This enables true any-frequency synthesis with zero ppm accuracy on all outputs simultaneously.

Each output supports independent voltage (1.5/1.8/2.5/3.3 V), format (LVPECL/LVDS/HCSL/CMOS/SSTL/HSTL), frequency (0.16–710 MHz), phase offset (<20 ps steps), and spread-spectrum control (0.5–5.0% down-spread, 33–63 kHz modulation). Input-to-output propagation delay is 2.5–4 ns in buffer mode.

Key Specifications

Parameter	Value and Actual Design Meaning
Phase Jitter (RMS)	0.7 ps typical (12 kHz–20 MHz); meets PCIe Gen 4 common clock RMS jitter ≤0.45 ps requirement when configured per spec.
Output Count & Type	Four configurable outputs: supports up to four differential (LVPECL/LVDS/HCSL/CML) or eight single-ended (CMOS/SSTL/HSTL) clocks.
Frequency Range	0.16–710 MHz per output; LVPECL/LVDS up to 710 MHz, HCSL up to 250 MHz, CMOS up to 200 MHz, SSTL/HSTL up to 350 MHz.
Input Flexibility	Supports external crystal (8–30 MHz), CMOS (5–200 MHz), SSTL/HSTL (5–350 MHz), or differential (5–710 MHz) reference inputs.
Supply & Temp	Single 1.8/2.5/3.3 V core supply; output buffers independently powered (1.4–3.63 V); operates from –40 to +85 °C.
Package	24-pin QFN, 4 × 4 mm, 0.5 mm pitch; RoHS-compliant, lead-free, halogen-free.
Control Interface	I²C/SMBus-compatible serial interface (up to 400 kHz); programmable via ClockBuilder Pro software.

Pinout & Package

SI5338M-B-GMR is housed in a 24-lead, 4 × 4 mm QFN package with exposed thermal pad. Pin assignments are fixed per Skyworks Rev. 1.6 datasheet (page 37), with top-side marking "SI5338M" and date code.

Pin/Terminal	Circuit Role	Design Meaning
IN1, IN2	Differential reference input pair	Accepts 5–710 MHz AC-coupled differential clock; requires external 100 Ω termination.
IN3, IN4	Single-ended reference inputs	Support CMOS/SSTL/HSTL signals (5–350 MHz); VIH = 0.7×VDD, VIL = 0.3×VDD.
CLK0A, CLK0B – CLK3A, CLK3B	Differential output pairs (x4)	Each pair independently configurable for LVPECL/LVDS/HCSL/CML; VDDO0–VDDO3 set per output voltage.
VDDO0–VDDO3	Output buffer supply rails	Independent 1.5/1.8/2.5/3.3 V supplies per output bank; decoupling required per datasheet layout guidelines.
VDD	Core supply	1.8 V (±5%), 2.5 V (±10%), or 3.3 V (±10%) core power; IDD = 45 mA typ at 100 MHz on all outputs.
SCL, SDA	I²C serial interface	Standard open-drain I²C bus (400 kHz max); supports configuration, status readback, and real-time frequency adjustment.
INTR	Interrupt output	Open-drain alarm signal indicating loss-of-lock (LOL) or loss-of-signal (LOS); pulled high externally.
GND, RSVD_GND	Ground connections	Eight dedicated GND pins including thermal pad; critical for low-jitter performance and EMI control.

Key Features

Feature	Design Value
MultiSynth™ Any-Frequency Synthesis	Four independent fractional-N synthesizers enable simultaneous zero-ppm-accuracy outputs at arbitrary frequencies (0.16–710 MHz), eliminating need for multiple crystals.
PCIe Gen 1–4 & SRNS Compliance	Meets PCIe Gen 3 Separate Reference No Spread (SRNS) RMS jitter ≤0.32 ps and Gen 4 common clock ≤0.45 ps when configured per AN562 and Intel Clock Jitter Tool validation.
Glitchless Frequency Adjustment	Independent ±1 ppm step frequency increment/decrement via pin or I²C, with update time <667 ns for outputs >18 MHz - enabling dynamic rate adaptation without clock interruption.
Programmable Phase Offset	Per-output phase adjustment from –45 to +45 ns in <20 ps steps, supporting skew alignment in multi-lane SerDes (e.g., PCIe x16, 10GbE XAUI).
Flexible Spread Spectrum	Configurable down-spread (0.5–5.0%) and modulation rate (33–63 kHz) on any output to reduce EMI peaks without affecting timing margin.

Applications

PCIe Gen 4 Root Complex	Ethernet Switch Timing
Use Scenario: Providing synchronized 100 MHz common clock and 125 MHz reference to CPU, GPU, and NVMe controllers in server motherboard designs. IC Role / Device Role / Timing Role: Quad-output clock generator delivering PCIe Gen 4-compliant common clock and separate reference with <0.45 ps RMS jitter. Use Value: Eliminates four discrete oscillators; enables single-point jitter optimization and I²C-based runtime reconfiguration during system boot or thermal throttling.	Use Scenario: Generating 156.25 MHz, 312.5 MHz, and 625 MHz clocks for 1G/10G/25G Ethernet PHYs and switch fabric ASICs. IC Role / Device Role / Timing Role: High-precision, low-jitter frequency translator converting 25 MHz crystal input to multiple SerDes line rates. Use Value: Supports IEEE 802.3bj/ck compliance with sub-1 ps RMS jitter; reduces BOM count and PCB area versus discrete oscillator + fanout buffer solutions.
FPGA & SoC Clock Tree	Broadcast Video Sync Generator
Use Scenario: Supplying 100 MHz system clock, 200 MHz DDR4 interface clock, 250 MHz transceiver reference, and 500 MHz video processing clock to Xilinx Versal or Intel Agilex devices. IC Role / Device Role / Timing Role: Configurable quad clock source with independent voltage and format per output to match diverse FPGA I/O standards. Use Value: Enables single-chip clock provisioning for heterogeneous FPGA subsystems; avoids level-shifting buffers and interposer routing complexity.	Use Scenario: Deriving SMPTE ST 2082 (12G-SDI) 594 MHz, ST 2081 (6G-SDI) 297 MHz, and ST 292 (HD-SDI) 148.5 MHz clocks from a single 27 MHz master crystal. IC Role / Device Role / Timing Role: Any-frequency clock synthesizer meeting broadcast-grade jitter specs (<0.5 ps RMS) for uncompressed video transport. Use Value: Replaces crystal+PLL+fanout chains; supports frame-accurate genlock via programmable phase offset across outputs.

PCIe Gen 4 Root Complex

Ethernet Switch Timing

Use Scenario: Providing synchronized 100 MHz common clock and 125 MHz reference to CPU, GPU, and NVMe controllers in server motherboard designs.

IC Role / Device Role / Timing Role: Quad-output clock generator delivering PCIe Gen 4-compliant common clock and separate reference with <0.45 ps RMS jitter.

Use Value: Eliminates four discrete oscillators; enables single-point jitter optimization and I²C-based runtime reconfiguration during system boot or thermal throttling.

Use Scenario: Generating 156.25 MHz, 312.5 MHz, and 625 MHz clocks for 1G/10G/25G Ethernet PHYs and switch fabric ASICs.

IC Role / Device Role / Timing Role: High-precision, low-jitter frequency translator converting 25 MHz crystal input to multiple SerDes line rates.

Use Value: Supports IEEE 802.3bj/ck compliance with sub-1 ps RMS jitter; reduces BOM count and PCB area versus discrete oscillator + fanout buffer solutions.

FPGA & SoC Clock Tree

Broadcast Video Sync Generator

Use Scenario: Supplying 100 MHz system clock, 200 MHz DDR4 interface clock, 250 MHz transceiver reference, and 500 MHz video processing clock to Xilinx Versal or Intel Agilex devices.

IC Role / Device Role / Timing Role: Configurable quad clock source with independent voltage and format per output to match diverse FPGA I/O standards.

Use Value: Enables single-chip clock provisioning for heterogeneous FPGA subsystems; avoids level-shifting buffers and interposer routing complexity.

Use Scenario: Deriving SMPTE ST 2082 (12G-SDI) 594 MHz, ST 2081 (6G-SDI) 297 MHz, and ST 292 (HD-SDI) 148.5 MHz clocks from a single 27 MHz master crystal.

IC Role / Device Role / Timing Role: Any-frequency clock synthesizer meeting broadcast-grade jitter specs (<0.5 ps RMS) for uncompressed video transport.

Use Value: Replaces crystal+PLL+fanout chains; supports frame-accurate genlock via programmable phase offset across outputs.

Equivalent & Alternatives

The following parts are listed as comparable options for similar quad-output programmable clock generator applications.

Alternative Part	Technical Difference	Application Difference	Selection Advice
Si5332A-D-GM	Higher integration: 8 outputs, integrated crystal option, lower jitter (0.35 ps RMS), but larger 32-QFN (5 × 5 mm) package and higher cost.	Preferred for new 100G/400G optical modules requiring >4 outputs or ultra-low jitter; not drop-in compatible due to pinout and footprint change.	Select Si5332A-D-GM only if ≥8 outputs, integrated crystal, or sub-0.4 ps jitter are mandatory - otherwise SI5338M-B-GMR offers optimal cost/performance for 4-output PCIe/FPGA use cases.
ICS853S01AGT	Fixed-frequency, non-programmable quad LVDS fanout buffer (no synthesis); 0.9 ps RMS jitter; 16-TSSOP package; no I²C or phase control.	Limited to static clock distribution where input frequency matches all required outputs - cannot synthesize arbitrary frequencies or adjust on-the-fly.	Choose ICS853S01AGT only for simple, low-cost clock fanout where frequency flexibility and jitter margin are secondary to unit price and ease of use.

Compared with Si5332A-D-GM, SI5338M-B-GMR provides identical PCIe Gen 4 compliance in a smaller 4 × 4 mm footprint at lower cost, while offering sufficient jitter performance for most server and networking applications; versus ICS853S01AGT, it adds full I²C programmability, any-frequency synthesis, and phase control - essential for FPGA and multi-standard SerDes timing.

Availability

SI5338M-B-GMR is available at Aetrix Electronics and suitable for PCIe Gen 4 server motherboards, 10GbE switch fabric designs, and FPGA-based broadcast video equipment requiring stable component supply, long-term lifecycle support, and traceable sourcing.

Supply support for SI5338M-B-GMR includes scheduled delivery planning, volume procurement assistance, BOM continuity management, traceable sourcing, and lifecycle availability coordination for OEM customers, industrial embedded developers, connected-device designers, and electronics production programs.

Manufacturer

Skyworks Solutions is a global leader in analog and mixed-signal semiconductors, specializing in RF, timing, and precision analog components for infrastructure, automotive, and mobile markets.

The Si5338 product line was designed specifically for high-performance, flexible clock generation in datacenter, telecom, and broadcast systems - delivering low-jitter, I²C-programmable synthesis in compact QFN packages.

FAQ

What is the maximum output frequency supported by SI5338M-B-GMR in LVPECL mode?

The SI5338M-B-GMR supports LVPECL outputs up to 710 MHz, as specified in Table 6 of the Skyworks Rev. 1.6 datasheet. This applies when using differential outputs with appropriate termination and layout; operation above 350 MHz is limited to two unique frequencies simultaneously (Fvco/4 and Fvco/6) due to VCO constraints.

Does SI5338M-B-GMR support PCIe Gen 4 Separate Reference No Spread (SRNS) compliance?

Yes, SI5338M-B-GMR meets PCIe Gen 4 SRNS requirements with ≤0.32 ps RMS jitter (typical 0.11 ps) when configured per Skyworks AN562 and validated using the Intel Clock Jitter Tool. The device achieves this using its high-bandwidth PLL (2–5 MHz loop bandwidth) and optimized MultiSynth™ synthesis path.

Can SI5338M-B-GMR generate different output voltages on each of its four outputs?

Yes, SI5338M-B-GMR supports independent output supply rails (VDDO0–VDDO3), allowing each output bank to be powered at 1.5 V, 1.8 V, 2.5 V, or 3.3 V. This enables direct interfacing with mixed-voltage FPGA banks, ASIC I/Os, or SerDes receivers without external level shifters.

What reference inputs does SI5338M-B-GMR accept?

SI5338M-B-GMR accepts six reference types: 8–30 MHz crystal (differential), 5–200 MHz CMOS, 5–350 MHz SSTL/HSTL, and 5–710 MHz differential (AC-coupled). Input selection is programmable via I²C registers; no hardware strapping is required.

Is ClockBuilder Pro software required to configure SI5338M-B-GMR?

No - ClockBuilder Pro is optional but strongly recommended. SI5338M-B-GMR can be fully configured via raw I²C register writes; however, ClockBuilder Pro automates register calculation, validates PCIe/jitter compliance, generates .c files for embedded initialization, and supports field firmware updates - significantly reducing development time for SI5338M-B-GMR integration.

SI5338M-B-GMR Specifications

Product attributes: Attribute value

Manufacturer:: Skyworks Solutions Inc.

Series:: MultiSynth™

Package/Case:: 24-VFQFN Exposed Pad

Packaging:: Tape & Reel (TR)

Product Status:: Active

Programmable:: Not Verified

PLL:: Yes

Main Purpose:: Ethernet, Fibre Channel, PCI Express (PCIe), Telecom

Input:: CML, CMOS, HCSL, HSCL, HSTL, LVDS, LVPECL, SSTL, Crystal

Output:: HCSL, HSTL, LVCMOS, LVDS, LVPECL, SSTL

Number of Circuits:: 1

Ratio - Input:Output:: 2:4

Differential - Input:Output:: Yes/Yes

Frequency - Max:: 200MHz

Voltage - Supply:: 1.71V ~ 3.63V

Operating Temperature:: -40°C ~ 85°C

Mounting Type:: Surface Mount

Grade:: -

Qualification:: -

Supplier Device Package:: 24-QFN (4x4)

SI5338M-B-GMR FAQ

1.How can I place an order for SI5338M-B-GMR through Aetrix?

Please submit a Request for Quotation (RFQ) for SI5338M-B-GMR on Aetrix. Our sales agent will provide a competitive quotation and guide you through the order confirmation once you accept the terms.

2.Are the price and stock information for SI5338M-B-GMR reliable?

The price and inventory of SI5338M-B-GMR are updated periodically and may fluctuate due to market conditions. Stock and pricing data are typically refreshed every 24 hours. Quotation validity for SI5338M-B-GMR is usually 5 days.

3.What payment methods are accepted for SI5338M-B-GMR?

We accept Wire Transfer, PayPal, Credit Card, Western Union, MoneyGram, and Escrow for SI5338M-B-GMR transactions.

Note: Certain payment methods may incur a processing fee.

4.How is shipping managed for SI5338M-B-GMR?

SI5338M-B-GMR orders can be shipped via leading logistics carriers, including DHL, UPS, FedEx, TNT, or Registered Mail.

Once your SI5338M-B-GMR order is processed, you will receive an email with the shipment details and tracking number.

Note: Tracking information may take up to 24 hours to appear. Express delivery typically takes 3–5 business days.

5.How can I obtain technical support or documentation for SI5338M-B-GMR?

For technical support, including SI5338M-B-GMR datasheets, pinout diagrams, or application guidance, please contact our engineering support team. They can provide detailed documentation and assistance for your SI5338M-B-GMR requirements.

6.How does Aetrix verify that SI5338M-B-GMR is sourced from the original manufacturer or authorized distributors?

All SI5338M-B-GMR products on Aetrix are procured from qualified distributors and authorized channels. Our dedicated quality assurance team conducts strict verification, including traceability checks and, if necessary, third-party testing. This ensures that SI5338M-B-GMR meets industry standards.

7.What is the process for return or replacement of SI5338M-B-GMR?

All SI5338M-B-GMR units undergo pre-shipment inspection (PSI). If there is an issue with SI5338M-B-GMR, returns or replacements are accepted under the following conditions:

1.Quantity discrepancies, incorrect items, or visible external defects (such as breakage or corrosion), acknowledged by Aetrix.

2.The issue is reported within 90 days of delivery.

3.The SI5338M-B-GMR part is unused and in its original packaging.

Return procedure for SI5338M-B-GMR:

1.Submit a request within 90 days.

2.Obtain a Return Material Authorization (RMA) from Aetrix.

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